EE 367 Logic Design Lecture #21

Agenda
1. Counters

Announcements (Monday, 3/24)

1. n/a

EE 367 Logic Design Spring 2008

Lecture #21 Page 1

Counters
Counters
- special name of any clocked sequential circuit whose state diagram is a circle - there are many types of counters, each suited for particular applications

EE 367 Logic Design Spring 2008

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Counters
Binary Counter
- state machine that produces a straight binary count - for n-flip-flops, 2n counts can be produced - the Next State Logic "F" is a combinational SOP/POS circuit - the speed will be limited by the Setup/Hold and Combinational Delay of "F" - this gives the maximum number of counts for n-flip flops

EE 367 Logic Design Spring 2008

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Counters
Toggle Flop
- a D-Flip-Flop can product a "Divide-by-2" effect by feeding back Qn to D - this topology is also called a "Toggle Flop"

EE 367 Logic Design Spring 2008

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Ripple Counter
- Cascaded Toggle Flops can be used to form rippled counter - there is no Next State Logic - this is slower than a straight binary counter due to waiting for the "ripple" - this is good for low power, low speed applications

EE 367 Logic Design Spring 2008

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Counters
Synchronous Counter with ENABLE
- an enable can be included in a "Synchronous" binary counter using Toggle Flops - the enabled is implemented by AND'ing the Q output prior to the next toggle flop - this gives us the "ripple" effect, but also gives the ability to run synchronously - a little faster, but still less gates than a straight binary circuit

EE 367 Logic Design Spring 2008

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Shift Register
- a chain of D-Flip-Flops that pass data to one another - this is good for "pipelining" - also good for Serial-to-Parallel conversion - for n-flip-flops, the data is present at the final state after n clocks

EE 367 Logic Design Spring 2008

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Counters
Ring Counter
- feeding the output of a shift register back to the input creates a "ring counter" - also called a "One Hot" - The first flip-flop needs to reset to 1, while the others reset to 0 - for n flip-flops, there will be n counts

EE 367 Logic Design Spring 2008

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Johnson Counter
- feeding the inverted output of a shift register back to the input creates a "Johnson Counter" - this gives more states with the same reduced gate count - all flip-flops can reset to 0 - for n flip-flops, there will be 2n counts

EE 367 Logic Design Spring 2008

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Counters
Linear Feedback Shift Register (LFSR) Counter
- all of the counters based off of shift registers give far less states than the 2n counts that are possible - a LFSR counter is based off of the theory of finite fields - created by French Mathematician Evariste Galois (1811-1832) - for each size of shift register, a feedback equation is given which is the sum modulo 2 of a certain set of output bits - this equation produces the input to the shift register - this type of counter can produce 2n-1 counts, nearly the maximum possible

EE 367 Logic Design Spring 2008

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Linear Feedback Shift Register (LFSR) Counter
- the feedback equations are listed in Table 8.26 of the textbook - It is defined that bits always shift from Xn-1 to X0 (or Q0 to Qn-1) as we defined the shift register previously - they each use XOR gates (sum modulo 2) of particular bits in the register chain ex) n 2 3 4 5 6 7 8 : : Feedback Equation X2 = X1 X0 X3 = X1 X0 X4 = X1 X0 X5 = X2 X0 X6 = X1 X0 X7 = X3 X0 X8 = X4 X3 X2 : :

X0

EE 367 Logic Design Spring 2008

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Counters
Linear Feedback Shift Register (LFSR) Counter
ex) 4-flip-flop LFSR Counter Feedback Equation = X1 # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 repeat Q(0:3) 1000 0100 0010 1001 1100 0110 1011 0101 1010 1101 1110 1111 0111 0011 0001 1000 Sin 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 X0 (or Q2 Q3 as we defined it)

- this is 2n-1 unique counts

EE 367 Logic Design Spring 2008

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