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A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop
Sbastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, and Angelo Nagari
AbstractThis paper proposes a 1-A, 6.4-MHz switching frequency DC-DC converter with embedded digital controller, implemented in 65-nm CMOS technology. The proposed DC-DC converter, exploiting a customized, multi-function SAR ADC and a non-linear PID controller, can switch automatically between continuous-conduction mode and pulse-skipping mode, thus maintaining a fairly large efciency also for light loads. Moreover, a feedforward path in the digital control loop, implemented using the SAR ADC for converting also the battery voltage, signicantly improves the line transient performance. The DC-DC converter, which occupies an area of 0.038 , consumes 115.5 , and requires an external inductance as low as 470 nH, is particularly suited for portable applications. Index TermsAnalog-digital conversion, analog-digital integrated circuits, CMOS integrated circuits, DC-DC power converters.


IGITAL control of Switched-Mode Power Supplies (SMPS) circuits is spreading in power electronics applications [1][8] and it can now be found in discrete commercial products. However, the adoption of this technique is not yet very common in Integrated Circuits (IC) for portable applications. First of all, digital SMPS ICs for portable applications work in the low power range (typically around 1 W), where high efciency is a must. To cope with this constraint, dedicated very low-power ADC structures [4], [8] and circuit solutions [2], [6] have to be developed. At the same time, as most of the ICs for portable applications, digital SMPS circuits have to be implemented in cutting edge technologies [3], [5], [6], [8], where they can benet from better digital density and transistor speed, which allows higher switching frequencies (1 MHz 10 MHz) to be used. Moreover, small silicon area is also of paramount importance, in order to compete with analog SMPS circuits, thus requiring dedicated solutions for implementing both the ADC and the digital controller. Finally, last but not least, digital SMPS circuits can take advantage of the inherent
Manuscript received November 15, 2011; revised January 30, 2012; accepted February 20, 2012. Date of current version June 21, 2012. This paper was approved by Guest Editor Atila Alvandpour. This work was supported in part by a Nano 2012 grant. S. Cliquennois, and A. Nagari are with ST-Ericsson, Grenoble, France (e-mail:sebastien.cliquennois@stericsson.com;angelo.nagari@stericsson.com). A. Donida, and P. Malcovati are with the Department of Electrical Engineering, University of Pavia, Italy (e-mail: achille.donida@unipv.it; piero.malcovati@unipv.it). A. Baschirotto is with Department of Physics G. Occhialini, University of Milan-Bicocca, Italy (e-mail: andrea.baschirotto@unimib.it). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2012.2191214

Fig. 1. Simplied block diagram of the digital SMPS.

signal processing capabilities of digital solutions, in order to implement advanced control schemes, including, for example, lossless current sensing [7] or non-linear algorithms [8]. In SMPS for portable devices, besides the peak efciency, which is an important performance parameter in conventional applications, the efciency at light loads is also a major issue. Indeed, considering that a portable device is typically requiring the peak current value for short periods and spends most of the time in low-power standby state, the efciency at light loads is affecting the battery life at least as much as the peak efciency. Therefore, SMPS for portable applications have to maintain a reasonable efciency even for load currents as low as 1% of the peak current, without signicantly degrading the voltage regulation performance, thus requiring some sort of efcient low-power operating mode. The minimization of the size of off-chip components, especially of inductors, is also quite important in portable applications, since PCB area is becoming as signicant as chip area in determining the device cost. This can be achieved using a higher switching frequency. This paper proposes a digital SMPS in 65-nm CMOS technology, designed for portable applications, in which area occupation is reduced by using a multi-function SAR ADC to achieve the required functionalities with minimum power consumption. Moreover, using a single multi-function SAR ADC in a digital SMPS enables to digitize with a time-sharing and the regulated scheme both the battery voltage

0018-9200/$31.00 2012 IEEE



Fig. 2. Simplied timing diagram of the digital SMPS in CCM.

voltage [9]. In particular, data enhances the line-transient performance, while allowing the implementation of additional control and estimation schemes needing this information. Other solutions presented in the literature, such as [10], , include an additional which exploit the information on dedicated ADC for this purpose, that requires extra area and power consumption. The proposed digital SMPS switches at 6.4 MHz and can operate both in Continuous-Conduction Mode (CCM) and Pulse-Skipping (PSK) mode, thus maintaining the efciency relatively high also at light loads. Automatic mode switching allows awless transitions between the two modes. The development of the proposed device is based on reallife specications of an SMPS for portable application, and, therefore, it does not focus solely on transient performance optimization, as most of the other digital SMPS ICs described in the literature. Indeed, the proposed SMPS involves a complete optimization of the system, including support for a wide range of feedforward), introduction power supplies (thanks to the of a digital variable reference, and automated-mode switching between PSK and CCM. All these features are available (for the controller part) with a silicon area almost one order of magnitude smaller than the state-of-the-art. The paper is organized as follows. Section II describes the digital SMPS architecture, including CCM and PSK control loops, as well as automatic mode switching. The proposed SAR ADC is then illustrated in Section III. Section IV reports the achieved experimental results and, nally, Section V draws some conclusions. II. DIGITAL SMPS ARCHITECTURE Fig. 1 shows a simplied block diagram of the proposed digital SMPS, showing both CCM and PSK mode control loops, while Fig. 2 shows a simplied timing diagram for the system operating in CCM. A single 7-bit SAR ADC embedded in the system is used and with different in time-sharing to digitize both bandwidth requires that is digtimings. The larger itized with a higher sampling frequency . On bandwidth allows us to digitize the other hand, the lower at a data rate equal to , thus reducing the ADC and clock generator power consumption of about 50%

is digitized with samwith respect to the case in which pling rate equal to , without degrading the system performance. A. Continuous-Conduction Mode (CCM) In CCM, a closed-loop mixed-signal system controls the output voltage . Bandwidth, stability, and accuracy are optimized by exploiting the 65-nm CMOS high-speed capability, for operating the digital SMPS with a 307.2-MHz master clock. is subtracted from a 7-bit The digital word representing , corresponding to the desired voltage level set-point ( ), to obtain a digital representation of the error . Reference is digitally ltered, to smooth the dynamic voltage scaling behavior. On the other hand, the allows the implementadigital word relative to tion of a feedforward path in the control-loop for optimizing the system response and stability [10]. Both digital words are fed to a digital controller, whose block diagram is shown in Fig. 3, including a non-linear PID [11] and a divider, which calculate the modulator dithers next 11-bit duty-cycle value. A multi-bit , coded on 6 bits, the 11-bit signal into a 48-level signal fed into a simple counter-based Digital Pulse-Width Modulator (DPWM) [12]. The DPWM generates the 1-bit signal which drives the integrated power stage buffers, as well as the clock signals for the ADC and the PID controller. The DPWM and clock generator consists of a simple 48-level ripple-counter operated at 307.2 MHz. From the counter output , several signals are obtained: the PWM signal, which is rising to 1 when and falling back to 0 when ; the SAR ADC conversion clock , obtained by gating with the counter the 307.2-MHz clock divided by is only present for 7 periods for 2, so that and 4 periods for ; , directly gener the SAR ADC sampling clock ated from counter. An additional 5-bit counter operated at 6.4 MHz (307.2 related clocks ( and MHz/48) is gating the ), allowing the sampling frequency to range (i. e. the same rate as ) to . from



Fig. 3. Block diagram of the digital controller.

The feedforward path in the digital controller introduces an additional static term in the classical open-loop control-to-output transfer function of a Buck converter based on the average model, given by (2) is the steady-state duty-cycle, and , in which the DC gain is actually proportional to . The additional term , introduced by the feedforward path, effectively cancels this dependency and leads to a constant DC gain in the transfer function, thus allowing the use of a more aggressive compensation over the whole range. It can also be shown [9] that with such a scheme, at least at DC. This is actually not at rst order, completely true when second order and quantization effects are considered, but it clearly shows the benets of the feedforward path in the digital controller on the line regulation performance. In order to preserve the phase margin, the digital SMPS must minimize the loop-delay, i. e. the time spent between sampling and applying the correction to the system. To optimize this timing, a 153.6-MHz burst clock signal is used for the ADC, derived from the master clock, allowing a xed latency. Moreover, as already mentioned, the calculations in the digital PID are done with mere lookup tables, adders and multipliers, only needing a single clock edge to determine the duty-cycle [13]. The DPWM is sampling this result 16.2 ns later, in order to account for worst-case signal propagation in the control circuit. where B. Pulse-Skipping (PSK) Mode The SMPS power stage and switching frequency are designed to offer maximum 85% efciency at minimum drop-out for high currents, but this efciency degrades very steeply when the load is such that the current in the inductance is inverting, adding extra losses to the already dominant switching losses. In order to alleviate this issue, a Pulse-Frequency Modulation (PFM) ) pulse is apscheme can be used. A xed-duration (xed plied to the output stage, which then goes to high-impedance

Fig. 4. Digital controller coefcient values as a function of the error signal.

The PID controller implements the classical discrete-time transfer function

(1) where is the signal coming from the ADC, coded with four signed bits, and is the duty-cycle, coded with 18 bits, as required to avoid saturation. As proposed in [12], coefcients , , and are implemented as lookup tables (LUTs). The coefcients depend on the value of , thus making the response non-linear and allowing a faster transient response, while keeping stability. The coefcient values as a function of are plotted in Fig. 4. Unlike in [11], where coefcients are analytically chosen, the proposed approach starts from a manuallydesigned compensator, which is then fed into an optimization loop, aiming at minimizing the over-voltage and maximizing , tranthe phase margin, over the whole range of , inductance , capacitance , sistor on-resistance . and equivalent series resistance



Fig. 5. Simplied automatic-mode switching nite-state machine.

state until the output voltage drops below the set-point. An alternative solution is synchronizing the output voltage tracking with a clocked comparator [2]. However, while this scheme offers excellent efciency performance, its reduced bandwidth, due to the lower clock frequency, makes it a good candidate only for dedicated ultra-low current modes, but it cannot be used for medium to low current modes (i. e. below critical conduction), where transient performance requirements are expected to be similar to CCM. The solution implemented in the proposed SMPS, called Pulse-Skipping (PSK) mode, is a synchronized xed-on-time PFM scheme, which exploits the same ADC as in CCM to compare the output voltage with a digital set-point. which minimizes losses, In order to generate a value of a digital adaptive scheme is used. An initial digital value , where is the number of DPWM levels, is calculated using look-up tables for fast and efcient implementation of the required division. corresponds to the time required for the The value of current to reach zero after a conduction period for a lossless will power stage. Because of losses, the actual value of be necessarily larger. Therefore, at the end of each conduction cycle, a current sensing circuit detects if the inductance current is negative (conventional zero crossing method [14]). If is increased by 1 LSB, until a positive this is the case, inductance current is detected. After a conduction period, if the ADC detects that the output voltage is still below the set-point, another pulse is generated, or, otherwise, the output stage goes in high-impedance state, until the output voltage drops again below the set-point. C. Automatic Mode Switching A key feature for a SMPS is the ability to automatically select the optimal operating mode for efciency: if the load current is such that the current in the inductance is inverting before the end of the switching period, PSK mode must . be used, whereas CCM is required for higher values of

The transition between the operating modes is managed by the Finite-State Machine (FSM) shown in Fig. 5. Two variables are used for choosing the operating mode: the output code of , which is a digital image of the the SAR ADC , provided by output voltage error, and the digital signal the current sensing circuit, whose function is to sense whether the current in the inductance is positive or negative at the end of every conversion period. The current sensing circuit runs at the as clock. power stage frequency, using The SMPS is starting in open-loop conguration, by progressively incrementing the internal value of the PID accumulator, while the saturated output of the ADC remains disconnected from the digital compensator. When the output voltage , the output of the ADC is approaches the set-point connected to the PID input and the system starts operating in closed-loop conguration, always in CCM mode. In order to avoid oscillation between modes, because of potential wrong decisions taken during transients, the FSM waits until for consecutive periods (i. e. the SMPS is in stable condition), before allowing entering PSK mode, if needed (in a low-load condition). Moreover, the decision to eventually enter PSK mode is taken when the inductance current is inverted consecutive periods. The value of for is chosen so that the system is settled in worst-case conditions. The state PSKOpen SW corresponds to the situation in which both power transistors are open, leading to high . When entering this state (always impedance at node after a conduction period of the bottom power transistor), the is detected and the value of for the next value of conduction period is calculated. The state PSKClose SW corresponds to a full conduction period, with duty-cycle given . by To be less sensitive to the offset of the current sensing circuit and provide hysteresis, the condition to quit PSK mode is based on the ADC output value: as long as the output voltage remains , the system stays in within 1 LSB around the set-point



Fig. 6. Operating principle of the current sensing circuit.

. In case PSK mode, otherwise it switches back to CCM of fast load transients, which create an important output voltage drop, the SMPS switches back at once to CCM and can quickly react to the transient. In case of slow increase of the load current, the system switches back to CCM only when needed. Indeed, if the load current is slightly larger than the maximum current that the system can supply in PSK mode, the output voltage slowly , for which it switches drops and reaches the condition back to CCM. A necessary condition for the FSM to be stable is that , where is the threshold value, for which the current sensing circuit detects that the inductance is the critical output current current is inverted, and (the steady-state output current for which the inductance current becomes negative during the conduction period). If is such that and the output current , the system will enter PSK mode, not being able to provide enough current. Therefore, the output voltage drops and the FSM continuously oscillates between the two modes. Although the transient and regulation characteristics of the SMPS are not affected by this situation, unwanted will low frequency oscillations with period larger than occur. In order to avoid this condition, an offset is added in the , even for current sensing circuit, such that worst-case process variations. As a consequence of this offset, , the system still remains in when

CCM, although the current in the inductance is inverting. Therefore, the efciency slightly drops in this zone, as evident in the measured efciency curve reported in Fig. 16. D. Current Sensing Circuit The operating principle and the schematic of the current sensing circuit are shown in Fig. 6 and Fig. 7, respectively. The function of this circuit is to determine, at the end of each conis inverted duction period, whether the inductance current and is owing back to ground. This information is used in CCM, to determine if the system should switch to PSK mode, is too short. and in PSK mode, to evaluate if the applied The inductance current detection is performed indirectly, by . As shown sensing the voltage in Fig. 6, if is inverting before the end of the conduction , then voltage is becoming posperiod of transistor to node itive, because the current is now owing from node . On the other hand, if remains positive, the sign of is not changing and remains negative. Morevoltage is turned off, either diode or over, since after diode is conducting, in both cases the sign of voltage and ). is actually reinforced (i. e. in phases The sensing circuit shown in Fig. 7 basically amplies ( , being the transconductance voltage and ), which is then further amplied by of transistors on the a chain of inverters and sampled by a ip-op . Since the clock falling edge of the driving signal of



Fig. 7. Schematic of the current sensing circuit.

Fig. 8. Schematic of the multi-function SAR ADC.

is then buffered to signal of the sampling ip-op generate the driving signal of the power transistor itself, it is guaranteed that switching always occurs after sampling, thus not disturbing the measurement. The drawback of this structure is that the PWM duty-cycle (i. has to be such that conduction occurs in transistor e. the duty-cycle has to be lower than 95%, considering digital clamping). However, in actual portable applications, where the input voltage is provided by a battery and the output voltage is lower than 1.8 V, a duty-cycle value larger than 95% never occurs in steady-state. The speed of decision impacts the precision of the threshold , which is important to avoid oscillation between current in each modes. Therefore, a fairly signicant current branch of the circuit shown in Fig. 7 is required. However, the current sensing circuit is only activated during conduction periods and, therefore, its power consumption leads to less than 0.1% efciency loss at the limit between PSK mode and CCM, while in PSK mode the average power consumption scales linearly with the output current, thus not impacting signicantly the overall efciency even for smaller currents.

III. MULTI-FUNCTION SAR ADC The functionality of the complete digital SMPS is achieved with a customized 7-bit SAR ADC, operated at 153.6 MHz (19.2-MHz maximum sampling frequency). The SAR ADC per, as a 4-bit forms three functions: it acts as a DAC for and as a 7-bit full-range ADC for windowed ADC for . The implementation of these three functions in a single device allows a signicant overall power consumption and area reduction. However, it requires different input conditioning cirand . The proposed architecture can furcuits for ther scale: control of several power stages can be multiplexed keeping a single ADC and controller by simply adding some phases to the clock generator and to the DPWM. Two different Successive Approximation Registers (SARs), as well as two different voltage dividers, placed in front of the ADC core have been implemented. A resistive divider by a and a capacitive divider by a factor factor 5 is used for . Considering that the maximum value 1.27 is adopted for is 4.8 V, the choice of a resistive divider in this case of is mandatory, in spite of the additional power consumption,



Fig. 9. Timing diagram of the multi-function SAR ADC.

to avoid using high voltage transistors in the ADC. By con, since the maxtrast, a capacitive divider can be used for imum output voltage is within the operating range of standard mid-oxide transistors (2.5 V). Moreover, different accuracies is and . The digital word are required for . Thus, representing only the error signal with respect to is coded with only 4-bit resolution around the reference (set-point). The ADC resolution while provalue set by ducing is a major design parameter of the circuit, since it is directly linked to the SMPS DC regulation performance and has a direct effect on potential stability issues. Indeed, a small LSB causes stability problems (due to the DPWM resolution) [15], while a large LSB leads to regulation performance issues. A reasonable trade-off is to use a 10-mV LSB. Lower LSB values cannot be achieved with the proposed architecture in the used technology, since the 11-bit resolution of the DPWM is the maximum achievable with a simple counter implementation (to achieve higher resolution a DLL would be required, with a large area and power consumption penalty). On the other conversion is 39 mV to cover the full hand, the LSB for range with 7 bits of resolution. The complete schematic and the timing diagram of the multifunction 7-bit SAR ADC are shown in Fig. 8 and Fig. 9, respectively. The ADC operates with 1.2-V power supply and 1-V . The 1.2-V power supply for the ADC is reference voltage generated by a small auxiliary voltage regulator (LDO). This solution is fully compatible with actual power management units (PMUs) for portable applications, where a LDO is often used to power an always-on small domain in the digital processor. This LDO is always turned-on rst and, hence, it can be used to power the ADC and the logic within the SMPS.

Fig. 10. Microphotograph of the chip and layout of the controller.

The input signals and , scaled by the correis sponding voltage dividers, are sampled (actually



Fig. 11. Line regulation measurement for different values of the load current . Fig. 14. Transient measurement during automatic mode switching from CCM to PSK.

Fig. 12. Line transient measurement.

Fig. 15. Transient measurement during automatic mode switching from PSK to CCM.

Fig. 13. Load transient measurement.

sampled by the capacitive divider itself) and applied to the comparator input. The DAC voltage , controlled by the SARs, is connected to the other comparator input. This choice while the ADC is converting and allows sampling vice-versa, thus increasing the time slot available for sampling, without degrading the conversion speed of the ADC. For sampling the input signal directly on the DAC, as typically done in SAR ADCs, a specic time slot would have been required, leading to a larger latency in the feedback control loop. The analog part of the SAR ADC consists of a latched comparator and a DAC, realized with a charge redistribution ca-

Fig. 16. Efciency measurement.

pacitive structure. The 7-bit array is split in two parts (4 and , to reduce 3 bits, respectively) with a bridge capacitor the total capacitance and, hence, the power consumption. In fact, a binary weighted DAC is chosen instead of a thermometric DAC, that would lead to lower reference voltage power consumption, but also to larger digital power consumption and




area, with an overall disadvantage. Before each conversion, the capacitive array is pre-charged with a xed offset , to adjust the intrinsic ADC voltage range (0 V 1 V), determined by the value of , to cover the whole range (0.6 V 1.35 V, which becomes 0.47 required is added to V 1.1 V after scaling). Basically, voltage by pre-charging, during reset, capacitors and to and discharging the other capacitors of the DAC to ground conversion the reference . During is added to the SAR output before feeding it to the word DAC, in order to center the 4-bit conversion around the required voltage level (windowed ADC operation). IV. EXPERIMENTAL RESULTS The proposed digital SMPS circuit has been fabricated in a 65-nm CMOS technology. Fig. 10 shows a microphotograph of the chip, whose area, without considering the power transistors, . is 0.038 The line regulation measurements for different values of the are illustrated in Fig. 11. The achieved load current

performance is limited by the ADC LSB (10 mV), as expected. Fig. 12 and Fig. 13 show the measured line and load transients, respectively. The line transient is signicantly improved by the introduction of the feedforward path that can be implemented , guaranthanks to the availability of the information on teed by the multi-function SAR ADC. The behavior of the system during the automatic transition , from CCM to PSK mode, resulting from a steep drop of drops, rises, since is illustrated in Fig. 14. When there is an excess of charge, coming from the inductance, that cannot be evacuated by the load and, hence, accumulates on the . When has been detected to be capacitance steadily inverted, the system enters in the PSKOpen SW state, leaving the output in high-impedance condition, until , and, hence, the ADC output reaches the value ( ) for which the normal corresponding to PSK sequence starts. The mode-transition overshoot, in this case, is around 25 mV. Fig. 15 shows the automatic transition from PSK mode to CCM, resulting from a load current step of 400 mA. The system is leaving PSK mode when the output



voltage drop is more than 15 mV and the non-linear PID takes over. The resulting undershot is limited to about 20 mV, in line with the load transient measurement shown in Fig. 13. Fig. 16 shows the efciency measurement. The input power has been accurately measured using a 4-wire source meter on (which is supplying the power stage and the buffers), and another 4-wire source meter on the 1.2-V supply. The maximum efciency achieved, equal to 85%, is in line with expectations, considering that the power stage has not been optimized for this particular application, nor in terms of transistor sizes, nor in terms of dead-time. This efciency value could appear fairly low compared to [3] and [6], but the high switching frequency, with the associated switching losses, explains most of the difference. The high switching frequency, on the other hand, allows to be used, which is a small inductance value important in portable applications (a 470-nH inductor occupies inductor with the same feaabout 50% of the area of a 1tures). The automatic mode switching allows us to maintain the efciency higher than 70% down to , while, the efciency would considering CCM only, at be around 13%. The main features of the proposed digital SMPS are summarized in Table I and compared with the state-of-the-art [3], [6]. The adopted system and circuit solutions achieve similar performance as [3], with smaller die area (1/3 factor) and lower power consumption (1/8 factor), while using a 6.4-MHz switching frequency, which allows the use of a small 470-nH inductor, in line with the continuous trend of shrinking portable devices PCB sizes [6]. V. CONCLUSIONS In this paper we presented a 1-A, 6.4-MHz switching frequency buck digital SMPS, realized in 65-nm CMOS technology, which takes advantage of a multi-function, low-power SAR ADC to achieve a very low area, while keeping acceptable static and dynamic performance. The proposed SMPS, besides the conventional continuous-conduction mode, implements a pulse-skipping mode with automatic simple, adaptivemode switching, which maintains the efciency fairly large also at low load currents. Moreover, a feedforward path in the control loop, implemented using the SAR ADC for converting also the battery voltage, leads to a signicant improvement of the line transient performance. The proposed architecture is well suited for further developments in the digital controller, which can take advantage of the battery voltage information to implement, for example, current estimation algorithms or more complex control schemes. Time-multiplexing can also be pushed further by using the same ADC for sensing the output voltage of several power stages. ACKNOWLEDGMENT The authors would like to thank Denis Cottin, Nicolas Marty, Sandrine Majcherczak, and Catherine Popon, for the design and

the implementation of the integrated power stage and of the current sensing circuit, as well as for the layout of the circuit and of the test chip, Shu Wang for the design of the DPWM and for the help in the measurements, and Christophe Prmont for supporting this work. REFERENCES
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Sbastien Cliquennois received the Engineering Degree from Institut Suprieur dElectronique et du Numrique (ISEN), Lille, France and DEA degree from Lille I University both in 1998. He held various positions at ST Microelectronics and ST-Ericsson in computer-aided design tools development and design of mixed-signal power management circuits for portable applications. He lead research activities on modeling, simulation and digital control of integrated switched-mode power supplies, and is now a Technical Project Leader for ST-Ericsson in Grenoble, France.



Achille Donida was born in Milano (MI), Italy, in 1983. He received the Bachelor Degree in Electronic and Telecommunications Engineering from the University of Pavia, Italy, in 2006. In 2008 he received the Master Degree in Electronic Engineering from the same University with a thesis on RFID system design. Since 2008 he is working at the Sensors and Microsystems Laboratory (SMS) of University of Pavia, Italy, as a Ph.D. student. His research activity is focused on analog to digital converter design in collaboration with ST-Ericsson (Grenoble).

Piero Malcovati graduated in electronic engineering from the University of Pavia, Italy, in 1991. In 1992, he joined the Physical Electronics Laboratory (PEL) at the Federal Institute of Technology in Zurich (ETH Zurich), Switzerland, as a Ph.D. candidate. He received the Ph.D. degree in electrical engineering from ETH Zurich in 1996. From 1996 to 2001, he was an Assistant Professor in the Department of Electrical Engineering at the University of Pavia. Since 2002, he is an Associate Professor in the same University. His research activities are focused on microsensor interface circuits, high performance data converters, and power management circuits. Dr. Malcovati is a co-recipient of the ESSCIRC 2007 best paper award. He was Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II from 2008 to 2010. He served as Technical Program Chairman of the IEEE PRIME 2006 Conference and as Technical Program Co-Chairman for the IEEE ICECS 2009 Conference. He was and still is member of the Scientic Committees for several International Conferences, including ESSCIRC, SENSORS, ICECS, DATE and PRIME. He is regional editor for Europe of the Journal of Circuits, Systems, and Computers. He is an IEEE senior member.

Andrea Baschirotto graduated in electronic engineering from the University of Pavia, Italy, in 1989. In 1994, he received the Ph.D. degree in electronic engineering from the same University. In 1994, he joined the Department of Electronics at the University of Pavia as Assistant Professor. In 1998, he joined the Department of Innovation Engineering at the University of Lecce, Italy, as Associate Professor. From 2007, he is Associate Professor at the University of Milano-Bicocca, Italy. His research activity is focused on the design of CMOS mixed analog/digital integrated circuits, in particular for low-power and/or high-speed signal processing. Dr. Baschirotto was Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II for the period 20002003, and of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I for the period 20042005. He was the technical program committee chairman of ESSCIRC 2002 and the guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS for ESSCIRC 2003. He was the general chair of PRIME 2006, AACD 2008, and of AISEM 2009. He has been or is still a member of the technical program committees of several international conferences, including ISSCC, ESSCIRC, and DATE. Since 2006 he serves as Data Converter Sub-Committee Chair in the ESSCIRC TPC. In 2008 he has been the Secretary of the ISSCC European Committee. Since 2011 he is a member of AACD TPC. He is an IEEE SSCS Distinguished Lecturer. He is an IEEE Senior member.

Angelo Nagari was born in Cilavegna, Pavia, Italy, in 1968. He received the degree in electronic engineering (summa cum laude) from the University of Pavia, Italy, in 1993. He has been with ST-Microelectronics, Milan, Italy, since 1993, where he was involved as a Design Engineer in the analog and mixed IC development for cellular telecommunications. His main research interests are in the elds of Nyquist-rate and oversampled A/D converters for system-on-chip in audio, RF and auxiliary applications. Since February 2008 he is IP design manager in ST-Ericsson, Grenoble, France. His main role is to dene mixed-signal architecture and partitioning for 2.5 G and 3 G mobile phones (and beyond) and provide IP design in audio and power management elds. He is a reviewer for several IEEE journals and conferences and, within ST-Ericsson, he holds several patents.