Performance Enhancement of the Tunnel Field Eect Transistor for Future Low Stand-by Power Applications

A Thesis Submitted For the Degree of Master of Science (Engineering) in the Faculty of Engineering

by

Nayan Bhogilal Patel

Centre for Electronics Design and Technology Indian Institute of Science BANGALORE 560 012 August 2007

Nayan Bhogilal Patel August 2007 All rights reserved

TO

My Parents Mrs. Sushila B. Patel & Mr. Bhogilal I. Patel

Acknowledgements
I express my sincere thanks to my adviser Prof. Santanu Mahapatra for giving me an opportunity to work on a very interesting and challenging topic. He was always easily approachable and always ready to answer any of my queries. I am also thankful to him for introducing me to the eld of VLSI Device Physics. I am thankful to Prof. Navakanta Bhat, ECE for his course on VLSI Device and Process Simulation which formed the background of my work.
A I am thankful to Chaitanya Sathe for his help with Linux and L TEXand also for a

lot of enlightening discussions which have only added to my knowledge of semiconductor physics. I am also thankful to Ramesha for his help with designing the process ow for the fabrication of the Tunnel FET. Thanks are due to Biswajit for some very good discussions. I was really lucky to have such good lab mates. Living at the Indian Institute of Science is an experience in itself and my stay over here was made even more memorable by my friends Venu, Nehal maam, Guru, Hemant, Rajdeep, Amrish, Chintan, Pratikbhai, Mehul and Rashmin. Their presence made my life much more easy and comfortable. I would like to thank all of them. A big thanks to my parents for their unconditional love, encouragement and support throughout my student life. They have sacriced a lot for my education and whatever I am today is all due to them. I will try my best that the eorts of all those acknowledged will not go in vain.

Publications based on this Thesis

1. Tunnel FET - A Novel Device with Sub-Threshold Swing less than 60 mV/decade for Future Low Stand-by Power Applications, Appearing in Proc. National Conference on VLSI and Communication Engineering 2007, Kottayam, India 2. A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications, Appearing in Proc. VLSI Design And Test Symposium 2007, Kolkata, India 3. Performance Enhancement of the Tunnel Field Eect Transistor using SiGe Source Appearing in the Proc. Fourteenth International Workshop on Physics for Semiconductor Devices, Dec 2007, IIT Bombay, India

Patent based on this Thesis

1. Indian Patent applied for Silicon Tunnel Field Eect Transistor

ii

Abstract
Continuous downscaling of CMOS technology has led to immense improvements in its performance. However, the switching characteristics of the present day MOSFET switch are far from the ideal one. For the Ideal switch the sub-threshold swing is zero and this leads to zero o-state current. This o-state current is the most crucial parameter for the low standby power applications (e.g. cellular phone) as it determines the battery life of the device. The minimum value of the sub-threshold swing of todays MOSFET is physically limited to 60mV/decade at room temperature due to the drift-diusion mode of carrier transport. In fact in ultra-short channel MOSFET the sub-threshold swing is further deteriorated due to several parasitic eects (e.g., punch through, short channel eects etc). Therefore for future low standby power application one requires alternative MOSFET architecture which uses dierent type of carrier transport mechanism. The aim of this thesis is to explore the various available options and to come up with a technology which is CMOS compatible and solves the problem of increased leakage for low standby power applications. The Tunnel Field Eect Transistor (TFET) with perfect saturation in the output characteristics, sub-60mV/decade subthreshold swing and extremely high ION /IOF F ratio has attracted a lot of attention for such applications. However, due to extremely low IOF F , even though it has a very good ION /IOF F ratio, it fails to meet the technology requirements of ION . To overcome this problem of low ION , in this work, we have proposed a new Tunnel FET architecture with SiGe layer at the source end. The improvement in ION is achieved by modulating the bandgap at the tunneling junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device simulation, we demonstrate that the proposed device is scalable upto channel lengths as iii

iv

small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole fraction is increased. A CMOS compatible process ow to fabricate the proposed device is discussed. The compatibility of the process ow with the standard CMOS process makes the proposed device highly attractive for future low stand-by power applications.

Contents
Acknowledgements Publications based on this Thesis Abstract 1 Introduction 1.1 The MOSFET Switch . . . . . . . . . . 1.2 I-MOS:The Impact Ionization MOSFET 1.3 TFET:Tunnel Field Eect Transistor . . 1.3.1 Planar TFET . . . . . . . . . . . 1.3.2 Vertical Channel Tunnel FET . . 1.3.3 Ultra thin body SOI TFET . . . 1.4 Comparison . . . . . . . . . . . . . . . . 1.5 Conclusions . . . . . . . . . . . . . . . . 2 Double Gate Tunnel FET 2.1 Introduction . . . . . . . . . . . 2.2 Device structure and Operation 2.3 Simulation Tools and Models . 2.4 Simulations and Analysis . . . . 2.5 Floating Body Eect . . . . . . 2.6 Scaling of Double Gate TFET . 2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i ii iii 1 1 4 5 6 7 10 12 12 14 14 15 16 16 23 23 24 25 25 26 28 29 29 33 33 34

3 Tunnel FET with SiGe layer at Source 3.1 Introduction . . . . . . . . . . . . . . . . . 3.2 Device Structure and Operation . . . . . . 3.3 Simulation Models and Device Parameters 3.4 Results and Discussion . . . . . . . . . . . 3.4.1 The SiGe layer . . . . . . . . . . . 3.4.2 Depth of SiGe Layer (Ld ) . . . . . 3.4.3 Eect of Body bias . . . . . . . . . 3.4.4 SCE and DIBL . . . . . . . . . . .

CONTENTS

vi

3.5

3.6

3.4.5 High material as gate dielectric 3.4.6 Eect of Strain on the channel . . 3.4.7 Eect of Strain on on SiGe layer . 3.4.8 Lateral vs. Vertical TFET . . . . Fabrication of The Proposed Device . . . 3.5.1 Description of Process steps . . . 3.5.2 Impact of Mask Misalignment . . Conclusion . . . . . . . . . . . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

36 37 38 38 39 40 40 42 44 45 46 47 49

4 Conclusion and Scope of Future work 4.1 Process Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Pass Transistor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . A Sub-threshold Swing of Tunnel Transistors Bibliography

List of Figures
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3.1 3.2 3.3 Comparison of MOSFET with Ideal switch Eect of MOSFET Scaling on IOF F . . . . I-MOS: Schematic . . . . . . . . . . . . . . I-MOS: Transfer characteristics . . . . . . Planar TFET: Schematic . . . . . . . . . . TFET working: Band diagrams . . . . . . VTFET: Schematic . . . . . . . . . . . . . Eect of SiGe layer on band diagrams . . . SOI TFET: Schematic . . . . . . . . . . . SOI TFET: Band diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 5 6 7 8 9 10 11 15 17 18 19 20 20 21 22 22 24 26 27 30 31 32 33 34 35 36 37 38

Double Gate TFET schematic . . . . . . . . . . . . . . . . . . . . ID vs. VGS and ID vs. VDS characteristics of the DG Tunnel FET Gm *Ro for the double gate TFET . . . . . . . . . . . . . . . . . . VTFET Band diagram near surface region . . . . . . . . . . . . . Point S vs. VGS for DG TFET . . . . . . . . . . . . . . . . . . . . DGTFET Band diagram in bulk region . . . . . . . . . . . . . . . Tunneling Electric eld in Bulk and Surface regions vs VDS . . . . Smin and ION /IOF F vs. VDS . . . . . . . . . . . . . . . . . . . . . Smin and ION /IOF F vs. TSi . . . . . . . . . . . . . . . . . . . . . . Scaling the DG TFET . . . . . . . . . . . . . . . . . . . . . . . .

Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . Working Band diagrams . . . . . . . . . . . . . . . . . . Simulated Band Diagrams of the proposed Tunnel FET Fig. 3.1 along the cut section (AB) . . . . . . . . . . . 3.4 Simulated Device characteristics for the proposed device 3.5 S and ION vs. x . . . . . . . . . . . . . . . . . . . . . . . 3.6 GBT BT contours at the tunnel junction . . . . . . . . . . 3.7 ION vs. SiGe layer depth (Ld ) . . . . . . . . . . . . . . . 3.8 Eect of body bias on device characteristics . . . . . . . 3.9 SCE and DIBL in the proposed device . . . . . . . . . . 3.10 High dielectric with proposed device . . . . . . . . . . 3.11 Eect of x of stained and relaxed SiGe on Bandgap . . . vii

. . . . . . . . . . . . . . architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . in . . . . . . . . . . . . . . . . . .

LIST OF FIGURES

viii

3.12 Process changes necessary to fabricate the proposed device . . . . . . . . 3.13 Overcoming Mask misalignment . . . . . . . . . . . . . . . . . . . . . . .

41 42

Chapter 1 Introduction
1.1 The MOSFET Switch

Over the last couple of years, the sales of certain battery powered equipment (like mobile phones, PDAs, Palmtops etc.) has increased immensely. Today, these devices form a major market share of the semiconductor industry. Being battery operated, lowering the power consumption w/o trading o the performance is the primary aim of the manufacturers. Since, all these devices mostly operate in the standby mode, of operation, it is required that they consume very less power when on standby. Therefore, they are also called Low Standby Power (LSTP) devices. Ideally, any device should consume zero power when on standby. However, these devices use the Metal Oxide Semiconductor Field Eect Transistor (MOSFET), which has a non zero o state current (IOF F ), as the switch. The IOF F in any device is directly dependent on the sub-threshold swing (S) of the device. Lower the value of S, lower is the o-state current of the device. S is dened as the amount of gate voltage needed to change the drain current by 1 decade. It indicates how eectively the MOSFET can be switched OFF by decreasing the gate voltage below VT H . For an ideal switch, the S is equal to zero and this leads to a zero o-state current(Fig. 1.1). Relentless scaling of the MOS switch has led to an increase in the IOF F of the device. Fig. 1.2(a) shows the increase in IOF F due to the reduction in VT H of the device as a result of scaling 1

Chapter 1. Introduction

IDS

Ideal Switch

MOSFET Switch

Sub-threshold Regime IOF F VGS Figure 1.1: Transfer characteristics of Ideal and MOSFET switch on semi-log scale (assuming that S remains constant as we scale down). Fig. 1.2(b) shows that S degrades as we scale the MOSFET due to the various eects like Punch through, Short Channel Eect (SCE), and Drain Induced Barrier Lowering (DIBL) in short channel devices. As a result of this the value of IOF F increases even more than expected. MOSFETs employ a Drift-Diusion model for carrier injection. In the Sub-threshold region (VGS < VT H ), the current is dominated by diusion mechanism. The Drain current in this region of operation is given by [1], W kT = ef f Cox (m 1) L q
2

IDS

eq(Vg Vt )/mkT (1 eqVds /kT )

(1.1)

taking logarithm and then dierentiating w.r.t. VGS and inverting, we get kT q Csi Cit + Cox Cox

S = 2.3 where, Cit = interface state Capacitance, Cox = gate oxide capacitance and Csi = bulk Silicon capacitance

1+

(1.2)

When the gate oxide thickness becomes zero, S approaches approximately 2.3kT/q

Chapter 1. Introduction

IDS

IDS

I OF F L I OF F H VT L VT H VGS

Punch Through SCE DIBL

VT

VGS

(a) Increase in IOF F due to reduction in VT

(b) Increase in IOF F due to degradation of S as a result of scaling

Figure 1.2: Eect of MOSFET Scaling on IOF F (60 mV/decade). But due to the presence of non idealities such as interface states, the practical value is higher than this. Also, as we scale down, the value increases further due to an increase in doping concentration and Short channel Eect (SCE). This means that we gradually move away from Ideal switch behavior. Fig.1.1 shows a comparison between the MOS switch and the ideal switch. The above problem is inherently due to the Drift-Diusion mechanism of carrier conduction. Therefore, for future low standby power applications, one requires alternative MOSFET architecture which uses a dierent type of carrier transport mechanism. Various device concepts have been suggested and researched recently. [3], [4]. Among these, the Tunnel Field Eect Transistor (TFET) has shown a lot of promise for achieving better scaling without severe short channel eects [5]. In the following sections, we discuss in detail, the structure and working of all these devices and justify why TFET is the best possible option. In the chapters following this one, we further explore the working of TFET by means of 2D computer simulations. We also identify the short comings of the present day TFET and try and come up with an alternative to overcome them.

Chapter 1. Introduction

1.2

I-MOS:The Impact Ionization MOSFET

The basic device structure of an n-channel I-MOS as proposed by Plummer et al. [6] is as shown in Fig.1.3. It is a gated p-i-n diode operating in the reverse biased region and works on the principle of modulation of channel length. For low gate voltages, the channel length is the entire I region. The electric eld in this condition is below breakdown and consequently, the device is o. The o-state current is limited to the reverse leakage current of the p-i-n diode. As VGS is increased, an inversion layer forms under the gate and the eective channel length reduces to L1 . Due to reduction in the length, the electric elds in the region increase, causing impact ionization to occur and the device breaks down. The breakdown region is lightly doped so as to reduce the elds required for impact ionization which prevents Band to Band Tunneling (BTBT) related soft breakdown. Here, the formation of the inversion layer is limited by the normal 60mV/decade limit, but the strong dependency of the impact ionization coecients on the electric eld and the inherent feedback involved in the avalanche multiplication process produces a very steep sub-threshold characteristics.

Figure 1.3: Basic Device structure of an N-channel SOI version of the IMOS [6] Fig.1.4 shows the simulated ID vs. VGS characteristics obtained by [6]. The results indicate an S of 5mV/decade and near ideal switching characteristics are obtained. To follow-up the simulation results, a prototype device was also fabricated in silicon

Chapter 1. Introduction

Figure 1.4: Simulated ID vs. VG characteristics for an n-channel germanium I-MOS [6] and it showed an S of 10mV/decade at a drain voltage of 20V. However, the following problems were faced in the rst prototype: 1. The drain current was very low because of large parasitic resistances from long source-drain extensions. 2. These devices also suer from hot carrier eects which result in a signicant threshold voltage shift. To avoid them, the breakdown region should be kept away from the surface of the device. This can be done by using a buried channel device. 3. Very high drain voltages are required. This is because Si has a higher band-gap and a large ratio of the ionization coecients (n /n > 10) which leads to high breakdown voltages. Also, the surface ionization coecients are much lower than bulk ionization coecients because of a reduction in mean free path due to interface scattering.

1.3

TFET:Tunnel Field Eect Transistor

The TFET is also a gated reverse biased p-i-n structure like the I-MOS but it uses the principle of gate controlled Band to Band Tunneling (BTBT) for operation. A total of

Chapter 1. Introduction

three dierent architectures for the TFET have been proposed till date.

1.3.1

Planar TFET

Fig.1.5 shows the schematic of a planar n-type TFET [4]. To understand its working, we need to study its band diagram (Fig.1.6). Applying a positive gate-source voltage produces a layer of electrons under the gate oxide, which pulls the valance band and the conduction band in the intrinsic (lightly doped) region downwards. This leads to a narrow barrier at the interface of the p+ doped region and the channel. Now the electrons can tunnel from the valance band of p+ region to the conduction band of the intrinsic region and therefore induce a higher ID . Because of the similarity of the characteristics to a NMOS FET, this operation mode is called NTFET.

Figure 1.5: Basic device structure of the conventional planar N-channel Tunnel FET [4] A negative gate voltage produces a layer of holes below the oxide and as a result, the bands in the intrinsic region get pulled up, this time forming a shallow barrier near the interface of n+ and the intrinsic regions. The electrons tunnel from the valance band of the intrinsic region to the conduction band of the n+ region. Now the transistor is in PTFET operation. Note, that the source of both NTFET and PTFET is dened as the highly doped region which is closer to the tunnel junction. Since, only the tunneling

Chapter 1. Introduction

1.5 V 1 0.5 Energy (eV) 0 V

GS

= 0V = 2V

VDS = 1.0V
EC

GS

EV

0.5 1 n+ drain isilicon p+ source

1.5 2 2.5 0.2

0.25

0.3

0.35 0.4 Distance (m)

0.45

0.5

Figure 1.6: Simulated Band diagrams of TFET in conducting and non-conducting regions region of the TFET is the active region of the TFET, and it is very small, the TFET can be scaled down to 20nm and below, without using other than standard MOSFET materials [5].

1.3.2

Vertical Channel Tunnel FET

The VTFET was proposed by Bhuwalka et al. [15] and is a modied version of the Planar TFET . The schematic of the device is as shown in Fig.1.7 This device consists of a molecular beam epitaxy (MBE) grown, vertical p-i-n structure. The vertical stack consists of a boron-doped source substrate, a 3 nm, 1 x 1020 cm-3 boron-doped delta layer (p+ ), 100 nm n-type unintentional-doped (1 x 1016 cm3 ) channel and a heavily doped n+ drain electrode. A vertical gate stack is grown on the sidewall. The operating principle is same as planar TFET. Here, a vertical gate controls the band to band tunneling width, and hence the tunneling current. The so called layer is deposited above the intrinsic channel to achieve an abrupt doping prole at the source. This results in a much better device performance as the tunneling is assisted by abrupt proles. However, the performance can be further improved by replacing the -layer by a highly doped strained SiGe- -layer.

Chapter 1. Introduction

Figure 1.7: A schematic of the Vertical Channel Tunnel FET [15] Eect of the SiGe- Layer: The delta layer plays a major role in improving the electrical characteristics of the VTFET [9].It is seen that the incorporation of pseudomorphic strained Si1x Gex leads to a signicant performance increase. Due to the lower bandgap of Germanium, the tunneling width decreases. Hence, there is a higher tunneling probability for electrons in this region and therefore, higher ION can be achieved. This also improves the Sub-threshold slope of the device. We can further control the ION /IOF F ratio by varying the Ge mole fraction (x) in the SiGe layer. Fig. 1.8 shows the new band diagram after the introduction of the SiGe layer. A reduction in the tunneling width ( ) can be clearly seen due to the introduction of a small notch near the p+ intrinsic region junction. It is to be noted here that the increase in current is due to the reduction in tunneling width ( ) and not due to the reduction in band-gap (Wg ). As x is varied from 0 to 0.5, an improvement in the sub-threshold swing is observed. This is due

Chapter 1. Introduction

Figure 1.8: Simulated band diagrams for 100nm n-channel VTFET with p+ -SiGe layer (x=0.5) as a function of VGS [26] to the fact that the Band to Band tunneling Generation rate increases with a reduction in the bandgap of the material. According to Kanes model for BTBT, the generation rate is given by [20], GB2B = AKane E 2 Wg1/2 eBKane Wg
3/2

/E

(1.3)

where, Akane and Bkane are material dependent constants and E is the electric eld at the tunneling junction of the TFET. It can be clearly seen that the BTBT generation rate is inversely related to the bandgap (Wg ). Thus, the subthreshold swing can be reduced below the 60mV/decade limitation of the MOSFET by increasing the Germanium molefraction (x) in the SiGe layer [26]

Chapter 1. Introduction

10

1.3.3

Ultra thin body SOI TFET

This TFET architecture was proposed by Zhang et al [3]. The P-type structure of the transistor is shown in Fig. 1.9 and comprises of a silicon-on-insulator (SOI) structure in which a lateral p+ n+ junction is formed in an ultra-thin semiconductor body. The gate is aligned to the junction on the p-side so as to facilitate better control of

Figure 1.9: Schematic cross section of the P-type Ultra thin body Silicon on Insulator TFET proposed in [3] the p-side electrostatic potential. The p-region is fully depleted for zero gate bias. An analytic solution for the potential prole using a two dimensional (2-D) Poisson equation is performed in [3]. Ignoring the statistical dopant uctuations (which become important as we scale down), the potential (x, y) is given by, for 0=x=tSi and L=y=L+W qNa d2 (x, y ) d2 (x, y ) + = 2 2 dx dy si (1.4)

where, NA is the acceptor concentration on the p-side, Si is the Si dielectric constant tSi is the thickness of the dielectric layer and L is the gate length The n-side is un-modulated by the gate and therefore can be treated as a one dimensional (1-D) problem with the potential given by [3] for 0=x=tSi and L=y=L+W d2 (x, y ) qNa = dy 2 si (1.5)

where, ND is the doping concentration on the n-side, and W is the depletion length on

Chapter 1. Introduction

11

the n-side Equations 1.4 and 1.5 have been solved using the following 4 boundary conditions: 1. Constant potential on the surface between the semiconductor and the gate oxide; 2. Zero electric eld in the x direction on the surface between semiconductor and buried oxide; 3. Continuous potential and electric eld at the p-n junction; and 4. 0.3-eV schottky barrier at the drain contact. Energy bands shown in 1.10 were computed from the solutions of the above equations. The transistor operation can be understood from the band diagrams.

(a)

(b)

Figure 1.10: Energy Band Diagrams at x=0 (in 1.9) with (a) zero and (b) negative gate voltages [3] The transistor o state is shown in Fig. 1.10(a); for a VGS of zero, the p side is depleted and the interband tunneling probability is low. When a negative gate voltage is applied, the valance band on the p-side is raised above the Fermi level on the n-side turning the interband tunneling and the transistor ON Fig. 1.10(b). In this transistor

Chapter 1. Introduction

12

geometry, the gate screens the drain eld enabling current saturation and isolation. The analytic model was veried using the Synopsis device simulator ISE TCAD. 2D device simulations of the transistor showed a subthreshold swing less than 60mV/decade for low gate voltages.

1.4

Comparison
DISADVANTAGES 1. Output Voltage swing is not rail to rail. 2. IDS is low because of parasitic resistances fromlong source drain ext. regions. 3. Hot carrier eects resulted in VT shifts. 4. High VDS is required (n /p > 10) 1. Because of low IOF F , the conventional TFET fails to meet the technology requirements for ION and VT . 2. The VTFET overcomes these problems but fabrication and packaging is not compatible with the standard CMOS process.

Comparison of TFET and IMOS DEVICE ADVANTAGES I:MOS 1. Very low IOF F . 2. Very fast Switching Speed (pS). 3. S as low as 5mV/decade can be obtained. 4. Easy to fabricate complementary devices.

TFET

1. Very low IOF F (fA). 2. S is not limited to 60mV/decade. 3. IOF F and VT are independent of channel length and scaling.

1.5

Conclusions

In this chapter, we have examined the problems faced by the MOSFET as it enters the nano-scale regime. Here, we propose to deal with the challenge of increased leakage and Sub-threshold swing of the MOSFET. Due to the drift diusion mode of carrier transport, the sub-threshold swing in the MOSFET is limited theoretically to 60mV/decade at room temperature. The Tunnel FET with perfect saturation and in the output characteristics and exponentially increasing IDS versus VGS , has shown a lot of promise for

Chapter 1. Introduction

13

sub-100nm analog and digital applications. However, the Silicon Tunnel FET, though it can be scaled to sub-20nm regime, because of very low IOF F , fails to meet the technology requirements in terms of ION and VT . The main challenges in this eld lie in the proper understanding of the carrier transport of the TFET and try and improve its drive strength so that it can be used for future Low Standby Power applications.

Chapter 2 Double Gate Tunnel FET

2.1 Introduction

As discussed in the previous chapter, the switching characteristics of the MOSFET switch have degraded considerably over the years. This has posed a major hurdle in its application to Low Stand by power applications if the scaling were to continue. The Tunnel Field Eect Transistor (TFET) [4] with perfect saturation in the output characteristics and exponentially increasing IDS versus VGS has shown a lot of promise for achieving better scaling without severe short channel eects [11]. In the following sections, we discuss in detail, the structure and working of TFET and how it can oer an alternative for future LSTP applications. O all the variants of TFET, the Vertical channel TFET (VTFET) discussed in section 1.3.2 with pseudomorphic p+ -SiGe layer has been the most widely discussed one in the literature. It has shown some very good electrical properties. However, its fabrication, which involves complex processes such as Molecular Beam Epitaxy (MBE) is a very costly and time consuming process. Thus, it is desirable to have a structure which can be fabricated with the existing process consisting of standard CMOS fabrication steps. In this work, we study by means of 2D- computer simulations, a planar Double gate structure of Tunnel FET whose fabrication can be easily integrated with the standard CMOS technology. 14

Chapter 2. Double Gate Tunnel FET

15

2.2

Device structure and Operation

The device being studied is the lateral Double gate TFET. Just as the conventional TFET, it is a gated reverse biased p+ i n+ structure which uses the principle of gate controlled Band to Band tunneling for its operation. The schematic of the device is shown in Fig. 2.1. To operate the device, the source is grounded, a positive voltage (1V) is applied to the drain and a voltage is swept across the gate terminals. The operating principle of the device is exactly the same as that of the conventional TFET and can be explained using the band diagrams in Fig. 1.6. In the absence of the gate voltage, the tunneling barrier width is much higher than 10nm (the approximate minimum required for tunneling to take place in silicon). However, on application of positive gate voltage (n-type behavior), the bands in the intrinsic region get pulled downwards and a tunneling junction is created at the junction of the p+ source and the intrinsic channel. Zener tunneling of electrons takes place from the valance band of the source to the conduction band of the channel and the device turns on. VGS

LCH =100nm VDS n+ drain i-channel

Tsi

p+ source

VGS Figure 2.1: Schematic of the DG Tunnel FET structure being investigated (Tox = 2nm)

Chapter 2. Double Gate Tunnel FET

16

2.3

Simulation Tools and Models

2D Device simulations are performed using Medici. Field dependent Kanes model [20] for band to band tunneling available in Medici [21] was used to model the band to band tunneling generation and recombination rate. Kanes model has been shown to give a good match for band to band tunneling in silicon based tunnel transistors at both high and low temperatures [9]. Since the source and drain regions are heavily doped and tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also included in simulations. Also, due to high values of doping involved, the Boltzmann approximation cannot be used to model the device. Hence, Fermi Dirac statistics are used to improve the accuracy of the simulation at the cost of computational eciency. For the simulations, a xed oxide thickness, tox =2nm is chosen. The n+ drain is doped 2x1019 cm3 , the p+ source is doped 1x1020 cm3 and the substrate is doped 1x1016 p-type, corresponding to the substrate doping in the standard CMOS process.

2.4

Simulations and Analysis

The transfer characteristics of the Double Gate Tunnel FET are shown in Fig. 2.2(a). Unlike the MOSFET, there is no clear boundary between sub-threshold and saturation regions. The output characteristics of the device are shown in Fig. 2.2(b). As compared to the power dependence on VGS in the MOSFET, the behavior seen here is of a much higher order. Also, gm and Ro were evaluated for IDS versus VGS at various Drain bias. It was found that, the gm value was in the range of 109 to 107 from sub-threshold to inversion region respectively. Ro was also evaluated from the IDS versus VDS curves for three dierent VGS (1.0V, 1.2V and 1.4V) near the operating potential of the device and was found to be of the order of 1011 for higher VDS . It was found that 104 as we increase the VDS to the operating voltages. This is signicantly higher when the Gm *Ro product is quite small (27) for lower values of VDS but is in the order of compared to the present day MOSFET which has the Gm *Ro value in the range of 40 to 50. The variation of the Gm *Ro product with VDS and VGS for the double gate TFET

Chapter 2. Double Gate Tunnel FET

17

Vds = 0.1V Vds = 0.4V Vds = 1.0V

-16 0.00 0.20

log(I(Drain)) (A/um) -14 -12 -10

-8

0.40

0.60

0.80 1.00 V(Gate) (V)

1.20

1.40

1.60 1.80

(a) Transfer Characteristics of the DG TFET for various values of drain voltages
Vgs = 1.3V Vgs = 1.2V Vgs = 1.4V

5.00

0.00 1.00

I(Drain) (A/um) *10-10 2.00 3.00 4.00

L = 100nm Tsi = 100nm

0.00

0.25

0.50

0.75

1.00 1.25 V(Drain) (V)

1.50

1.75

2.00

(b) Output Characteristics of the DG TFET

Figure 2.2: ID vs. VGS and ID vs. VDS characteristics of the DG Tunnel FET

Chapter 2. Double Gate Tunnel FET

18

can be seen in the Fig. 2.3. This feature can make the device highly suitable for analog applications such as ampliers and current mirrors.
10
5

GmRo Product

10

10

10

VGS =1V VGS=1.2V VGS=1.4V

10

0.5 VDS (V)

1.5

Figure 2.3: The Gm *Ro versus VDS for various VGS near the operating point. According to Kanes model [20] of BTBT, the relation for Band to Band Tunneling current is given by Equ. 1.3. Using this relation, an expression (Equ. 2.1) for the Subthreshold Swing (S) of Tunnel transistors has been derived in [26]. A detailed derivation of the equation can be seen in the appendix. DVGS 2 2DVGS + Bkane Wg 3/2

S=

(2.1)

This derivation is based on the following two assumptions: 1. The tunneling width ( ) , which is gate controlled, is independent of the drain bias, this can be seen from the band diagrams in Fig. 2.4. 2. The tunneling electric eld (E) is also fairly independent of the drain bias and can be approximated by a relation E = DVGS 2 , where D is a constant determined by various device parameters such as Doping concentration (N), drain bias (VDS ), oxide thickness (tox ) and channel length (L). From Equ. 2.1, it is seen that the S of tunnel FET is a strong function of the gate voltage (VGS ). hence, the value of S is very low for lower gate voltages (sub-threshold

Chapter 2. Double Gate Tunnel FET

19

Figure 2.4: Simulated band diagrams of VTFET (near the surface region) with increasing VDS at xed VGS =0. The tunnel barrier is nearly independent of VDS [26] region) but degrades considerably for higher gate voltages (saturation region). Fig. 2.5 shows the variation of S as a function of the gate voltage for the double gate tunnel FET. However, it is observed that the the assumptions made to derive Equ. 2.1 are true only in the surface region (the region very close to the oxide channel interface) of the device where the bands bend under the eect of the gate workfunction. In the bulk region, since the intrinsic channel if fully depleted, the bands in the channel are straight lines (Fig. 2.6) as compared to the curved bands in case of surface region. Therefore, as clearly seen in Fig. 2.6, the tunneling width ( ) in the bulk region reduces considerably with an increase in drain bias. It is also observed (Fig. 2.7) that the tunneling electric eld (E) is fairly constant with respect to VDS in the surface region but increases linearly with the drain bias in the bulk region. Since the eect of gate is negligible in the deep seated region of the device, this region is responsible only for the o-state current (IOF F ) of the device. Thus, the reduction in and an increase in E with an increase in the drain bias should lead to an increase in the IOF F of the device. As a result of that, the ION /IOF F ratio should

Chapter 2. Double Gate Tunnel FET

20

250 S.S. (mV/decade) 200 150 100 50 0 0

TSi=100nm L=100nm

Subthreshold region

0.5 VGS

1.5

Figure 2.5: Point Sub-threshold swing (S) of DG Tunnel FET as a function of the gate voltage. (VDS =1V). S degrades considerably as the device moves from sub-threshold to saturation region

Figure 2.6: Simulated band diagrams of DGTFET (in the bulk region) with increasing VDS at xed VGS =0. Tunneling barrier reduces signicantly due to increase in VDS

Chapter 2. Double Gate Tunnel FET

21

(MV/cm)

0.18

EBULK ESURFACE

E.SURFACEMAX (MV/cm)

1.8 1.7

0.16

1.6 1.5 1.4 1.3

E.BULK

MAX

0.14

0.12

1.2 1.1

0.1 0

0.5

DS

(V)

1.5

1 2

Figure 2.7: Simulated maximum electric eld Emax , across the tunnel junction as a function of VDS in the bulk and surface regions of the device. the eld is independent of VDS at the surface but increases linearly with drain bias in the bulk region. degrade at higher VDS We also need to note that Equ. 2.1 does not take into account the variation of and E with respect to VDS in the bulk region. Hence, the value of S predicted by this equation will not be very accurate. Also, one should keep in mind that this (deviation) happens only at higher drain voltages. The obtained values of S agree very well with expected values at low drain bias. Fig. 2.8 shows the variation in the minimum point sub-threshold swing (Smin ) and ION to IOF F ratio with VDS for a xed device. For very low drain voltages (below 0.4V), ION of the device is very low and as a result, the ION /IOF F ratio is not very good. The device shows excellent parameters for VDS between 0.4 and 1.2V. However, as we increase the drain bias above this value, both these parameters degrade drastically. From the analysis above, we can conclude that signicant reduction in IOF F of the device can be achieved without aecting the ION if the thickness (TSi ) of the device is reduced. The above conclusion of was veried using 2D device simulations in Medici. The thickness of the double gate structure in Fig. 2.1 was varied and the results noted down. It was found that ION /IOF F ratio and the sub-threshold swing improved considerably

Chapter 2. Double Gate Tunnel FET

22

10

15

L=100nm T =100nm
si

ON

/I

120 100

OFF

SMIN

S (mV/decade)

80 10
ON OFF
10

60 40 20

MIN

/I

10

0.5

DS

(V)

1.5

0 2

Figure 2.8: Simulated ION to IOF F ratio and minimum point sub-threshold swing as a function of VDS . As predicted, both the values degrade a lot at higher drain bias

10 10
ON OFF

13

12

L = 100nm VDS = 1V

120 I /I ON OFF SMIN 100

10 10 10

11

80 60

MIN

(mV/decade)

/I I

10

40
9

20 0 100

10

20

40

60

80

Tsi (nm)

Figure 2.9: Simulated ION to IOF F ratio and minimum point sub-threshold swing as a function of TSi . As expected, both the parameters improve when the body thickness is reduced

Chapter 2. Double Gate Tunnel FET

23

for the thin body device when compared to the thicker structure. Fig. 2.9 shows the improvement in device behavior with reduction in TSi . The ION /IOF F is seen to degrade for TSi less than 10nm. This is because for very thin structures, the on-current (at VGS =1.5V) starts to drop (due to the reduction in cross sectional area). Hence, there is a maximum in the ION /IOF F vs TSi curve at TSi 10nm.

2.5

Floating Body Eect

Unlike the conventional transistor, where there is a high eld at the reverse biased drain substrate junction, in TFET, the high eld region is the tunneling junction which is formed near the source channel junction. Also, the barrier between the p-type channel and the p+ source is negligible (compared to the p-n+ barrier in case of a MOSFET). Because of these reasons, any charge that is generated, gets ushed out through the source straight away. Thus, there are no oating body eects in the double gate Tunnel Field Eect transistor.

2.6

Scaling of Double Gate TFET

As we have seen, the active region of the TFET is only the tunneling junction between the source and the intrinsic region of the structure. as a result, the device performance is nearly independent of channel length. this was veried using 2D device simulations. It was found that the main device parameters (namely the sub-threshold swing and ION /IOF F ratio) were found to remain unchanged upto a channel length of 30nm. However, the parameters degraded below this value of the channel length. This is because the gate length is too less and as a result, the gate is not able to bend the bands enough for conduction to take place. Fig. 2.10 shows variation in log10 (IDS ) vs VGS curves with channel length.

Chapter 2. Double Gate Tunnel FET

24

L = 20nm L = 30nm L = 50nm L = 100nm

Vds = 1.0V

-15 0.00

log(I(Drain)) (A/um) -10

-5

0.50

1.00

1.50 V(Gate) (V)

2.00

2.50

3.00

Figure 2.10: Simulated ID vs VGS characteristics of the DG Tunnel FET with dierent channel lengths. The characteristics start deviating from normal when the Length is 20nm or lower

2.7

Conclusion

In this work, the Double Gate TFET was explored using 2D device simulations. Due to the tunneling mechanism involved in its carrier transport, unlike the MOSFET, TFET does not have any physical lower limit to the sub-threshold swing. Also, due to the reverse biased structure, the leakage current is extremely low. Both these properties make the TFET highly suitable for Low-Standby Power applications. It is observed that the bulk of the device plays a major role in degrading the ION /IOF F ratio and the S of the device. Using simulations, it is veried that both these parameters can be improved by reducing the thickness (and hence the amount of bulk region) of the device. It is also seen that the TFET performance is nearly independent of the channel length and the device (in its present form) can be easily scaled upto 30nm channel lengths.

Chapter 3 Tunnel FET with SiGe layer at Source

3.1 Introduction

As we have seen in the earlier chapters, due to extremely low IOF F and excellent switching characteristics, the Tunnel Field Eect Transistor (TFET) has attracted a lot of attention for Low Stand-by Power (LSTP) applications. However, in spite of excellent sub-threshold swing and high ION /IOF F ratio, the very low ION is the main issue with this device. Previously reported Tunnel FET designs either suer from low ION [14] (due to the reverse biased pin structure and high bandgap of silicon) or involve complex fabrication process steps [15]. Recently, ON current improvement has been reported using HK gate dielectric [27]. However, it does not take into account the mobility degradation related to High- material, gate dielectric breakdown due to high eld across the very thin high- material and fabrication issues involved. In this work, a new classical MOSFET alike Tunnel FET architecture is proposed, which oers sub-60mV/decade sub-threshold swing with a signicant improvement in ION . The enhancement in ION is achieved by introducing a thin SiGe layer on top 25

Chapter 3. Tunnel FET with SiGe layer at Source

26

of the Silicon Source. With the help of TCAD simulations, it is demonstrated that the proposed device is naturally immune to short channel eect (SCE) and can be fabricated with standard CMOS process steps. It is observed that the body bias does not aect the drain current but the body current gets aected. Another original nding is that the introduction of SiGe layer makes the device immune to Drain induced Barrier lowering (DIBL) eect and the ION increases exponentially with Ge mole fraction. It is noted that if proposed architecture is coupled with high- material (as proposed in [27]) additional boost in drive current can be achieved with a thicker gate dielectric.

3.2

Device Structure and Operation

The device being investigated is a lateral n-type Tunnel FET with a SiGe layer on the top of the source. The Tunnel FET is a gated reverse biased p+ i n+ structure which uses the principle of gate controlled band to band tunneling for its operation. The proposed device is shown in Fig. 3.1
GATE DRAIN SOURCE 11111 00000 0000011111111 11111 00000000 A B 00000000 11111111 Xj=40nm 00000000 11111111 p+ Si
strained SiGe Layer (depth=Ld)

n+ Si

Ptype Si Substrate

Figure 3.1: Schematic of the proposed n-type TFET structure with SiGe layer at Source. For all simulations, tox = 2nm, drain doping(n+) = 5 x 1019 and source doping(p+) = 1 x 1020 was used. Germanium mole fraction (x) was varied from 0.0 to 0.5 in steps of 0.1 To operate the device, the p+ source is grounded, a positive voltage (1V) is applied to the n+ drain and a voltage is swept across the gate. The simulated band diagrams are shown in Fig. 3.2. In the absence of a gate voltage (non-conducting region), the tunneling barrier height is much higher than 10nm (the approximate minimum required

Chapter 3. Tunnel FET with SiGe layer at Source

27

for tunneling to take place in silicon). However, on application of positive gate voltage, the bands in the intrinsic (lowly doped) region are pulled downwards and a tunneling junction is created at the junction of the p+ - source and the intrinsic channel. Due to the reduction in tunneling width and electric elds produced, zener tunneling of electrons takes place from the valance band of the source to the conduction band of the channel and the device turns ON. One should note that this behavior is exactly same as the NMOS in the CMOS technology. Hence, this can be called as an n-type tunnel FET.

1.5 1 0.5 Energy (eV) 0 VGS = 0V VGS = 2V VDS =1.0V e 1 n+ drain p channel p+ source

EC EV

0.5

1.5 2 2.5 0.2

0.25

0.3 0.35 0.4 Distance (m)

0.45

0.5

Figure 3.2: Simulated band diagrams (along the cut section AB in Fig. 3.1) of the ntype TFET in non-conducting and conducting regions. The large reverse biased barrier insures extremely low IOF F For a Tunnel FET, the ON current is proportional to the electron/hole transmission probability T(E) in the Band to Band tunneling mechanism, which is given by [24]: 4 2m Eg 3/2 Si tox tSi T (E ) = exp 3|e| (Eg + ) ox (3.1)

where, m is the carrier eective mass, e is the electron charge, Eg is the bandgap, is the energy range over which tunneling can take place, and tox ,tSi ,ox and Si are the oxide and silicon lm thickness and di-electric constants, respectively.This equation shows

Chapter 3. Tunnel FET with SiGe layer at Source

28

that decreasing oxide thickness (tox ) [26], increasing oxide dielectric constant (ox ),and reducing bandgap (Eg ), will enhance the performance of the device. Boucart and Ionescu [27] have proposed the use of High- materials as the gate dielectric (high ox in Eq. 3.1) in order to increase ON current (ION ). In this work, ION enhancement has been done by modulating the bandgap (Eg ) by using a strained SiGe layer at the source end and varying its germanium mole fraction (x). As the electron/hole eective mass m does not change too much with mole fraction (x), its impact on ION could be ignored. The device performance is sensitive to the doping concentration of source and abruptness of doping prole at source-channel interface [14]. The doping of source, substrate and drain regions chosen to optimize ION respectively are 1 x 1020 , 1 x 1016 and 5 x 1019 cm3 . Device performance is very sensitive to Gate work function as reported in [26], but we have used n+ Polysilicon compatible to CMOS process ow for gate material. A constant oxide thickness (tox = 2nm) and channel length (L = 100nm) is chosen for all simulations.

3.3

Simulation Models and Device Parameters

2D Device and process simulations were performed in Medici[21] and Tsuprem4[22] respectively. Field dependent Kanes model[20] available in Medici is used to model the band to band tunneling generation and recombination rate. Kanes model has been shown to give a good match for band to band tunneling in silicon based tunnel transistors at both high and low temperatures[9]. Since the source region is heavily doped, and tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also included in the simulations. Fermi Dirac statistics, although they are computationally less ecient, are used instead of Boltzmann approximations for the same reason. The BTBT model in Medici is congured in such a way that it uses the average tunneling eld while solving the pre-exponential and the path integral eld while solving the exponential in the tunneling rate. Also a recursive renement procedure is used that further improves the accuracy of the simulations. Also, non local tunneling is enabled

Chapter 3. Tunnel FET with SiGe layer at Source

29

which causes the electrons to be generated at the end of the tunneling path as implied by the tunneling physics. A small aside on how the device characteristics, namely the subthreshold swing, VT H and the ION , are calculated. Unlike the MOSFET, where there is a clear transition from the sub-threshold to the saturation region when plotted on the semilog scale, in TFET the slope (of log10 ID ) is an exponential function of VGS . The slope is very steep for lower VGS but becomes less and less steeper as the gate voltage increases. Therefore, the threshold voltage cannot be extracted using the standard MOSFET techniques. Hence, as discussed in [25] VT H is calculated by a constant current method at IV T = 107 A/m. The average subthreshold swing is extracted by taking the average between the gate voltage at which the ID begins to increase and the threshold voltage. This method has been explained in detail earlier by [26] and [27] and is considered to be a consistent way to dene S for TFETs. ION is calculated at VGS = VDS = 1.2V as per the voltages specied by ITRS for LSTP applications at the 65 nm node. All results obtained from MEDICI are also veried using ATLAS [29], version 5.12.1.R, using the nonlocal Hurkx band-to-band tunneling model [30]. It is found that the simulations show exactly same trend with slightly lower IOF F in the case of ATLAS. However, in this work, we report results which are obtained from MEDICI.

3.4
3.4.1

Results and Discussion

The SiGe layer

As discussed earlier, a SiGe layer is introduced at the top of the source in the conventional Tunnel FET to achieve an improvement in the ON state current. Fig. 3.3(a) shows the eect of varying the Germanium molefraction in the equilibrium band diagrams of the proposed device. As expected, the Bandgap at the source end reduces as we increase the Ge molefraction (x). This results in a reduction in the tunneling bandgap and consequently an increase in the Transmission probability in Equ. 3.1 which in turn, increases the BTBT current. Fig. 3.3(b) shows how the bands vary under the eect

Chapter 3. Tunnel FET with SiGe layer at Source

30

1.5 1 Energy (eV) 0.5 0 0.5 1 1.5 0.25

x=0.0 x=0.2 x=0.5 Fermi level

0.3

0.35 0.4 Distance (m)

0.45

(a) Equilibrium Band diagrams of the proposed TFET structure for various values of Ge mole fraction (x)

VGS= 0V

x=0.5V

Energy (eV)

3 0.25

VDS=0V VDS=1.5V 0.3 0.35 0.4 Distance (m) 0.45

(b) Eect of Drain voltage on the device band diagrams. It is seen that the tunneling width remains nearly independent of the applied drain bias. Thus insuring high immunity to DIBL

Figure 3.3: Simulated Band Diagrams of the proposed Tunnel FET architecture in Fig. 3.1 along the cut section (AB)

Chapter 3. Tunnel FET with SiGe layer at Source

31

10

10 ID(A/m)

10

10

x=0.0 x=0.2 x=0.3 x=0.5

10

VDS=1.0V VDS=0.1V 1.5 2

0.5

1 VGS(V)

(a) Simulated transfer characteristics of the device for various values of Ge mole fraction (x) for linear and saturation VDS .

7 6 5

VGS=1.2V VGS=1.3V VGS=1.4V x = 0.1

ID (A/m)

4 3 2 1 0

0.5

1 VDS (V)

1.5

(b) Output characteristics of the TFET with SiGe layer at the Source end.

Figure 3.4: Simulated Device characteristics for the proposed device

Chapter 3. Tunnel FET with SiGe layer at Source

32

of Drain bias. As can be seen there is negligible change in the tunneling bandgap with increase in VDS . This means that the device should be immune to Drain Induced Barrier Lowering (DIBL). The Transfer and Output characteristics of the proposed device are shown in the Fig. 3.4. As expected, in Fig. 3.4(a) we observe that, the over all drain current and specially the ON current increases as we increase the germanium mole fraction. Fig. 3.4(b) shows the output characteristics of the device. Due to the reverse biased p-i-n structure, the output impedance of the device is very high. This is also seen in the IDS vs. VDS curves where the drain current current is almost constant in the saturation region. In accordance with Equ.3.1, we observe in Fig.3.5 that, the increase in ION is exponentially dependent on the reduction in Eg (which reduces linearly with increase in germanium mole fraction (x)). Also, this increase in ION leads to a reduction in the average subthreshold swing of the device since now the threshold voltage falls in the steeper region of the curve. An ION of 580A/m, IOF F of 1.04fA/m and an average S of 13mV/decade are achieved for x=0.7 with VDD =1.2V
120 600

Subthreshold Swing (mV/dec.)

S.S.
100 80 60 40 20 0

ION

VDS=1.2V VGS=1.2V LD=20nm

500 400 300 200 100 0 0.7

0.1

0.2 0.3 0.4 0.5 Ge Mole Fraction (x)

0.6

Figure 3.5: The avg. sub-threshold swing (S) and ION vs. x. ION increases exponentially with x. However, the IOF F remains in the order of fA (IOF F = 1.04fA/m at x = 0.7)

ION(A/m)

Chapter 3. Tunnel FET with SiGe layer at Source

33

Figure 3.6: A zoomed view of the tunneling junction of the TFET. 2D simulations show that the band to band generation is limited to the top 20nm layer of the device (when it is biased in the operating region)

3.4.2

Depth of SiGe Layer (Ld )

The conventional TFET is a surface tunneling device and the active region of the device is situated right at the surface near the channel-source junction. From 2D device simulations, it is observed that the band to band generation rate is maximum at the surface and has some practical value only in the top 20nm layer of the device (Fig. 3.6). Therefore, it is believed that increase in ION can be achieved by reducing bandgap only in this 20nm region right below the surface. This fact is veried in Fig. 3.7 where we observe that the ION of the device increases as we increase the depth of SiGe (Ld ) layer to 20nm but does not increase further as we increase Ld beyond this value. Any additional increase in the SiGe layer depth only causes an increase in the IOF F of the device. It is also observed in Fig. 3.7 that the eect of Ld becomes more prominent as the value of the mole fraction (x) is increased.

3.4.3

Eect of Body bias

Since the investigated device is a p+ -pn+ structure, unlike the MOSFET, there is a p+ -p junction between the source and the body. As a result of this, there could be a

Chapter 3. Tunnel FET with SiGe layer at Source

34

600 500

ION(A/m)

400 300 200 100 0

x=0.1 x=0.3 x=0.5 x=0.7

10 15 20 Depth of SiGe Ld(nm)

25

30

Figure 3.7: ION as a function of the depth of SiGe layer (Ld ). ION increases with an increase in Ld up to a depth of 20nm. increasing Ld beyond this value does not help in increasing ION as it falls beyond the active region of the device direct path (short circuit) between these two terminals depending on body bias. Hence, application of a body bias does not aect the ID -VGS characteristics of the device. On the contrary, it adds up a large leakage current (of the order of A) component from the bulk to the source (Fig. 3.8). It is observed that this current component is more in case of negative body voltage as the p-p+ junction is forward biased in that case.

3.4.4

SCE and DIBL

The active region of the TFET is only a very small region near the surface at the channel source interface. This, along with the large reverse biased barrier, makes the TFET a highly scalable device. It has been shown that the device can be scaled up to channel lengths as small as 30nm without aecting its performance. Fig. 3.9 shows the eect of channel length and drain bias on the threshold voltage (VT H ) of the device. VT H values, which are quite high for x=0, agree well with ITRS requirements [23] for higher values of x. Also, it is observed that there is virtually no DIBL for higher values of x

Chapter 3. Tunnel FET with SiGe layer at Source

35

10 0 IBULK (A/m) 200 400 600 800 VBS= 0.8V 0.5 1 VGS (V)
(a) Eect of negative body bias

VBS= 0.1V VBS= 0.3V VBS= 0.5V 10

2

ID (A/m)
6

1000 1200 0

10

1.5

16 14 VBS=0.8V IBULK (A/m) 12 10 8 VBS=0.5V VBS=0.3V

10

10

VBS=0.1V 0.5 V 1
GS

10

ID (A/m)
6

1.5 (V)

(b) Eect of positive body bias

Figure 3.8: Eect of Body bias on device performance. The ID -VGS characteristics remain un-altered but the bulk current increases linearly with increase in bulk terminal potential.

Chapter 3. Tunnel FET with SiGe layer at Source

36

(above x=0.3). This is because, the barrier height (which is directly proportional to the tunneling bandgap) is a much stronger function of x than VDS . Therefore, as we increase the mole fraction, the lowering of bandgap by x dominates the lowering of bandgap by VDS .

1.5 Threshold Voltage (V)

x=0.0 1

0.5 x=0.3 0 0 VDS=0.1V VDS=1.0V 200

50 100 150 Channel Length (nm)

Figure 3.9: SCE and DIBL in the proposed device. A reduction in VT H (as a result of reduction in barrier height) is seen with an increase in x. DIBL also disappears with an increase in x

3.4.5

High material as gate dielectric

In [27], the use of High materials to improve the ION of the device has been reported. The thickness of the dielectric material needed to achieve this improvement in ION is very small (3nm). It may not be practical to use such thin HK dielectric as their breakdown voltages are much smaller compared to SiO2 . However, if the same technology is used with the proposed TFET design, it is possible to achieve very good ION even for a thicker, more realistic physical dielectric thickness (5nm). Fig. 3.10 shows the transfer characteristics comparing the two devices with dierent dielectric constants (HfO2 and SiO2 ) for two dierent values of germanium mole fractions. It is seen that a very high

Chapter 3. Tunnel FET with SiGe layer at Source

37

ION (nearly 1mA/m) can be achieved if both the techniques are combined.

10

VDS=1.0V 10 ID (A/m)
0

10

HfO2,x=0.0 10
6

HfO2,x=0.3 SiO2,x=0.0 SiO2,x=0.3 0 0.4 0.8 1.2 VGS (V) 1.6 2

10

Figure 3.10: Combination of High (=29) along with the SiGe layer at the source end helps in achieving much better ION and sub-threshold swing for realistic physical thickness. Tdielectric = 5nm in this case. IOF F = 19.79pA/m for High K dielectric with x = 0.3

3.4.6

Eect of Strain on the channel

The reasons behind adding the SiGe layer only to the source region are twofold. First, the active region of the device is located only at the source-channel junction and the drain voltage does not play any role in BTBT tunneling. Second, adding SiGe to the drain also would add strain to the channel from both sides. This strain in the channel may increase/reduce the carrier mobility. Therefore, it is very dicult to predict the eect of stress and requires further investigation. In fact the proposed device will operate with same eciency if we use fully Silicon-Germanide source instead of SiGe layer on the top of a Si Source. However, we propose SiGe layer source in order to minimize the eect of stress on the silicon channel. The eect of strain on the Si channel is not considered in this work due to non availability of proper models in the simulator.

Chapter 3. Tunnel FET with SiGe layer at Source

38

0.9

Strained SiGe Relaxed SiGe Band Gap (eV)

0.8

0.7

0.6

0.5 0.3

0.4

0.5 0.6 Ge Mole fraction (x)

0.7

Figure 3.11: Band gap of strained SiGe and Relaxed SiGe for dierent values of Ge mole fraction. Strain tends to reduce the band gap and thus helps in improving ION

3.4.7

Eect of Strain on on SiGe layer

The eect of strain on SiGe bandgap is shown in Fig. 3.11. The band gap values are extracted from 2D simulations in Medici. It is observed that strain tends to reduce the band gap of the SiGe layer. This further helps in improving the ION of the device. Thus, it is desirable to have a strained SiGe layer at the source.To obtain 20nm or more thick layer of strained SiGe over Si with Ge mole fraction x=0.7 is a challenging technology problem (it can be obtained by growing over relaxed SiGe) [31]-[32].However, the same ION can be obtained with lower Ge mole fraction by decreasing tox (compromising with gate leakage).

3.4.8

Lateral vs. Vertical TFET

The concept of using the SiGe layer in the proposed device is the same as in the Vertical channel TFET proposed in [15] (i.e. to improve the ION of the device). However, there are a few dierences in the two structures which cause the eect of the SiGe layer to

Chapter 3. Tunnel FET with SiGe layer at Source

39

be slightly dierent for the device proposed here. The main dierence between the structures is that the VTFET proposed in [15] is very much like a vertical form of the double gate TFET in chapter 2 with the thin SiGe layer spread all across the channel. Thus, there is a reduction in the bandgap all across the junction of source and channel. As we had seen in the 2nd chapter, the bulk region plays a major role in determining the o state current of the device. Thus, since the SiGe layer is placed all across the channel, the o state current too goes up signicantly with an increase in the germanium mole fraction. As a result, additional techniques such as gate work function modulation are needed to reduce the o state current [26]. In the lateral device proposed over here, the bandgap reduction occurs only at the tunneling junction and thus only results in an increase in the ION without aecting the IOF F by much. Thus, there is no need of additional changes in the gate material.

3.5

Fabrication of The Proposed Device

A process ow compatible with standard CMOS process to fabricate the proposed Tunnel FET with SiGe layer was designed using 2D Process simulations in Tsuprem4 [22]. The device can be fabricated with slight modications in the standard CMOS process ow after Gate stack formation. The following main changes are needed for fabricating the proposed device: 1. A new set of masks is needed to incorporate a n+ drain and a p+ source in the same device. (unlike the conventional NMOS where we had n+ in both source and drain regions.) 2. To get the SiGe layer at the source, additional steps of isotropic etching of Si and epitaxial deposition of SiGe are needed.

Chapter 3. Tunnel FET with SiGe layer at Source

40

3.5.1

Description of Process steps

Fig. 3.12 shows the device in various stages of process simulation. Here we show only those steps which are dierent from the standard CMOS steps. Fig. 3.12(a) shows the photoresist mask necessary to dope the n+ drain and gate regions. This doping is achieved by Ion implantation of Arsenic followed by annealing. An active doping of approx. 5 x 1020 cm3 has been achieved. After the gate and drain doping, the another mask is prepared which covers these two regions and with the help of this mask, silicon in the source region is etched away (Fig. 3.12(b)). This is followed by epitaxial deposition of Boron doped p+ silicon. As shown in Fig. 3.12(c), this deposition is only partial and does not form the full source. The rest of the source (the SiGe layer) is deposited using epitaxy of Boron doped silicon with germanium (Fig. 3.12(d). The epitaxy process helps in achieving abrupt doping prole at the source end which has been shown to achieve better ION for the silicon TFET [28].

3.5.2

Impact of Mask Misalignment

As we have seen, a set of two complimentary masks is required to fabricate the tunnel FET with SiGe layer. During these photo steps, it is inevitable to have an overlay error. The eect of mask alignment on the conventional Tunnel FET performance has already been studied by T. Nirschl et al for the 130nm technology [33]. Here, the authors consider the ION to IOF F ratio as the performance benchmark for the device. In this study, the authors have reported that, the mask misalignment improves the performance of the TFET when there is a positive overlap (i.e. the photoresist mask covering initially covering only the source is shifted slightly towards the drain side and now partially covers the Gate). However, the performance degrades when there is a negative overlap (referred as underlap from here onwards) (i.e. the photo-resist is shifted away from the drain and does not fully cover the source). For the proposed device, an underlap would be even more depreciating in terms of its performance as it would mean that there is no SiGe at the tunneling junction.

Chapter 3. Tunnel FET with SiGe layer at Source

41

(a) Drain and Gate doping mask used for Ion im- (b) Mask used for etching the Source. The mask plantation leaves some part of the gate partially open to avoid Gate to Source underlap due to process variations. Xj =40nm

(c) Partial deposition of p+ Source (upto 20nm) (d) Deposition of p+ SiGe layer on top of the p+ source using epitaxy with Boron as impurity using epitaxy with Boron as impurity

Figure 3.12: Modications needed in the standard CMOS process ow to fabricate the proposed Tunnel FET structure

Chapter 3. Tunnel FET with SiGe layer at Source

42

According to the 2006 ITRS update [23], a variation of 10nm is expected in the present day lithography techniques. This much underlap is enough to degrade the performance of the tunnel FET with SiGe layer and limit its ON current to lower than or equal to the conventional TFET. Therefore, it is advisable to start with an initial positive overlap of 10nm so as to avoid an underlap. (Fig. 3.13)

Figure 3.13: The Photoresist mask covering the p+ source is made to overlap the gate by 10nm in the beginning so as to cancel out any chance of an underlap being formed due to mask overlay This would mean that there would be a worst case positive overlap of 20nm (assuming a 10nm variation of the mask in the other direction. This would result in a structure in which a part of the gate is p+ SiGe and causing a shift in the net work function of the gate. The net work function calculated by averaging the work functions of each of the regions shows a good match with actual data [33]. The eect of Gate work function has been discussed in [26] and shows that an increase in gate function would result in a slight reduction in the ON state current but an improved average sub-threshold swing of the device and much more improvement in IOF F . Hand calculations show that the net increase in work function for a 100nm long gate is about 0.044eV (from 4.17eV to 4.214eV) and simulations show that there isnt any noticeable change in the device characteristics.

3.6

Conclusion

A novel Silicon Tunnel FET architecture with SiGe layer at source is proposed and analyzed using 2D device simulations. The proposed device is nearly free of SCE and

Chapter 3. Tunnel FET with SiGe layer at Source

43

DIBL and can be scaled upto channel lengths of 30nm. The proposed device shows orders of improvement in ON current over the conventional TFET with the added advantage of compatibility with CMOS fabrication steps. A process technique to fabricate the device is also designed using 2D process simulations.

Chapter 4 Conclusion and Scope of Future work

In this work, we have discussed the shortcomings of the present day MOSFET as a switching device and how it adversely aects the Low Stand-by Power applications such as mobile phones, PDAs etc. These shortcomings of the MOSFET are essentially due to the drift diusion mode of carrier conduction which limits its sub-threshold swing to a minimum of 60mV/decade at the room temperature. The only way to overcome this physical limit is to change the mode of carrier conduction of the device. Among the available alternatives, the Tunnel Field Eect Transistor (TFET), which is based on the principle of gate controlled interband tunelling, appears to be the most promising device. We have seen that there is no theoretical lower limit of the subthreshold swing for TFET and also due to the reverse biased p-i-n structure, it has very low IOF F and is naturally immune to the Short Channel Eect (SCE). However, in spite of excellent sub-threshold characteristics and very low IOF F , the device fails to meet the technology requirements of ION and that is the main issue with this device. 2D device simulations are used to gain some insight into the device behavior. It is seen that the active area of the device is a very small area near the gate oxide at the channel source interface and the bulk region contributes only to the IOF F . To overcome the problem of low ION , we have proposed a novel TFET architecture (with 44

Chapter 4. Conclusion and Scope of Future work

45

a strained SiGe layer at the source) which can be fabricated with slight modications in the standard CMOS process ow and shows orders of improvement in the ON current of the device. It is found that the proposed device is scalable up to channel lengths as small as 30 nm without aecting its performance. Also, the eect of DIBL reduces as we increase the Ge molefraction (x) and in fact, it nearly reduces to zero for x 0.3. Since, TFET is a surface conduction device, the depth of strained SiGe layer needed to achieve the improvement in ION is very less ( 20nm). It is also seen that the body bias has very little impact on the device performance and the VT is purely dependent on the oxide thickness, doping at source and the gate workfunction. In the end, to fabricate the proposed device, a process ow compatible with the standard CMOS process steps is also designed using 2D process simulations. Working on this thesis has exposed a couple of other issues about the Tunnel FET which need to be addressed before it can actually be used in commercial circuits.

4.1

Process Challenges

As discussed earlier in Chapter 3, the fabrication of the proposed Tunnel FET with a Ge rich strained SiGe layer of 20 nm thickness is a challenging proposition for the process engineer. Growing a strained SiGe layer over a relaxed SiGe layer is an alternative but that makes the process much more complex and time consuming. Also, Boron is used as the impurity for the p+ source and it has a very high diusivity in silicon. Because of this boron diusion, the source region extends to some distance under the gate. However, the SiGe layer which is deposited epitaxially does not form an overlap with the gate. As a result of this, the tunneling junction is formed slightly away from the Si-SiGe interface and consequently, the advantage of using the SiGe layer is lost. Thus, the key process challenges are to deposit a 20nm thick SiGe layer and to avoid/minimise the Boron diusion at the source.

Chapter 4. Conclusion and Scope of Future work

46

4.2

Pass Transistor Behavior

The Tunnel FET being a gated p-i-n diode is not a symmetrical structure like the conventional MOSFET. Therefore, its performance as a pass transistor is a questionable as the diode will always conduct in the other direction (irrespective of the potential at the gate terminal). A pass transistor is a major building block when it comes to CMOS circuits. Hence, if the Tunnel FET has to replace the conventional MOSFET, this is an issue which needs to be resolved.

Appendix A Sub-threshold Swing of Tunnel Transistors

According to Kanes model [20] of band to band (B2B) tunneling, the B2B generation rate is given by GB2B = AKane E 2 Wg 1/2 eBKane Wg
3/2

/E

(A.1)

where Akane and Bkane are material dependent constants, E is the electric eld at the tunneling junction. It is found that, at high values of VGS , E is nearly independent of VDS . Therefore, we can say that E = DVGS , where, D is a function of drain bias (VDS ), channel doping (N), oxide thickness (tox ) and channel length (L). D = f (VDS , N, tox , L) Since, IDS GB2B , IDS = AKane (DVGS )2 Wg 1/2 eBKane Wg
3/2 /(DV GS )

(A.2)

(A.3)

47

Appendix A. Sub-threshold Swing of Tunnel Transistors

48

Taking logarithm on both sides, we get ln(IDS ) = ln AKane D 2 (VGS )2 BKane (Wg )3/2 (Wg (1/2) DVGS (A.4)

Dierentiating both sides w.r.t. VGS , 2DVGS + BKane (Wg )3/2 d(ln(IDS )) = dVGS D (VGS )2 (A.5)

S=

dVGS D (VGS )2 = d(ln(IDS )) 2DVGS + BKane (Wg )3/2

(A.6)

Bibliography
[1] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, 1st South Asian Edition, Cambridge university Press. p.p. 128 [2] S. M. Sze, Physics of Semiconductor Devices, 2nd edition New York, Wiley. p.p. 147 [3] Qin Zhang, Wei Zhao, Alan Seabaugh, Low Subthreshold-Swing Tunnel Transistors IEEE EDL, Vol. 27, pp. 297300, Apr 2006. [4] P.F. Wang, T. Nirschl, D. Schmitt-Landsiedel, and W. Hansch, Complementary tunneling transistor for VLSI application, Proc. IEEE Silicon Nanoelectron Workshop, 2004, pp. 1516. [5] M. Sterkel, P.F. Wang, T. Nirschl, B. Fabel, K.K. Bhuwalka, J. Schulze, I. Eisele, D. Schmitt-Landsiedel and W. Hansch, Characteristics and optimization of vertical and planar Tunneling FETs, Journal of Physics: Conference series 10, 2005, pp. 1518. [6] K. Gopalakrishnan, P. Grin, J. Plummer, I-MOS: a novel semiconductor device with a subthreshold slope lower than kT /q , IEDM Tech Digest 2002, pp. 289292. [7] J. Quinn, G. Kawamoto, and B. McCombe, Subband spectroscopy by surface channel tunneling, Surf. Sci., vol. 73, pp. 190196, May 1978. [8] T. Baba, Proposal for surface tunnel transistors, Jpn. J. Appl. Phys., vol. 31, no. 4B, pp. L455L457, Apr. 1992.

49

BIBLIOGRAPHY

50

[9] W. Reddick and G. Amaratunga, Silicon surface tunnel transistor, Appl. Phys. Lett., vol. 67, no. 4, pp. 494496, Jul. 1995. [10] J. Koga and A. Toriumi, Three-terminal silicon surface junction tunneling device for room temperature operation, IEEE Electron Device Lett., vol. 20, no. 10, pp. 529531, Oct. 1999. [11] W. Hansch, C. Fink, J. Schulze, and I. Eisele, A vertical MOS-gated Esaki tunneling transistor in silicon, Thin Solid Films, vol. 369, no. 1/2, pp. 387389, Jul. 2000. [12] C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, Lateral interband tunneling transistor in silicon-on-insulator, Appl. Phys. Lett., vol. 84, no. 10, pp. 17801782, Mar. 2004. [13] J. Appenzeller, Y.M. Lin, J. Knoch, and P. Avouris, Band-to-band tunneling in carbon nanotube eld-eect transistors, Phys. Rev. Lett., vol. 93, no. 19, pp. 196805 1196805-4, Nov. 2004. [14] P.F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt Landsiedel, and W. Hansch, Complementary tunneling transistor for low power application, Solid State Electron., vol. 48, no. 12, pp. 22812286, Dec. 2004. [15] K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, I. Eisele, Vertical Tunnel eld Eect Transistor, IEEE Tran. Elec. Dec., vol. 51, no. 2, pp. 279282, Feb. 2004. [16] K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele, Pchannel tunnel eld-eect transistors down to sub-50 nm channel lengths, Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 31063109, Apr. 2006. [17] K. Bhuwalka, J. Schulze, and I. Eisele, Performance enhancement of vertical tunnel eld-eect transistor with SiGe in the delta p+ layer, Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 40734078, 2004.

BIBLIOGRAPHY

51

[18] M. Born, K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, Tunnel FET: A CMOS device for high temperature applications, in Proc. 15th Int. Conf. Microelectron., 2006, pp. 124127. [19] Q. Zhang, W. Zhao, and A. Seabaugh, Analytic expression and approach for low subthreshold-swing tunnel transistors, in Proc. DRC, Santa Barbara, CA, Jun. 2022, 2005, pp. 161162. [20] E.O. Kane, Zener tunneling in semiconductors, J. of Phy. Chem. Solids, vol. 12, no. 2, pp. 181188, 1960. [21] MEDICI Users Manual version Y.2006.06 [22] TSUPREM4 Users Manual version Y.2006.06 [23] Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2005. [Online]. Available: http://www.itrs.net/ [24] J. Knoch, J. Appenzeller, A Novel concept for Field Eect Transistors The tunneling Carbon Nanotube FET, in Proc. 63rd DRC., June 2022, 2005, vol. 1, pp. 153158. [25] K. Bhuwalka, J. Schulze, I. Eisele, Scaling the Vertical Tunnel FET with Tunnel Bandgap Modulation and Gate Workfunction Engineering, IEEE Tran. Elec. dev., vol. 52, no. 5, pp 909917, May 2005. [26] K. Bhuwalka, J. Shulze, A simulation approach to optimize electrical parameters of a Vertical Tunnel FET, IEEE Tran. Elec. Dev., vol. 52, no. 7, pp. 15411547, July 2005. [27] K. Boucart, A. Ionescu, Double Gate Tunnel FET with High gate dielectric, IEEE Tran. Elec. Dev., vol. 54, no. 7, pp. 17251733, July 2007. [28] P.F. Wang, T. Nirschl, D. Landsiedel, W. Hansch, Simulation of Esaki Tunnel FET, Sol. State. Elec., vol. 47, no. 7, pp. 11871193, 2003.

BIBLIOGRAPHY

52

[29] ATLAS Users Manual version 5.12.1.R. [30] G. Hurkx, D. Klaassen, and M. Knuvers, A new recombination model for device simulation including tunneling, IEEE Trans. Elec. Dev., vol. 39, no. 2, pp. 331338, Feb. 1992. [31] G. Hock, E. Kohn, C. Rosenblad, H. Von Kanel, H.J. Herzog, and U. Konig, High hole mobility in Si0.17 Ge0.83 channel MOSFET grown by plasma-enhanced chemical vapor deposition, Appl. Phys. Letters, vol. 76, no. 26, pp 39203922, 2000. [32] Tejas Krishnamohan, Ph.D thesis, Stanford University, pp.57-61, June 2006. [33] T. Nirschl, U. Schaper, J. Einfeld, St. Henzler, M. Sterkel, J. Singer, M. Fulde, W. Hansch, G. Georgakos, D. Schmitt-Landsiedel, Impact of Mask Alignment on the Tunneling Field Eect Transistor (TFET), Proc. IEEE International Conf on Microelectronic Test Structures, April 2005.