CISC vs RISC By Armin Gerritsen - Which one is better? RISC vs CISC is a topic quite popular on the Net.

Everytime Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again. But what are CISC and RISC exactly, and is one of them really better? This article tries to explain in simple terms what RISC and CISC are and what the future might bring for the both of them. This article is by no means intended as an article pro-RISC or proCISC. You draw your own conclusions CISC Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures. Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instructionset, which provides programmers with assembly instructions to do a lot with short programs. In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. RISC Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as

used by CISC, and people mostly use compilers which never use complex instructions. Apple for instance uses RISC chips. Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task. An other advantage of RISC is that - in theory - because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce. Finally, it's easier to write powerful optimised compilers, since fewer instructions exist.

RISC vs CISC There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefor the architecture of the future. Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks. Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway. RISC has now existed more than 10 years and hasn't been able to kick CISC out of the market. If we forget about the embedded market and mainly look at the market for PC's, workstations and servers I guess a least 75% of the processors are based on the CISC architecture. Most of them the x86 standard (Intel, AMD, etc.), but

even in the mainframe territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay Is RISC than really not better? The answer isn't quite that simple. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Further more today's CISC chips use many techniques formerly associated with RISC chips. So simply said: RISC and CISC are growing to each other. x86 An important factor is also that the x86 standard, as used by for instance Intel and AMD, is based on CISC architecture. X86 is th standard for home based PC's. Windows 95 and 98 won't run at any other platform. Therefore companies like AMD an Intel will not abandoning the x86 market just overnight even if RISC was more powerful. Changing their chips in such a way that on the outside they stay compatible with the CISC x86 standard, but use a RISC architecture inside is difficult and gives all kinds of overhead which could undo all the possible gains. Nevertheless Intel and AMD are doing this more or less with their current CPU's. Most acceleration mechanisms available to RISC CPUs are now available to the x86 CPU's as well. Since in the x86 the competition is killing, prices are low, even lower than for most RISC CPU's. Although RISC prices are dropping also a, for instance, SUN UltraSPARC is still more expensive than an equal performing PII workstation is.

Equal that is in terms of integer performance. In the floating pointarea RISC still holds the crown. However CISC's 7th generation x86 chips like the K7 will catch up with that. The one exception to this might be the Alpha EV-6. Those machines are overall about twice as fast as the fastest x86 CPU available. However this Alpha chip costs about 20000, not something you're willing to pay for a home PC. Maybe interesting to mention is that it's no coincidence that AMD's K7 is developed in co-operation with Alpha and is for al large part based on the same Alpha EV-6 technology. EPIC The biggest threat for CISC and RISC might not be eachother, but a new technology called EPIC. EPIC stands for Explicitly Parallel Instruction Computing. Like the word parallel already says EPIC can do many instruction executions in parallel to one another. EPIC is a created by Intel and is in a way a combination of both CISC and RISC. This will in theory allow the processing of Windows-based as well as UNIX-based applications by the same CPU. It will not be until 2000 before we can see an EPIC chip. Intel is working on it under code-name Merced. Microsoft is already developing their Win64 standard for it. Like the name says, Merced will be a 64-bit chip. If Intel's EPIC architecture is successful, it might be the biggest thread for RISC. All of the big CPU manufactures but Sun and Motorola are now selling x86-based products, and some are just waiting for Merced to come out (HP, SGI). Because of the x86 market it is not likely that CISC will die soon, but RISC may.

So the future might bring EPIC processors and more CISC processors, while the RISC processors are becoming extinct. Conclusion The difference between RISC and CISC chips is getting smaller and smaller. What counts is how fast a chip can execute the instructions it is given and how well it runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the competition. The future might not bring victory to one of them, but makes both extinct. EPIC might make first RISC obsolete and later CISC too. Written by A.A.Gerritsen for the CPU Site March '99 7 - RISC vs. CISC

Launch this Guide The biggest conceptual battle played out during the history of instruction sets was the battle between RISC and CISC. Needless to say, its a battle that Intel has mostly won, given the dominance of x86. It started when processors became fast enough and memory was cheap, so you could afford to have more, unlike the very early days of x86 when every byte counted. This is when close-to-themetal assembly language started falling out of favour and programmers moved on to easier, higher-level languages. The language called C was the favourite, but brought a new problem to computer science: compiler design. The C code which is simply

a text file written by the programmer has to be converted into machine code, low-level instructions for whatever processor platform the program was running on. One school of thought considered the huge list of x86 instructions well over 100 even at that point good for making machine code programming as easy as possible, but less efficient when it came to producing the best compiled code. As a result, RISC (reduced instruction set computer) processors were born. Unlike the dozens of instructions supported by x86, a RISC processor only has a few basic primitive instructions, but these can be executed at very high speed, typically taking only one or two clock cycles. Its then down to the compiler to use these native instructions and build up the functions of the more complex ones in machine code. However, an x86 PC is now known as CISC - a complex instruction set computer. Its continued to dominate, due to clever design and other, more prosaic factors. For instance, the 486 introduced instruction pipelining, splitting instructions into RISClike pieces for simultaneous decoding and execution. Add to that the fact that Intel has a far larger R&D budget than any other CPU manufacturer, so it can compensate for any architectural deficiencies with better materials, engineering and shrinking fabrication processes. Finally, we come back to the unavoidable fact that x86 compatibility is needed to run the millions of existing PC applications available. RISC never had much of a chance.The most popular example of a RISC architecture is the IBM PowerPC CPUs, but these are harder than ever to find in consumer PCs now that the x86 steamroller has replaced PowerPC in Apple Macs. The RISC philosophy has endured pretty well in areas other than the desktop though. The PlayStation 3, Nintendo Wii and the iPhone (with its ARM processor) are all RISC-based.

Architecture is a way of looking at the fundamental operational structure of the computer. It is the blueprint of the requirements and design implementations for the various parts of a computer focusing largely on the way by which the central processing unit (CPU) performs internally and accesses addresses in memory. The key to a successful computing system is to select and interconnect hardware components that results in that a functional, costeffective performance-driven machine. The topic of computer architecture addresses this. Instruction set architecture; Computer organization and System Design are three underlying aspects which need to be addressed [1]. I will now discuss two CPU design philosophies which represent two controversial architectural philosophies [2]. CISC (Complex Instruction Set Computer) Processor Architecture A 1960s architect who took the CISC (Complex Instruction Set Computer) approach was an architect who could build a computing system that would utilize the smallest amount of assembly code possible [3]. Armed with fresh innovation in a world of growing technological advancement at his disposal, and the Modus operandi of reducing the level of code, a CISC architect would strive to build as much of the "coding" as possible into the computers hardware itself. An "Intelligent" and "logical" processor hardware system which could "understand" high-level instructions would have huge cost-cutting implications by enabling the use of minimal lines of code to achieve maximum computer functionality and complete any computing task. A CISC system would contain a Microprocessor instruction set so that each single instruction can execute several low-level operations such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. For a specific task, a CISC processor would come prepared with a specific instruction,

e.g. ADD. Take a look at a working example to see how powerful and economical this system was: ADD 2:3 First of all, two values are loaded into separate register Then, the operands are added in the exception unit Finally, the sum is stored in the associated register At the very heart of CISC is a set "complex" instruction like ADD. The computer's memory banks are directly operated on [3], thus making the loading or storing functions redundant. ADD is similar to what a programmer in C++ or any other high-level language would code. Takes control over thousands or millions of transistors, CPU etc. One of the primary advantages of this system is that the compiler has to do very little work to translate a highlevel language statement into assembly. Micro program instruction sets can be written to match high-level languages and the compiler does not have to be as complicated. Minimal lines of coding must also have reduced the probability of errors in the code, thus reducing cost and debugging-time. In addition, small code sizes could be stored easily to enable a frugal use of RAM [3]. CISC seemed like such a natural and intuitive system at the time and it didn't even have a name. The term was retroactively coined [4] in contrast to reduced instruction set computer computers of the 1970s (although we also have examples of pre-RISC systems of the 1960s) which eventually brought CISC (Complex Instruction Set Computer) to its knees and forced CISC-philes to defend and debate with their adversaries. RISC (Reduced Instruction Set Computer) Architecture Design The RISC-brigade strive for an instruction set reduced both in size and complexity of addressing modes which they argue enables

easier implementation, greater instruction level parallelism, and more efficient compilers [5]. A RISC architect tries to keep the instruction set as simple as possible [6] so that a job can be executed within one clock cycle. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible [7]. Rather than using an "intelligent" hard-coded CPU hardware system, there is more emphasis on the software. Every slight small hardware job can be managed and customized by the software used. So, to add two integers, LOAD A, 2:3 LOAD B, 5:2 ADD A, B STORE 2:3, A "LOAD" moves data from the memory bank to a register; "ADD" finds the sum of two operands located within the registers; and "STORE" moves data from a register to the memory banks. They support only register-to-register operations and a few simple addressing modes. In using three instructions codes to achieve only one task, larger amounts of RAM would be needed to store the assembly code, and the compiler would need to do more work to convert that code to a lower-level form. However, this is balanced by the more economical use of registers by means of a set of "reduced instructions" which incorporate a reduced amount of transistors; and as already mentioned, by maximizing the number of instructions per program, the number of clock cycles per second is reduced. So, by using a number of small instructions rather than one "large" instruction, the amount of actual work done by the machine is reduced. If there were any advantages in this system, the RISC people certainly had their work cut-out for them at first. RISC chips weren't in wide-circulation until the 1970s. Much of the software available at the time was designed for CISC machines. It would

have been a commercial risk to actually start mass-producing this technology. RISC & CISC Architecture in Today's Computer Systems In the early years, there appeared more of a distinction between the two designs than appears today. Systems designed on the RISC philosophy included IBM's System/360 (1964) which was the first commercially available micro programmed computer architecture latter to become known as CISC architecture. The success of System/360 resulted in CISC architectures dominating computer, and later microprocessor, design for two decades. Other CISC computers included VAX (mid-1970s); PDP-11 (1970s); and the Motorola 68000 series (1970s). CISC was also an influence on the Windows 3.1 (1992) and Windows 95 were designed with CISC processors in mind [3] If pure CISC design is not commonly used in todays computing systems, it may have to do with the following: [8]: Increasing instruction set & chip hardware complexity leads backward-compatibility issues Variable length instructions slow down the overall performance of the machine Many specialized instructions are15 not used frequently CISC instructions typically also set the condition codes as a side effect Whatever the disadvantages in CISC usage, it took at least 10 years for RISC to take commercial hold [3] as Intel was one roadblock to its widespread implementation as Intel (a CISC user) had vast resources to continue implementing the CISC model. Although RISC is often thought of as a more recent development, in fact the first system which could now be considered as RISCbased was the CDC 6600 supercomputer, designed in 1964 [9]. But the first major RISC projects came from IBM, Stanford, and UCBerkeley in the late 70s and early 80s [10]. More modern systems were Apple's Power Macintosh line (1994) Windows NT (1993)

was RISC compatible. Nowadays, CISC and RISC conflict has ended with some factions claiming that RISC has won [2], and have more or less converge. Examples of convergences include [11]: With an increase in processor speeds, CISC chips are now able to execute more than one instruction within a single clock which enables RISC-like pipelining. We can fit many more transistors on a single chip thus providing more space to execute CISC-like commands. Although today, it is proposed that Intel x86 is the only chip which retains pure CISC architecture [10] it is however at least as fast the fastest true RISC single-chip solutions available [12]. How the two are compared depends on whether a qualitative comparison or a quantitative comparison is made [13]. This author concludes that nowadayas, both architectural designs having little difference, nor much significance between themselves. http://knol.google.com/k/david-mccaldin/what-is-the-risc-incomputer/2pr18mcjtayt9/1#CISC_(28)Complex_Instruction_Set_C omputer(29)_Processor_Architecture CISC vs RISC In the early days of the computer industry, high level programming languages were not available and most of the work was done in assembly language. Therefore CPU designers tried to make instructions that would do as much work as possible. The general thinking at that time was that hardware design was easier than compiler design, so large parts of the complexity of the software went into the hardware (and/or microcode). This design philosophy was named Complex Instruction Set Computer (CISC).

With the advent of higher level languages, a new design strategy started to gain more and more popularity: instructions which "do less" may still provide high performances if this simplicity can be utilized to make instructions execute very quickly. The focus on "reduced instructions" led to the resulting machine being called a Reduced Instruction Set Computer (RISC). The goal was to make instructions so simple that they could easily be pipelined, in order to achieve a single clock throughput at high frequencies. Currently, many processors are called RISC because there is a perception tat RISC is faster than CISC. This can be confusing because many of the processors available are identified as being "RISClike", but are, in fact, CISC processors. You must be aware that in some appliocations, CISC processor can execute code faster than RISC processors, or execute applications that a RISC processor cannot. Characteristics of a RISC architecture:

Emphasis on software; Single-clock, reduced instruction only; Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding; Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design; Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations; Typically larger code sizes; Few data types in hardware;

Characteristics of a CISC architecture:

Emphasis on hardware; Includes multi-clock complex instructions; Small code sizes; Complex data types in hardware; some CISCs have byte string instructions, or support complex numbers;

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. im khc bit thc s gia RISC so vi CISC l nguyn tc thc hin mi th trong cc thanh ghi, c v lu d liu vo cc thanh ghi. Do trnh hiu lm nhiu nh nghin cu thch dng thut ng load-store. Qua thi gian, cc k thut thit k c c gi l CISC ( Complex Instruction Set Computer My tnh vi tp lnh phc tp), d rng thut ng ny thng ch c dng vi mc ch so snh.

CISC RISC CPUs were an idea of the 1980's because hardware was getting less expensive, while coding was becoming increasingly more costly. CISC was a term created to mean Complex Instruction Set Computing, giving a name to the existing processor designs that were not RISC. Today, your authors prefer CISC to mean Conventional Instruction Set Computing. RISC Verses CISC The argument between CISC and RISC has reached religious fervor.

CISC = BAD. RISC =GOOD. Don't fall into this trap. It is an outdated thought. The RISC philosophy made a great deal of sense at the time up its inception, in the 80's. At that time, 1MB of RAM carried a cost of about $5,000.00. In 2001, current cost for 1MB of RAM is about $0.50. When RAM was that expensive, copying the micro code, from a ROM to a much faster RAM was too expensive. Today, this is a common technique used to increase the speed of a CISC based computer. The process of copying a ROMs micro code to RAM is known as shadowing. Shadowing greatly improves performance of any CISC based CPU.

Before beginning a deeper review of the popular CPUs, one more thought is in order in the RISC/CSIC debate. Today's CPUs, from any manufacturer is actually a hybrid of the RISC/CSIC philosophy.

RISC From the minds at University of California, Berkeley and Stanford University sprouted the idea that maximizing computer performance could be accomplished by putting most functions in software, except for the teachers who were putting them in hardware would yield a net performance gain. This is the idea behind the Reduced Instruction Set Computer (RISC). The basic design concepts include:
o

Hardwired control. RISC designs eliminate micro code in ROM and put the instruction set directly in hardware. Simple instructions with few addressing modes. Conventional CPU design includes a variety of ways to

address memory, which require the processor to calculate effective addresses on a variety of fronts. Simplifying operations reduces CPU overhead. RISC based CPUs are popular in high-end computers dedicated to resource intensive tasks such as animation. Perhaps the most well known RISC CPU is the SPARC (Scalable Processor Architecture)

D bt k cp no, n v logic ca mt chip RISC bao gi cng cn t transistor hn so vi ca mt chip CISC. iu ny gip ngi thit k c rt nhiu s linh hot, v d h c th: 1. Tng s lng thanh ghi. 2. S dng cc phng php ti u tng mc x l song song bn trong CPU (pipeline, superscalar) 3. Tng kch thc cache 4. Thm cc tnh nng nh I/O, timer v.v 5. Thm cc b x l vector. 6. Tn dng cc dy chuyn cng ngh c, trong khi vi CISC iu ny rt kh khn do kch thc chip ln hn 7. Cung cp nhng chip cho nhng ng dng c yu cu cao v thi gian s dng pin hoc v kch thc chip. Nhng c im thng thy trong 1 chip RISC: 1. nh dng chun m lnh (v d lnh c chiu di c nh, cc bit ca m lnh lun nm v tr c nh trong m lnh) s lm qu trnh gii m lnh n gin hn. 2. Cc thanh ghi ng nht, do chng c th c s dng thay th nhau trong mi tnh hung (tuy nhin cc thanh ghi