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Bangladesh University of Engineering and Technology Department of Electrical and Electronics Engineering Central Quiz EEE 304: Digital Electronics Laboratory Total Marks: 40 Student No.: ____________________________________ Time: 40 minutes Date:

(The marks are written on the right side of each question)

Question 1: State whether the following statements are True or False. Give the answers by placing T or F in the table given below 5 a b c d e f g h i j

A Full-adder can be used as a NOT gate. The Vcc pin of an AND gate IC is located at the bottom left hand side. An IC containing T flip-flops was used when implementing the frequency division circuit. In a 4 bit signed binary number system (using 2s complement), 8 is represented by 1000. If you have a 4 bit counter IC, Clock signal, Vcc and Ground, you need no other ICs or logic gates to create 4 output pins which will count only even numbers with counting rate equal to half of clock frequency. f. If two clocks with same frequency and phase are used as inputs to a XOR gate, the output of the gate will be always zero. g. J-K flip-flops were used to implement the serial-in serial-out shift resistor. h. In a 4 bit adder/subtractor circuit, the carry-in pin is used as the selector pin for addition/subtraction. i. Flip-flops and latches are both synchronous. j. An 8 to 1 MUX can be used to implement any Boolean logical function of 3 variables without using any logic gates or other ICs.

a. b. c. d. e.

Question 2: Multiple Choice Questions (put a mark beside the correct answer(s))

i) Two main HDLs in use today are VHDL and Verilog, Whats true about thema) Both allow us to specify logic designs as textual descriptions b) Both look like a software procedure but are describing Hardware c) Both a & b

d) None of above

ii) Which of the following characteristics all bi-stable binary storage elements must havea) The element must have two stable states b) Inputs must exist to modify or hold FF state c) The present element state must be detectable d) All of above e) a & c

iii) Consider the following circuit

What kind of purpose it will serve? a) 1:2 Decoder, Active High Enable b) 1:2 Decoder, Active Low Enable c) Both d) None

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iv) Which one of the following will be your choice for sequential network a) Simple Circuits with Feedback b) R-S Latch c) J-K Flipflop d) All of above e) Both b & c

v) Which one of the following will be the best choice for storage registers? a) SR b) JK c) D d) T vi) Which one of the following will be the best choice for implementing counters? a) SR b) JK c) D d) T

Question 3: A Verilog code segment is given below. Explain the output of this code segment. What mathematical operation will be performed by this code? 4 module labquiz(A,B,C,D); input [3:0] A,B; output [3:0] C,D; reg [3:0] C,D; integer k; always@(A or B) begin C=0; D=A; for(k=1;k<=15;k=k+1) begin if(D<B) begin D=D; C=C; end else begin D=D-B; C=C+1; end end end endmodule (Write down your answer here)

Question 4: Consider the following circuit

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If the period of repeating waveform is Tp and gate delay of each inverter is Td, draw the waveforms at each node (A, B, C, D and E ) for the full period Tp. Also state the relationship between Tp and Td.

Question 5: A 4-1 multiplexer is shown in the figure below. Let a single clock signal, only the IC(s) you used during your lab-works and +5v and 0v supplies are available to you. You have to make necessary connections with the multiplexer to obtain the output waveform shown below. 4

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Question 6: In the following figure, the internal structure of an FPGA is shown. Show how you can implement

the following function in this FPGA block. At each wire junction you may place cross (x) to show the necessary active connection. Also write the required contents of all the lookup tables and indicate input/output pins. Answer must be given in this figure.

LUT I1 Q

LUT

I1

I2

I2 I1=MSB, I2=LSB

I1=MSB, I2=LSB I/O Pad Interconnection Wire

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Question 7: Design a counter so that it can count only the numbers of the form

, where n is the sequence number. If n=0,1,2,3,4,5 then the counter output will show 0,1,3,7,15,31 Design for only 4 bit, i.e. your counter will count in this sequence 0,1,3,7,15,0,1,3,7,15, upon each clock pulse. 4

Question 8: The flip-flops in the following figure are negative edge triggered J-K flip- flops. Let Q2, Q1, Q0 = 0, 0, 0 initially. Plot the clock, Q2, Q1 and Q0 until the outputs begin to repeat. Analyze the outputs (Q2, Q1 and Q0) and mention the purpose that this circuit serves. 4

Question 9: A counter IC is shown in the figure below. Consider that the time period of the available clock signal is 1 second. Connect necessary IC(s) with the counter IC so that it starts counting 3 seconds after receiving the first clock signal. Suppose only the IC(s) you used during your lab-works are available to you. The design can be easily implemented using those IC(s). 4

Question 10: Write a Verilog code to design a circuit which will have a clock pulse input and a 4 bit output and

will show each successive Fibonacci number upon each positive clock edge. The output numbers upon successive clock pulses will be 1,1,2,3,5,8,13,1,1,2,3,5 4