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N-channel 650 V@Tjmax, 0.9 , 8 A MDmesh Power MOSFET TO-220, TO-220FP, D2PAK, DPAK, IPAK
Features
Type STD5NM60 STD5NM60-1 STB8NM60 STP8NM60 STP8NM60FP
ID 5A 5A 5A 8A 8 A(1)
Pw
3
96 W 96 W 100 W 100 W 30 W
DPAK
3 1
TO-220FP DPAK
3
3 1 2
100% avalanche tested HIgh dv/dt and avalanche capabilities Low input capacitance and gate charge Low gate input resistance Figure 1. TO-220
2 1
IPAK
Application
Switching applications
Description
The MDmesh is a new revolutionary Power MOSFET technology that associates the multiple drain process with the companys PowerMESH horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the companys proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competitions products. Table 1. Device summary
Order codes STD5NM60-1 STD5NM60T4 STB8NM60T4 STP8NM60 STP8NM60FP Marking D5NM60 D5NM60 B8NM60 P8NM60 P8NM60FP Package IPAK DPAK DPAK TO-220 TO-220FP Packaging Tube Tape & reel Tape & reel Tube Tube
October 2008
Rev 17
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www.st.com 18
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Value Symbol Parameter TO-220 DPAK VGS ID ID IDM(2) PTOT dv/dt(3) VISO TJ Tstg Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C Derating factor Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s;TC=25 C) Operating junction temperature Storage temperature -8 5 32 100 0.8 TO-220FP 30 8(1) 5 (1) 32 (1) 30 0.24 15 2500 -5 3.1 (1) 20 (1) 96 0.0.4 IPAK DPAK V A A A W W/C V/ns V Unit
-55 to 150
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD 5 A, di/dt 400 A/s, VDD = 80%V(BR)DSS
Table 2.
Thermal resistance
Value
Symbol
Parameter
TO-220 DPAK
Rthj-case Rthj-a Tl
Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose
1.25
Table 3.
Symbol IAS EAS
Avalanche data
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj=25 C, ID=IAS, VDD=50 V) Value 2.5 200 Unit A mJ
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Electrical characteristics
Electrical characteristics
(TCASE = 25 C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = max rating, VDS = max rating @125 C VGS = 20 V VDS = VGS, ID = 250 A VGS= 10 V, ID= 2.5 A 3 4 0.9 Min. 600 1 10
100
Typ.
Max.
Unit V A A nA V
5 1
Table 5.
Symbol gfs Ciss Coss Crss
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS = ID(on) x RDS(on)max, ID = 2.5 A VDS = 25 V, f=1 MHz, VGS=0 Min. Typ. 2.4 400 100 10 50 13 5 6 18 Max. Unit S pF pF pF pF nC nC nC
Coss eq(1). Equivalent output capacitance Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge
VGS=0, VDS =0 to 480 V VDD= 400 V, ID = 5 A VGS =10 V (see Figure 12)
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf tr(Voff) tf tc
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Off-voltage rise time Fall time Cross-over time Test conditions VDD= 300 V, ID= 2.5 A, RG= 4.7 , VGS=10 V (see Figure 17) Min. Typ. 14 10 23 10 7 10 17 Max. Unit ns ns ns ns ns ns ns
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM trr Qrr IRRM
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
2.1
Figure 2.
Figure 4.
Figure 5.
Figure 6.
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Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations
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STP8NM60, STD5NM60, STB8NM60 Figure 14. Normalized gate threshold voltage vs temperature
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Test circuit
Test circuit
Figure 18. Gate charge test circuit
Figure 19. Test circuit for inductive load Figure 20. Unclamped inductive load test switching and diode recovery times circuit
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mm Dim Min A b b1 c D D1 E e e1 F H1 J1 L L1 L20 L30 P Q 4.40 0.61 1.14 0.48 15.25 1.27 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 Typ Max 4.60 0.88 1.70 0.70 15.75 Min 0.173 0.024 0.044 0.019 0.6
inch Typ Max 0.181 0.034 0.066 0.027 0.62 0.050 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 0.151 0.116
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DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7
L3 L6 L7
F1 F
G1 H
F2
L2 L5
E
1 2 3
L4
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mm Dim Min A A1 b b2 c c2 D D1 E E1 e e1 H J1 L L1 L2 R V2 4.40 0.03 0.70 1.14 0.45 1.23 8.95 7.50 10 8.50 2.54 4.88 15 2.49 2.29 1.27 1.30 0.4 0 8 0 5.28 15.85 2.69 2.79 1.40 1.75 0.192 0.590 0.099 0.090 0.05 0.051 Typ Max 4.60 0.23 0.93 1.70 0.60 1.36 9.35 10.40 Min 0.173 0.001 0.027 0.045 0.017 0.048 0.352 0.295 0.394 0.334
inch Typ Max 0.181 0.009 0.037 0.067 0.024 0.053 0.368 0.409 0.1 0.208 0.624 0.106 0.110 0.055 0.069 0.016 8
0079457_M
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0068771_H
13/18
0068772_G
14/18
* on sales type
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DPAK FOOTPRINT
mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40
15.7 16.3
inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574
0.618 0.641
MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1
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Revision history
Revision history
Table 8.
Date 14-Apr-2004 11-Apr-2005 21-Feb-2006 08-Sep-2006 14-Sep-2006 09-Jul-2007 01-Oct-2008
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