ACPL-P346/W346

Isolated Power MOSFET Gate Driver Evaluation Board

User's Manual
Quick Start
Visual inspection is needed to ensure that the evaluation board is received in good condition. All part references are designated with suffix a and b to indicate the lower and the upper inverter arms, respectively. If part references are made without suffixes, then they are valid for both upper and lower inverter arms (except R6, which is shared). Figure 1 shows the default connections of the evaluation board: 1. Q1 and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q1 (for TO-220 package) or Q2 (for TO247 package) or connected to the driver board through short wire connections from the holes provided at Q1 or Q2. 2. D4 and R7 are not mounted (on solder side). A 12 V Zener diode footprint at D4 is provided to allow for a single DC power supply of 15 V ~25 V to be applied across VCC2 and VEE if needed. A virtual ground VE (at Source pin of Q1 or Q2) can then be generated and it acts as the reference point at the source pin of each power MOSFET. VCC2 will then stay at 12 V above the virtual ground VE. R7 is needed to generate the bias current across D4. 3. S2 and S3 jumpers are shorted by default to connect VE to VEE, assuming that a negative supply is not needed. Note: If a negative supply is needed, then S2 and S3 jumpers must be removed. 4. Bootstrap diode D3b and resistor R6 are connected by default. These two components are provided to help generate VCC2b supply through bootstrapping assuming that VCC2a supply is available. Note: Bootstrapping supply works only when Q1 or Q2 are mounted in a half-bridge configuration and turned on and off through proper PWM driving signals. 5. S1 is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when VCC1 is supplied. This short can be removed if IN- cannot be grounded. 6. Upper and lower arms of the inverter will have common VCC1 (and GND1), a provision is made to allow VCC1 to be connected by solder between upper and lower inverter PCB portions (and GND1 on the solder side). 7. Provisions are also made to allow VCC2 (and VEE) to be generated from VCC1 through a DC/DC converter at IC2. When this DC/DC converter is used, S2, S3 (and R6) should be disconnected.

VCC1a and VCC1b (shorted) GNDa and GNDb on solder side (also shorted)

VCC1b VCC1a

S1 (shorted)

S2 (shorted)

S3 on solder side (also shorted)

Figure 1. Actual ACPL-P346/W346 evaluation board showing default connections

R6 mounted (shorted)

Once inspection is done, the evaluation board can be powered up in five simple steps. Figure 2 shows you how to test the top or the bottom half-bridge inverter arms in simulation mode without the need for an actual power MOSFET.

Testing both arms of the half-bridge inverter driver (without a power MOSFET)
1. Solder a 10 nF capacitor across the gate and emitter terminals of Q1 or Q2. This is to simulate actual gate capacitance of a power MOSFET. 2. Connect a +5 V DC supply (DC supply 1) across the +5V and GND terminals of CON1. 3. Connect another DC supply (DC Supply 2 with voltage range from 12 V ~ 20 V) across VCC2 (pin 7 of IC2) and VEE (pin 5 of IC2) terminals of IC2a, respectively. This can be non-isolated for testing purposes. 4. Connect drive signals: a. A 10 kHz 5 V DC pulse (at slightly < 50% duty) from a dual-output signal generator across IN1+ and IN1- pins of CON1a to simulate microcontroller output to drive the lower arm of the half-bridge Inverter. b. Another 10 kHz 5V DC pulse (at 180 out of phase to the signal in 4a) from the dual-output signal generator across IN2+ and IN2- pins of CON1b to simulate microcontroller output to drive the upper arm of the half-bridge inverter. 5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points: a. LED signal at the IN1+ pin with reference to (w.r.t.) GND. b. LED signal at the IN2+ pin w.r.t. GND.
Note: The VCC2b supply of voltage close to V CC2a should then be successfully generated through the built-in bootstrap components D3b and R6.

c. VGa representing the output voltage of ACPL-P346/W346 (IC1a) at the gate pin of Q1a (or Q2a) w.r.t. VEa. d. VGb (through an isolated probe) representing the output voltage of ACPL-P346/W346 (IC1b) at the gate pin of Q1b (or Q2b) w.r.t. VEB.
In2In2+ 4b 5b Signal Input

5d 10nF + VCC2b 5c 10nF 2 3 + 12~20 V DC Supply 2

1 VEb

4a 5a

Signal Input

In1In1+

1 VEa

Figure 2. Simple Simulation Test Setup of Evaluation Board

Gnd +5V

DC Supply 1

Schematics
Figure 3 shows the schematics of the evaluation board:
CON1b
LEDb+ R1b 249R 1

IC1b ACPL-P346

VCC2b 6 C1b 0.1F D4b R7b NM TP1b R4b 4R7 1W NM D G SS32 SMBJ11CA D1b S2b D2b

NM R3b

R5b NM R2b 130R S1b VCC1b 1

TO220/TO247 S Q1b/Q2b

NM

LEDb-

VEEb VCC2b S3b C2b 10 F Ta C3b 10 F Ta VEEb BYM26F D3b

VEb

IC2b

7 TP2b

GNDb

NM

6 TP3b 5 TP4b

4R7 1W D4a R7a NM NM

R6

CON1a
LEDa+

R1a 249R

IC1a ACPL-P346

VCC2a 6 C1a 0.1 F

NM R3a

TP1a R5a NM

R4a 4R7 1W

D G SS32 SMBJ11CA D1a D2a VEa TO220/TO247 S Q1a/Q2a

NM

LEDa-

R2a 130R S1a

4 VEEa

S2a

VCC1a GNDa

1 2

IC2a

7 TP2a 6 TP3a 5 TP4a

VCC2a S3a C2a 10F Ta C3a 10F Ta VEEa

BYM26F

D3a

R05P212D/R8

Figure 3. Schematics of ACPL-P346/W346 evaluation board

Practical connections of the evaluation board using a power MOSFET for an actual inverter test
1. Solder actual power MOSFETs at Q1 (or Q2) for the top and bottom arms of the half-bridge inverter isolated drivers. 2. Connect a +5V DC isolated supply1 across +5V and GND terminals of CON1 for both arms of the isolated drivers. 3. Connect another isolated DC supply2 (voltage range from 12 V ~ 20 V) across VCC2a and VEEa at pin 7 and pin 5 of IC2a respectively for the bottom arm. 4. Connect the signal output (meant to drive the bottom arm of the half-bridge inverter) from the microcontroller to Signal Input 1 across pin IN1+ and IN1- of CON1a of the bottom inverter arm isolated driver. 5. Connect the signal output (meant to drive the top arm of the half-bridge inverter) from the microcontroller to Signal Input 2 across pin IN2+ and IN2- of CON1b of the top inverter arm isolated driver. Note: Signal Input 2 should be 180 out of phase w.r.t. Signal Input 1. Check that VCC2b (voltage close to VCC2a) is generated through the bootstrap components D3b and R6. 6. Use a multi-channel digital oscilloscope to capture the waveforms at the following points: a. LED signal at IN1+ pin w.r.t. GND for the bottom arm. b. LED signal at IN2+ pin w.r.t. GND for the top arm. c. Vga for the gate driving voltage of Q1a (or Q2a) w.r.t. VEa of the bottom inverter arm (differential probe needed). d. Vgb for the gate driving voltage of Q1b (or Q2b) w.r.t. VEb of the top inverter arm (differential probe needed). 7. Connect a power cable from the output pin (marked Load) to the inverter load. 8. Connect the high voltage cables from the top arm power MOSFET drain pin to HVDC+ and from the bottom arm power MOSFET source pin to HVDC-, respectively, as shown. (Note: It is recommended that you enable the currentlimiting function of the HV power source supplying the high voltage DC bus voltage during this test to protect the inverter and its driver circuitries).
8 HVDC+ 6d 5 IN2+ 6b Signal Input 2 IN21 Power MOSFET mounted

Microcontroller

12~20V

+
6c 1 Power MOSFET mounted 3

7 Load

IN1+ 6a Signal Input 1 IN14 DC Supply1

2 GND +5V

12~20 V DC Supply2

HVDC 8

Figure 4. Connection of evaluation board in actual applications

Application Circuit Description

The ACPL-P346/ACPL-W346 is an isolated gate driver that provides 2.5 A output current. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving of MOSFET with ratings up to 1000 V/100 W. It is also designed to drive different sizes of buffer stage that will make the class of power MOSFET scalable. ACPL-P346 (and ACPL-W346) provides a single isolation solution suitable for both low and high power ratings of motor control and inverter applications. Each of the ACPL-P346/ACPL-W346 evaluation boards, as shown in Figure 5, accommodates two ACPL-P346/ACPL-W346 ICs. Therefore, each board is enough to drive the top and the bottom arms of the half-bridge inverter. It allows the designer to easily test the performance of a gate driver in an actual application under real-life operating conditions. Operation of the evaluation board requires merely the inclusion of a common 5 V DC isolated Supply1 on the input side and an isolated DC Supply2 (range from 12 V ~ 20 V) for the bottom arm of the inverter power MOSFET, while the DC supply needed for the top arm is easily generated through bootstrapping included in the evaluation board. Note: As can be seen on the board, the isolation circuitry (at the far left) is easily contained within a small area while maintaining adequate spacing for good voltage isolation and easy assembly.

Figure 5. Top and bottom views of ACPL-P346/W346 evaluation board 5

Using the Board

It is easy to prepare the evaluation board for use. You just need to solder cables for DC supplies, have proper cables for HVDC+/HVDC- high voltage bus, and load connections. The evaluation board has a default connection as shown in Table 1 when it is shipped to the customer. We offer several power supply schemes from which you can choose.

Power Supply Schemes

The evaluation board is built with DC supply flexibility in mind; choose a power supply scheme from the seven available. Table 1 shows all the possible power supply schemes that work for the evaluation board. A description of each scheme is given; you are encouraged to explore each scheme and decide which one works best for your needs: 1. Scheme 1 is the simplest and possibly the cheapest scheme. A +5 V isolated DC supply is supplied externally to power the low voltage Vcc1 circuit. Another external supply (+12 V~20 V for Vcc2a) is needed for the gate driver driving the power MOSFET at the bottom inverter arm. Vcc2b supply is obtained from Vcc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative supply of Vee is allowed, and the Signal Input 2 is at 180 out of phase to Signal Input 1. All S2 jumpers are shorted to connect Vee to Ve so that there are no negative supplies. S3 jumpers are shorted by default but this has no effect on actual operation of the board. Contact Avago Technologies if bootstrapping operation works are required. 2. Scheme 2 is similar to Scheme 1: it has Vcc1 and Vcc2a supplies. However, as the power MOSFET used gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nC). A third external supply (+12 V~ 20 V for Vcc2b) will be needed. 3. Scheme 3 is similar to Scheme 2 in that it uses three external supplies at Vcc1, Vcc2a and Vcc2b. Scheme 3, however, has the advantage of getting negative supplies for Vee (or Veea and Veeb) by introducing a 12 V Zener diode at D4 and R7 of around 1 k to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be open while the external supplies (+15 V ~ 24 V) on the high voltage driver side are to be connected across Vcc2 and Vee pins only, not the Ve pin. As the external supply changes from +15 V to +24 V, Vcc2 will stay at +12V, but Vee changes from -3 V to -12 V, all w.r.t. virtual ground at Ve. 4. Scheme 4 is another simple scheme; an alternative to Scheme 1. Here, only one external supply for Vcc1 is needed. Vcc2a is obtained by a lower power DC/DC converter at IC2a, with Vcc1 as Vin and +12 V output at Vcc2a w.r.t. Vea. Vcc2b supply is obtained from Vcc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative supply of Vee is allowed, and the Signal Input 2 should be 180 out of phase to Signal input 1. S2 is shorted to connect Vee to Ve so that there is no negative supply. S3 jumpers are shorted by default but this has no effect on actual operation of the board. 5. Scheme 5 is similar to Scheme 4: it has Vcc1 and a DC/DC converter for Vcc2a. However, as the power MOSFET used gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nC). A second DC/DC converter at IC2b with Vcc1 as Vin and +12 V output at Vcc2b w.r.t .Veb. All S2 jumpers are shorted to connect Vee to Ve so that there are no negative supplies. S3 jumpers are shorted by default but this has no effect on actual operation of the board. 6. Scheme 6 is similar to Scheme 5 with the use of Vcc1 and two DC/DC converters. Each DC/DC converter, however, has dual outputs set at 12 V to allow for the availability of negative Vee (at Veea and Veeb). Therefore, all S2 jumpers must be open, while all S3 jumpers must be shorted. 7. Use Scheme 7 if dual-output 12 V DC/DC converters are not available or dual-output 9 V DC/DC converters are preferred. 12 V Vcc2 can still be obtained using 9 V DC/DC converters by introducing a 12V Zener diode at D4 and R7 of around 1k to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be open. As the total voltage across Vcc2 w.r.t. Vee stays at 18V (=9V+9V), Vcc2 of 12 V will be obtained through the 12 V D4 Zener diode, and -6V at Vee, all w.r.t. virtual ground at Ve.

Table 1. Power Supply Schemes

Vcc1
1 +5 V External +5 V External +5 V External

Vcc2a
+12V~20V External +12V~20V External

Veea
0V

S2a
s/c

S3a
s/c

D4a/ R7a
NM

Vcc2b
Bootstrapped from Vcc2a (+12V~20V) +12V~20V External

Veeb
0V

S2b
s/c

S3b
s/c

D4b/ R7b Remarks

NM Default (simplest) - Two external supplies needed for Vcc1 and Vcc2a Higher Power - Three external supplies needed for Vcc1, Vcc2a and Vcc2b

0V

s/c

s/c

NM

0V

s/c

s/c

NM

+15V~24V External
12V -3V~-12V 0V

open open

12V/ 1k

+15V~24V External
12V -3V~-12V 0V

open open 12V/1k Vee available - Three external supplies needed for Vcc1, Vcc2a and Vcc2b - Virtual gnds Vea and Veb generated through D4 and R7 s/c s/c NM Cheap - One single output DC/DC converter for Vcc2a - Only one external supply is needed (Vcc1) Higher Power - Two single output DC/DC converters for Vcc2a and Vcc2b - Only one external supply is needed (Vcc1) Vee available - Two dual output DC/DC converters for Vcc2a,Vcc2b, Veea and Veeb - Only one external supply is needed (Vcc1)

+5 V DC/DC External (=Vcc1/+12V)

s/c

s/c

NM

Bootstrapped from Vcc2a (+12V)

+5 V DC/DC External (=Vcc1/+12V)

0V

s/c

s/c

NM

DC/DC (=Vcc1/+12V)

0V

s/c

s/c

NM

+5 V External

DC/DC (=Vcc1/12V) open

+12V -12V

s/c

NM

DC/DC (=Vcc1/12V)
+12V -12V

open

s/c

NM

+5 V External

DC/DC (=Vcc1/9V)

open open

12V/ 1k

DC/DC (=Vcc1/9V)

+12V

-6V

+12V

-6V

open open 12V/1k Vee available - Dual output DC/DC converters for Vcc2a and Vcc2b - only 1 external supply is needed (Vcc1) - Virtual gnds Vea and Veb generated through D4 and R7

Note: As TVS D2 voltage is selected at a breakdown voltage of 12.2 V, it is not advised to set both Vcc2 and Vee voltage at a voltage beyond 12 V. To use a voltage higher than 12 V, please replace D2 with a bigger clamping voltage.

Output Measurement
A sample of input LED and various output waveforms are captured and shown in Figure 6. The default setup connection is adopted, except with Q1a and Q1b power MOSFETs are mounted. The power MOSFETs used have a gate capacitance equivalent to 10 nF.

Figure 6. Input LED signal and Power MOSFET Gate Voltage Waveforms

Figure 6 also shows that, once a bootstrap supply is adopted, the amplitude of the output voltage at the top inverter arm will be slightly smaller than that of the bottom inverter arm, at 180 out of phase. (IN1+ is set at 49% duty ratio, while IN2+ (not shown) is also set with 49% duty ratio, plus a turn-on delay of 100 ns with respect to IN1+). Figure 7 shows the turn-off signal of IN1+, the turn-off signal at gate of Q1a, and the turn-on signal at gate of Q1b.

Figure 7. Turn-off and Turn-on Gate waveforms of Q1a and Q1b

Figure 8 shows the turn-on signal of IN1+, the turn-on signal at gate of Q1a and the turn-off signal at gate of Q1b.

Figure 8. Turn-on and Turn-off Gate waveforms of Q1a and Q1b

As can be seen from Figure 7 and Figure 8, the turn-off speed of the power MOSFET will be slow, due to the capacitive effects of D2 and the gate capacitance of Q1. To improve the turn-off speed, the board is provided with a diode resistor pair footprints at D1 and R5 (not mounted NM) to increase the gate current during turn-off. Another way to further improve the turn-on and turn-off speed is by reducing the gate resistance of R4, but make sure the gate drive current is not more than 2.5 A.

For product information and a complete list of distributors, please go to our web site:

www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2013 Avago Technologies. All rights reserved. AV02-4051EN - May 2, 2013