Control of BLDC Motor Using dsPIC30F2010 Final Year Project

CONTROL OF BLDC MOTOR USING dsPIC30F2010
Chapter 1
INTRODUCTION
Recent developments in power electronics, fast digital signal processors (DSPs) and modern control technologies have significantly influenced the wide spread use of permanent magnet brushless (BLDC) motor [3] drives in order to meet the competitive worldwide market demands of manufactured goods, devices, products and processors. Large, medium, small as well as micro BLDC motors are extensively sought for applications in all sorts of motion control [5] apparatus and systems. The availability of smart power electronics devices and their optimal topologies has accelerated unprecedented growth of cost effective and reliable inverter and converter systems. Software controlled online implementation of sophisticated robust controllers has advanced the art of digital control of BLDC motor drives.
In electric traction, like in other applications, a wide range in speed and torque control for the electric motor is desired. The DC machine fulfils these requirements but these machines needs periodic maintenance. The AC machines like induction motors and brushless DC [1] motor does not have brushes, and their rotors are robust because commutator and or rings do not exist. That means very low maintenance. This also increases the power to weight ratio and efficiency. For induction motors flux control has been developed, which offers a high dynamic performance for electric traction application however this control type is complex and sophisticated.
The development of BLDC has permitted an important simplification in the hardware for electric traction control. The term Brushless DC motor [1] is used to identify the combination of AC machine, solid state inverter and rotor position sensor that results in a drive system having a linear torque speed characteristic as in an conventional DC machine High efficiency due to reduced losses, low maintenance and low rotor inertia of the BLDC motor have increased the demand of BLDC motors in high power servo and robotic applications.
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The invention of modern solid state devices like MOSFET, IGBT and high energy have widely enhanced the applications of BLDC motors in variable speed drives. In this work, a digital controller is developed for this drive which uses minimum number of components employing a recently introduced DSP (dsPIC0F2010) by Microchip for power electronics applications. First the control scheme of the drive is analysed and its simulated results are validated with test results obtained from developed digital controller.
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Chapter 2
BRUSHLESS DC MOTOR FUNDAMENTALS

2.1 Introduction
Brushless Direct Current (BLDC) motors are one of the motor types rapidly gaining popularity. BLDC motors are used in industries such as Appliances, Automotive, Aerospace, Consumer, Medical, Industrial Automation Equipment and Instrumentation.
As the name implies, BLDC motors do not use brushes for commutation; instead, they are electronically commutated. BLDC motors have many advantages over brushed DC motors and induction motors. A few of these are:
Better speed versus torque characteristics High dynamic response High efficiency Long operating life Noiseless operation Higher speed ranges
In addition, the ratio of torque delivered to the size of the motor is higher, making it useful in applications where space and weight are critical factors. In this application note, we will discuss in detail the construction, working principle, characteristics and typical applications of BLDC motors.
2.2 Construction and Operating Principle

BLDC motors are a type of synchronous motor. This means the magnetic field generated by the stator and the magnetic field generated by the rotor rotates at the same frequency. BLDC motors do not experience the slip that is normally seen in induction motors.
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BLDC motors come in single-phase, 2-phase and 3-phase configurations. Corresponding to its type, the stator has the same number of windings. Out of these, 3-phase motors are the most popular and widely used. This application note focuses on 3-phase motors
2.2.1 Stator
The stator of a BLDC motor consists of stacked steel laminations with windings placed in the slots that are axially cut along the inner periphery. Traditionally, the stator resembles that of an induction motor; however, the windings are distributed in a different manner. Most BLDC motors have three stator windings connected in star fashion. Each of these windings is constructed with numerous coils interconnected to form a winding. One or more coils are placed in the slots and they are interconnected to make a winding. Each of these windings is distributed over the stator periphery to form an even numbers of poles.
FIGURE 1: STATOR OF A TYPICAL BLDC MOTOR
There are two types of stator windings variants: Trapezoidal motors Sinusoidal motors
This differentiation is made on the basis of the interconnection of coils in the stator windings to give the different types of back Electromotive Force (EMF). As their names
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indicate, the trapezoidal motor gives a back EMF in trapezoidal fashion and the sinusoidal motors back EMF is sinusoidal, as shown in Figure 1 and Figure 2. In addition to the back EMF, the phase current also has trapezoidal and sinusoidal variations in the respective types of motor. This makes the torque output by a sinusoidal motor smoother than that of a trapezoidal motor. However, this comes with an extra cost, as the sinusoidal motors take extra winding interconnections because of the coils distribution on the stator periphery, thereby increasing the copper intake by the stator windings. Depending upon the control power supply capability, the motor with the correct voltage rating of the stator can be chosen. Forty-eight volts, or less voltage rated motors are used in automotive, robotics, small arm movements and so on. Motors with 100 volts, or higher ratings, are used in appliances, automation and in industrial applications.
TRAPEZOIDAL BACK EMF
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SINUSOIDAL BACK EMF
2.2.2 Rotor
FIGURE 2: ROTOR OF A TYPICAL BLDC MOTOR
The rotor is made of permanent magnet and can vary from two to eight pole pairs with alternate North (N) and South (S) poles. Based on the required magnetic field density in the rotor, the proper magnetic material is chosen to make the rotor. Ferrite magnets are traditionally used to make permanent magnets. As the technology advances, rare earth alloy magnets are gaining popularity. The ferrite magnets are less expensive but they
have the disadvantage of low flux density for a given volume. In contrast, the alloy material has high magnetic density per volume and enables the rotor to compress further for the same torque. Also, these alloy magnets improve the size-to-weight ratio and give higher torque for the same size motor using ferrite magnets. Neodymium (Nd), Samarium Cobalt (SmCo) and the alloy of Neodymium, Ferrite and Boron (NdFeB) are some examples of rare earth alloy magnets. Continuous research is going on to improve the flux density to compress the rotor further. Figure below shows cross sections of different arrangements of magnets in a rotor.
FIGURE [3] ROTOR VARIANTS
2.3 Hall Sensors

Unlike a brushed DC motor, the commutation of a BLDC motor is controlled electronically. To rotate the BLDC motor, the stator windings should be energized in a sequence. It is important to know the rotor position in order to understand which winding will be energized following the energizing sequence. Rotor position is sensed using Hall Effect sensors embedded into the stator.
Most BLDC motors have three Hall sensors embedded into the stator on the non-driving end of the motor. Whenever the rotor magnetic poles pass near the Hall sensors, they give a high or low signal, indicating the N or S pole is passing near the sensors. Based on the combination of these three Hall sensor signals, the exact sequence of commutation can be determined.
FIGURE 4: HALL SENSORS
Above figure shows a transverse section of a BLDC motor with a rotor that has alternate N and S permanent magnets. Hall sensors are embedded into the stationary part of the motor. Embedding the Hall sensors into the stator is a complex process because any misalignment in these Hall sensors, with respect to the rotor magnets, will generate an error in determination of the rotor position. To simplify the process of mtounting the Hall sensors onto the stator, some motors may have the Hall sensor magnets on the rotor, in addition to the main rotor magnets. These are a scaled down replica version of the rotor. Therefore, whenever the rotor rotates, the Hall sensor magnets give the same effect as the main magnets. The Hall sensors are normally mounted on a PC board and fixed to the enclosure cap on the non-driving end. This enables users to adjust the complete assembly of Hall sensors, to align with the rotor magnets, in order to achieve the best performance.
Based on the physical position of the Hall sensors, there are two versions of output. The Hall sensors may be at 60 or 120 phase shift to each other. Based on this, the motor manufacturer defines the commutation sequence, which should be followed when controlling the motor.
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2.4 Theory of Operation

Each commutation sequence has one of the windings energized to positive power (current enters into the winding), the second winding is negative (current exits the winding) and the third is in a non-energized condition. Torque is produced because of the interaction between the magnetic field generated by the stator coils and the permanent magnets. Ideally, the peak torque occurs when these two fields are at 90 to each other and falls off as the fields move together. In order to keep the motor running, the magnetic field produced by the windings should shift position, as the rotor moves to catch up with the stator field.
2.4.1 Torque/Speed Characteristics

Figure shows an example of torque/speed characteristics. There are two torque parameters used to define a BLDC motor, peak torque (TP) and rated torque (TR). During continuous operations, the motor can be loaded up to the rated torque. As discussed earlier, in a BLDC motor, the torque remains constant for a speed range up to the rated speed. The motor can be run up to the maximum speed, which can be up to 150% of the rated speed, but the torque starts dropping.
Applications that have frequent starts and stops and frequent reversals of rotation with load on the motor, demand more torque than the rated torque. This requirement comes for a brief period, especially when the motor starts from a standstill and during acceleration. During this period, extra torque is required to overcome the inertia of the load and the rotor itself. The motor can deliver a higher torque, maximum up to peak torque, as long as it follows the speed torque curve.
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FIGURE 5: TYPICAL TORQUE SPEED CHARACTERISTICS OF BLDC MOTOR
2.4.2 Commutation Sequence
FIGURE 6: AN EXAMPLE OF HALL SENSOR SIGNALS WITH RESPECT TO BACK EMF
Every 60 electrical degrees of rotation, one of the Hall sensors changes the state. Given this, it takes six steps to complete an electrical cycle. In synchronous, with every 60 electrical degrees, the phase current switching should be updated. However, one electrical cycle may not correspond to a complete mechanical revolution of the rotor. The number of electrical cycles to be repeated to complete a mechanical rotation is
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determined by the rotor pole pairs. For each rotor pole pairs, one electrical cycle is completed. So, the number of electrical cycles/rotations equals the rotor pole pairs.
FIGURE 7: TYPICAL COMMUATION CIRCUIT
Table 3 and Table 4 show the sequence in which these power switches should be switched based on the Hall sensor inputs, A, B and C. Table 3 is for clockwise rotation of the motor and Table 4 is for counter clockwise motor rotation. This is an example of Hall sensor signals having a 60 degree phase shift with respect to each other.
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FIGURE 8: HALL SENSOR OUTPUT
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Chapter 3
dsPIC30F2010
3.1 Introduction
The dsPIC30F2010 [2] is a 28-pin 16-bit MCU specifically designed for embedded motor control applications. AC Induction Motors (ACIM), Brushless DC (BLDC) and DC are some typical motor types for which the dsPIC30F2010 has been specifically designed.
3.2 Features
Modified Harvard architecture C compiler optimized instruction set architecture 84 base instructions with flexible addressing modes 24-bit wide instructions, 16-bit wide data path 12 Kbytes on-chip Flash program space 512 bytes on-chip data RAM 1 Kbyte non-volatile data EEPROM 16 x 16-bit working register array Up to 30 MIPs operation o DC to 40 MHz external clock input o 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x) 27 interrupt sources Three external interrupt sources 8 user selectable priority levels for each interrupt 4 processor exceptions and software traps
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3.2.1 DSP Engine Features

Modulo and Bit-Reversed modes Two, 40-bit wide accumulators with optional saturation logic 17-bit x 17-bit single cycle hardware fractional/ integer multiplier Single cycle Multiply-Accumulate (MAC) operation 40-stage Barrel Shifter Dual data fetch
3.2.2 Peripheral Features

High current sink/source I/O pins: 25 Ma/25 Ma Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules Four 16-bit Capture input functions Two 16-bit Compare/PWM output functions o Dual Compare mode available 3-wire SPITM modules (supports 4 Frame modes) I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing Addressable UART modules with FIFO buffers
3.2.3 Motor Control PWM Module Features

6 PWM output channels o Complementary or Independent Output modes o Edge and Center Aligned modes 4 duty cycle generators Dedicated time base with 4 modes Programmable output polarity Dead time control for Complementary mode Manual output control Trigger for synchronized A/D conversions
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3.2.4 Quadrature Encoder Interface Module Features

Phase A, Phase B and Index Pulse input 16-bit up/down position counter Count direction status Position Measurement (x2 and x4) mode Programmable digital noise filters on inputs Alternate 16-bit Timer/Counter mode Interrupt on position counter rollover/underflow
3.2.5 Analog Features

10-bit Analog-to-Digital Converter (A/D) with: o 500 Ksps (for 10-bit A/D) conversion rate o Six input channels o Conversion available during Sleep and Idle Programmable Brown-out Detection and Reset generation
3.2.6 Special Microcontroller Features

Enhanced Flash program memory: o 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical) Data EEPROM memory: o 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical) Self-reprogrammable under software control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation Fail-Safe clock monitor operation Detects clock failure and switches to on-chip low power RC oscillator
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Programmable code protection In-Circuit Serial Programming (ICSP) Selectable Power Management modes o Sleep, Idle and Alternate Clock modes
3.2.7 CMOS Technology

Low power, high speed Flash technology Wide operating voltage range (2.5V to 5.5V) Industrial and Extended temperature ranges Low power consumption
3.3 Pin Diagram
FIGURE 9: PIN DIAGRAM OF dsPIC30F2010
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FIGURE 10: dsPIC30f2010 BLOCK DIAGRAM
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3.3.1 Explanation of each pin

Pin Pin Name Type AN0 I AN5 AVDD P AVSS P CLKI I CLKO O Buffer Type Analog P P ST/ CMOS Description Analog input channels. Positive supply for analog module. Ground reference for analog module. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. ICD Secondary Communication Channel data input/output pin ICD Secondary Communication Channel clock input/output pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin. Capture inputs. The dsPIC30F2010 has 4 capture inputs. The inputs are numbered for consistency with the inputs on larger device variants. Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. External interrupt 0 External interrupt 1 External interrupt 2 PWM Fault A input PWM 1 Low output PWM 1 High output PWM 2 Low output PWM 2 High output PWM 3 Low output PWM 3 High output Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare outputs.
CN0 CN7 EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3 IC1, IC2, IC7, IC8 INDX QEA QEB
I I/O I/O I/O I/O I/O I/O I/O I/O I
ST ST ST ST ST ST ST ST ST ST
I I I
ST ST ST
INT0 INT1 INT2 FLTA PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H MCLR
I I I I O O O O O O I/P
ST ST ST ST ST ST
OCFA I OC1 O OC2
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Pin Name OSC1 OSC2
Pin Type I I/O
PGD PGC RB0-RB5 RC13RC14 RD0RD1 RE0-RE5, RE8 RF2, RF3 SCK1 SDI1 SDO1 SS1 SCL SDA SOSCO SOSCI T1CK T2CK U1RX U1TX U1ARX U1ATX VDD VSS VREF+ VREFLegend CMOS Analog ST O I P
I/O I I/O I/O I/O I/O I/O I/O I O I I/O I/O O I I I I O I O P P I I
Buffer Description Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST In-Circuit Serial Programming data input/output pin. ST In-Circuit Serial Programming clock input pin. ST PORTB is a bidirectional I/O port. ST PORTC is a bidirectional I/O port. ST ST ST ST ST ST ST ST ST/CMOS ST ST ST ST Analog Analog PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. Synchronous serial clock input/output for SPI #1. SPI #1 Data In. SPI #1 Data Out. SPI #1 Slave Synchronization. Synchronous serial clock input/output for I2CTM Synchronous serial data input/output for I2CTM. 32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Timer1 external clock input. Timer2 external clock input. UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Analog Voltage Reference (High) input. Analog Voltage Reference (Low) input.
CMOS compatible input or output Analog input Schmitt Trigger input with CMOS levels Output Input Power
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3.4 CPU Architecture Overview

The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant (LS) bit always clear (see Section 3.1), and the Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
The working register array consists of 16x16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls. The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory AGU, which provides the appearance of a single unified data space. The MultiplyAccumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. There are two methods of accessing data stored in program memory: The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method. Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.
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Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.
The X AGU also supports bit-reversed addressing on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing. The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.
For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory, while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.
The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions.
The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined natural order. Traps have fixed priorities, ranging from 8 to 15.
3.5 Programmers Model

The programmers model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing. Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows. PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred. DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end. When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.
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3.5.1 Software Stack Pointer/FRAMe pointer

The dsPIC devices contain a software stack. W15 is the dedicated software stack pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames). W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space. W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.
3.5.2 Status Register

The dsPIC core has a 16-bit status register (SR), the LS Byte of which is referred to as the SR Low Byte (SRL) and the MS Byte as the SR High Byte (SRH). See Figure 2-1 for SR layout. SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0>, and the REPEAT active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked. The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit.
3.5.3 Program Counter

The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.
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FIGURE 11: PROGRAMMERS MODEL
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3.6 DSP Engine

The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter, and a 40-bit adder/ subtractor (with two target accumulators, round and saturation logic).
The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below: Fractional or integer DSP multiply (IF). Signed or unsigned DSP multiply (US). Conventional or convergent rounding (RND). Automatic saturation on/off for AccA (SATA). Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). Accumulator Saturation mode selection (ACCSAT).
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Chapter 4
CHANGE NOTIFICATION
4.1 Introduction
The Change Notification (CN) [3] pins provide dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change of state on selected input pins. Up to 24 input pins may be selected (enabled) for generating CN interrupts. The total number of available CN inputs is dependent on the selected dsPIC30F device.
FIGURE 12: INPUT CHANGE NOTIFICATION BLOCK DIAGRAM
4.1.1 CN Control Registers
There are four control registers associated with the CN module. The CNEN1 and CNEN2 registers contain the CNxIE control bits, where x denotes the number of the CN input pin. The CNxIE bit must be set for a CN input pin to interrupt the CPU.
The CNPU1 and CNPU2 registers contain the CNxPUE control bits. Each CN pin has a weak pull-up device connected to the pin, which can be enabled or disabled using the CNxPUE control bits. The weak pull-up devices act as a current source that is connected
to the pin and eliminate the need for external resistors when push button or keypad devices are connected.
4.1.2 CN Configuration and Operation

The CN pins are configured as follows:
1. Ensure that the CN pin is configured as a digital input by setting the associated bit in the TRISx register. 2. Enable interrupts for the selected CN pins by setting the appropriate bits in the CNEN1 and CNEN2 registers. 3. Turn on the weak pull-up devices (if desired) for the selected CN pins by setting the appropriate bits in the CNPU1 and CNPU2 registers. 4. Clear the CNIF (IFS0<15>) interrupt flag. 5. Select the desired interrupt priority for CN interrupts using the CNIP<2:0> control bits (IPC3<14:12>). 6. Enable CN interrupts using the CNIE (IEC0<15>) control bit.
When a CN interrupt occurs, the user should read the PORT register associated with the CN pin(s). This will clear the mismatch condition and setup the CN logic to detect the next pin change. The current PORT value can be compared to the PORT read value obtained at the last CN interrupt to determine the pin that changed.
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4.1.3 CN Operation in Sleep and Idle Modes

The CN module continues to operate during Sleep or Idle modes. If one of the enabled CN pins changes states, the CNIF (IFS0<15>) status bit will be set. If the CNIE bit (IEC0<15>) is set, the device will wake from Sleep or Idle mode and resume operation.
If the assigned priority level of the CN interrupt is equal to or less than the current CPU priority level, device execution will continue from the instruction immediately following the SLEEP or IDLE instruction.
If the assigned priority level of the CN interrupt is greater than the current CPU priority level, device execution will continue from the CN interrupt vector address.
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Chapter 5
GENERATION OF PWM SIGNALS

5.1 Introduction
The motor control PWM (MCPWM) [3] module simplifies the task of generating multiple, synchronized pulse width modulated outputs. In particular, the following power and motion control applications are supported Three-Phase AC Induction Motor Switched Reluctance (SR) Motor Brushless DC (BLDC) Motor Uninterruptable Power Supply (UPS)
The PWM module has the following features: Dedicated time base supports TCY/2 PWM edge resolution Two output pins for each PWM generator Complementary or independent operation for each output pin pair Hardware dead time generators for complementary mode Output pin polarity programmed by device configuration bits Multiple output modes: o Edge aligned mode o Center aligned mode o Center aligned mode with double updates o Single event mode Manual override register for PWM output pins Duty cycle updates are configurable to be immediate or synchronized to the PWM Hardware fault input pins with programmable function Special Event Trigger for synchronizing A/D conversions Each output pin associated with the PWM can be individually enabled
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5.2 Motor Control PWM Module

The dsPIC30F2010 has six PWM outputs that can be driven with the PWM signal. As shown in Figure 2, the three windings can be driven ON High, driven ON Low or not driven at all by using six switches, IGBTs or MOSFETs. When one leg of the winding is connected for example, to the high side, the variable duty cycle signal PWM can be injected on the low side driver. This has the same effect as having a PWM signal on the high side and connecting the low side to VSS or GND. When driving the PWM signal, low side drivers are preferred over high side drivers.
FIGURE 13: PWM MODULE
PWM is provided by the dsPIC30F2010s dedicated Motor Control (MC) PWM. The MCPWM module has been designed specifically for motor control applications. (Please refer to Figure 3 as you follow this discussion of the MCPWM module.)
The MCPWM has a dedicated 16-bit PTMR time base register. This timer is incremented by a user defined clock tick, which can be as low as TCY. The user also decides the period required for the PWM by selecting a value and loading it in the PTPER registers. The PTMR is compared to the PTPER value at every TCY. When there is a match, a new period is started.
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FIGURE 14: EDGE CONTROLLED PWM
The duty cycle is controlled similarly, by loading a value in the three duty cycle registers. Unlike the period compare, the value in the duty cycle register is compared at every TCY/2 interval (i.e., twice as fast as the period compare). If there is a match between the PTMR value and the PDCx value, then the corresponding duty cycle output is driven low or high as dictated by the PWM mode selected. The three outputs from the duty cycle compare are channelled to a complementary output pair where one output is high while the other is low, and vice versa. The two outputs can also be configured as independent outputs. When driven as complementary outputs, a dead time can be inserted between the time the high level goes low and the low level goes high. This dead time is hardware configured and has a minimum value of TCY. Dead time insertion prevents inadvertent shoot-thru in output drivers.
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FIGURE 15: MOTOR CONTROL PWM MODULE BLOCK DIAGRAM
There are several modes in which the MCPWM module can be configured. Edge aligned output is probably the most common mode. Figure 4 depicts the operation of an edge aligned PWM. At the start of the period, the outputs are all driven high. As the PTMR increments, a match with the duty cycle registers causes the corresponding duty cycle output to go low thereby marking the end of the duty cycle. The PTMR match with
PTPER register caused a new period to start and all outputs go high to start a whole new cycle.
The important feature of the MCPWM used in this application is the Override Control. The Override Control is the last stage of the MCPWM module. It allows the user to directly write to the OVDCON register and control the output pins. The OVDCON register has two 6 bit fields in it. Each of the six bit fields corresponds to an output pin. The high byte portion of the OVDCON register, determines if the corresponding output pin is driven by a PWM signal (when set to 1) or (when set to 0) driven Active/Inactive by the corresponding bit field in the low byte portion of the OVDCON register. This feature allows the user to have PWM signals available, but not driving, at all output stages of the pins. For BLDC motors, the same value is written to all PDCx registers.
Depending on the value in the OVDCON register, the user can select which pin gets the PWM signal and which pin is driven active or inactive. When controlling the BLDC sensored motor it is necessary to excite two winding pairs depending on where the rotor is located and dictated by the value of the hall sensors. In the CN Interrupt Service routine the hall sensors are read and then the value of the sensors is used as an offset in a lookup table which corresponds to the value which will be loaded in the OVDCON register. Table 1 and Figure 5 show how different values are loaded in the OVDCON register depending on which sector the rotor is located in and thereby which windings need to be excited.
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Chapter 6
MOSFET MOTOR DRIVER

6.1 Introduction
The bridging element between the motor and MOSFET driver is normally in the form of a power transistor. This can be a bipolar transistor, MOSFET or an Insulated Gate Bipolar Transistor (IGBT). In some small Brushless DC motor or stepper motor applications, the MOSFET driver can be used to directly drive the motor. For this application note, though, we are going to assume that a little more voltage and power capability is needed than what the MOSFET drivers can handle.
The purpose of motor speed control is to control the speed, direction of rotation or position of the motor shaft. This requires that the voltage applied to the motor is modulated in some manner. This is where the power-switching element (bipolar transistor, MOSFET, IGBT) is used. By turning the power-switching elements on and off in a controlled manner, the voltage applied to the motor can be varied in order to vary the speed or position of the motor shaft.
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6.2 Hardware Description
FIGURE 16: BLOCK DIAGRAM
The three pairs of Motor Control PWM outputs are connected to three MOSFET driver pairs (BC547), which in turn are connected to six MOSFETs (IRF547 and IRF9540). These MOSFETs are connected in a three-phase bridge format to the three BLDC motor windings. In the current implementation, the maximum MOSFET voltage is 70Volts, and the maximum MOSFET current is 18 Amps.
6.3 MOSFET Driver

MOSFET Driver along with three phase half bridge driver sends the PWM switching pulses to the BLDC Motor. It is biased for switching operation which consists of high side switching and low side switching. In this circuit MOSFET Driver comprises of BJTs (BC547) which is biased as emitter to base bias for high side switching and collector bias technique for low side switching.
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6.3.1 MOSFET Driver Circuit for high side switching
The base resistor RB and collector RC values are found using the formulae,
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6.3.2 MOSFET Driver Circuit for low side switching
The emitter resistor RE and collector RC values are found using the formulae,
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6.4 Three phase half bridge

It produces PWM signals required for controlling of the BLDC Motor. MOSFET is used as switch for producing the PWM Signals. Switching circuit consists of Low side switching and high side switching IRF540 is used for low side switching IRF9540 is used for high side switching
6.4.1 Three phase half bridge circuit with driver
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Chapter 7
PI CONTROLLER
7.1 Introduction
Commutation ensures proper rotor rotation of the BLDC motor, while the motor speed depends only on the amplitude of the applied voltage. The amplitude of the applied voltage is adjusted by using the PWM technique. The required speed is controlled by a speed controller. The speed controller is implemented as a conventional PI controller. The difference between the actual and required speed is input to the PI controller and, based on this difference, the PI controller controls the duty cycle of PWM pulses, which corresponds to the voltage amplitude required to keep the required speed.
7.2 Mathematical Model
FIGURE 16: BLOCK DIAGRAM OF PI CONTROLLER
The speed controller calculates a Proportional-Integral (PI) [5] algorithm according to the following equations: ( ) [ ( ) ( ) ]
Transformation to a discrete time domain using an integral approximation by a Backward Euler method yields the following equations for the numerical PI controller calculation:
( )
( )
( ) ( )
( )
( Where, e(k) w(k) m(k) u(k) up(k) uI(k) uI(k-1) TI T Kc = = = = = = = = = = Input error in step k Desired value in step k Measured value in step k Controller output in step k
( )
Proportional output portion in step k Integral output portion in step k Integral output portion in step k-1 Integral time constant Sampling time Controller gain
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7.3 Flowchart for speed control of BLDC Motor
FIGURE 17: FLOWCHART
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Chapter 8
UART
8.1 Introduction
The Universal Asynchronous Receiver Transmitter (UART) [4] module is one of the serial I/O modules available in the dsPIC30F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, RS-232 and RS-485 interfaces. The primary features of the UART module are: Full-duplex 8- or 9-bit data transmission through the UxTX and UxRX pins Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Fully integrated Baud Rate Generator with 16-bit prescaler Baud rates ranging from 29 bps to 1.875 Mbps at FCY = 30 MHz 4-deep First-In-First-Out (FIFO) transmit data buffer 4-deep FIFO receive data buffer Parity, Framing and Buffer Overrun error detection Support for 9-bit mode with Address Detect (9th bit = 1) Transmit and Receive Interrupts Loopback mode for diagnostic support
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8.2 Block Diagram
FIGURE 18: BLOCK DIAGRAM OF UART
A simplified block diagram of the UART is shown in Figure 18. The UART module consists of the key important hardware elements: Baud Rate Generator Asynchronous Transmitter Asynchronous Receiver
8.3 UART Configuration

The UART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits, and one or two Stop bits). Parity is supported by the hardware, and may be configured by the user as even, odd or no parity. The most common data format is 8 bits, no parity and one Stop bit (denoted as 8, N, 1), which is the default (POR) setting. The number of data bits and Stop bits, and the parity, are specified in the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. An on-chip dedicated 16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The UART transmits and receives the LSb first. The UARTs transmitter and receiver are functionally independent, but use the same data format and baud rate.
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8.4 UART Transmitter

The UART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the Transmit Shift register (UxTSR). The Shift register obtains its data from the transmit FIFO buffer, UxTXREG. The UxTXREG register is loaded with data in software. The UxTSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the UxTSR is loaded with new data from the UxTXREG register.
FIGURE 19: UART TRANSMITTER
Transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The actual transmission will not occur until the UxTXREG register has been loaded with data and the Baud Rate Generator (UxBRG) has produced a shift clock (Figure 19-2). The transmission can also be started by first loading the UxTXREG register and then setting the UTXEN enable bit. Normally when transmission is first started, the UxTSR register is empty, so a transfer to the UxTXREG register will result in an immediate transfer to UxTSR. Clearing the UTXEN bit during a transmission will cause the transmission to be
aborted and will reset the transmitter. As a result, the UxTX pin will revert to a highimpedance state.
In order to select 9-bit transmission, the PDSEL<1:0> bits (UxMODE<2:1>) should be set to 11 and the ninth bit should be written to the UTX9 bit (UxTXREG<8>). A word write should be performed to UxTXREG so that all nine bits are written at the same time.
8.4.1 Transmit Buffer

Each UART has a 4-deep, 9-bit wide FIFO transmit data buffer. The UxTXREG register provides user access to the next available buffer location. The user may write up to 4 words in the buffer. Once the UxTXREG contents are transferred to the UxTSR register, the current buffer location becomes available for new data to be written and the next buffer location is sourced to the UxTSR register. The UTXBF (UxSTA<9>) status bit is set whenever the buffer is full. If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO.
The FIFO is reset during any device Reset, but is not affected when the device enters a Power saving mode or wakes up from a Power saving mode.
8.4.2 Transmit Interrupt
The transmit interrupt flag (UxTXIF) is located in the corresponding interrupt flag status (IFS) register. The UTXISEL control bit (UxSTA<15>) determines when the UART will generate a transmit interrupt. 1. If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word. Since an interrupt is generated after the transfer of each individual word, this mode is useful if interrupts can be handled frequently (i.e., the ISR is completed before the transmission of the next word). 2. If UTXISEL = 1, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) and the transmit buffer is empty. Since an interrupt is generated only after all 4 words have been transmitted,
Page 45
this Block Transmit mode is useful if the users code cannot handle interrupts quickly enough (i.e., the ISR is completed before the transmission of the next word).
The UxTXIF bit will be set when the module is first enabled. The user should clear the UxTXIF bit in the ISR. Switching between the two Interrupt modes during operation is possible. While the UxTXIF flag bit indicates the status of the UxTXREG register, the TRMT bit (UxSTA<8>) shows the status of the UxTSR register. The TRMT status bit is a read only bit, which is set when the UxTSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the UxTSR register is empty.
8.4.3 Steps for UART Transmit

Steps to follow when setting up a transmission 1. Initialize the UxBRG register for the appropriate baud rate 2. Set the number of data bits, number of Stop bits, and parity selection by writing to the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. 3. If transmit interrupts are desired, set the UxTXIE control bit in the corresponding Interrupt Enable Control register (IEC). Specify the interrupt priority for the transmit interrupt using the UxTXIP<2:0> control bits in the corresponding Interrupt Priority Control register (IPC). Also, select the Transmit Interrupt mode by writing the UTXISEL (UxSTA<15>) bit. 4. Enable the UART module by setting the UARTEN (UxMODE<15>) bit. 5. Enable the transmission by setting the UTXEN (UxSTA<10>) bit, which will also set the UxTXIF bit. The UxTXIF bit should be cleared in the software routine that services the UART transmit interrupt. The operation of the UxTXIF bit is controlled by the UTXISEL control bit. 6. Load data to the UxTXREG register (starts transmission). If 9-bit transmission has been selected, load a word. If 8-bit transmission is used, load a byte. Data can be loaded into the buffer until the UxTXBF status bit (UxSTA<9>) is set.
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Chapter 9
ANALOG TO DIGITAL CONVERTOR

9.1 Introduction
The dsPIC30F2010 10-bit A/D converter has the following key features: Successive Approximation (SAR) conversion Up to 1 Msps conversion speed Up to 16 analog input pins External voltage reference input pins Four unipolar differential S/H amplifiers Simultaneous sampling of up to four analog input pins Automatic Channel Scan mode Selectable conversion trigger source 16 word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes
9.2 Block Diagram

A block diagram of the 10-bit A/D is shown in Figure 17-1. The 10-bit A/D converter can have up to 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific dsPIC30F device. Refer to the device data sheet for further details.
The analog inputs are connected via multiplexers to four S/H amplifiers, designated CH0CH3. One, two, or four of the S/H amplifiers may be enabled for acquiring input data. The analog input multiplexers can be switched between two sets of analog inputs during conversions. Unipolar differential conversions are possible on all channels using certain input pins.
An Analog Input Scan mode may be enabled for the CH0 S/H amplifier. A Control register specifies which analog input channels will be included in the scanning sequence.
The 10-bit A/D is connected to a 16-word result buffer. Each 10-bit result is converted to one of four 16-bit output formats when it is read from the buffer.
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FIGURE 20: BLOCK DIAGRAM OF ADC
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9.3 Control Registers

The A/D module has six Control and Status registers. These registers are: ADCON1: A/D Control Register 1 ADCON2: A/D Control Register 2 ADCON3: A/D Control Register 3 ADCHS: A/D Input Channel Select Register ADPCFG: A/D Port Configuration Register ADCSSL: A/D Input Scan Selection Register
The ADCON1, ADCON2 and ADCON3 registers control the operation of the A/D module. The ADCHS register selects the input pins to be connected to the S/H amplifiers. The ADPCFG register configures the analog input pins as analog inputs or as digital I/O. The ADCSSL register selects inputs to be sequentially scanned.
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Chapter 10
CONCLUSION
The dsPIC30F2010 is well suited for closed loop control of a sensored BLDC motor. The peripherals and DSP engine provide an excellent bandwidth for sensored BLDC applications with sufficient code space available for the customers application program.
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Chapter 11
SCOPE OF THE PROJECT

11.1 Typical BLDC Applications
BLDC motors find applications in every segment of the market. Automotive, appliance, industrial controls, automation, aviation and so on, have applications for BLDC motors. Out of these, we can categorize the type of BLDC motor control into three major types: Constant load [1] Varying loads [1] Positioning applications [1]
11.1.1 Applications with constant loads

These are the types of applications where a variable speed is more important than keeping the accuracy of the speed at a set speed. In addition, the acceleration and deceleration rates are not dynamically changing. In these types of applications, the load is directly coupled to the motor shaft. For example, fans, pumps and blowers come under these types of applications. These applications demand low-cost controllers, mostly operating in open-loop.
11.1.2 Applications with Varying Loads

These are the types of applications where the load on the motor varies over a speed range. These applications may demand high-speed control accuracy and good dynamic responses. In home appliances, washers, dryers and compressors are good examples. In automotive, fuel pump control, electronic steering control, engine control and electric vehicle control are good examples of these. In aerospace, there are a number of applications, like centrifuges, pumps, robotic arm controls, gyroscope controls and so on. These applications may use speed feedback devices and may run in semi-closed loop or in total closed loop. These applications use advanced control algorithms, thus complicating the controller. Also, this increases the price of the complete system.
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11.1.3 Positioning Applications

Most of the industrial and automation types of application come under this category. The applications in this category have some kind of power transmission, which could be mechanical gears or timer belts, or a simple belt driven system. In these applications, the dynamic response of speed and torque are important. Also, these applications may have frequent reversal of rotation direction. A typical cycle will have an accelerating phase, a constant speed phase and a deceleration and positioning phase. The load on the motor may vary during all of these phases, causing the controller to be complex. These systems mostly operate in closed loop. There could be three control loops functioning simultaneously: Torque Control Loop, Speed Control Loop and Position Control Loop. Optical encoder or synchronous resolvers are used for measuring the actual speed of the motor. In some cases, the same sensors are used to get relative position information. Otherwise, separate position sensors may be used to get absolute positions. Computer Numeric Controlled (CNC) machines are a good example of this. Process controls, machinery controls and conveyer controls have plenty of applications in this category.
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Chapter 12
REFERENCES
[1] N. Hemati and M. C. Leu, A complete model characterization of brushless dc motors, IEEE Trans. Ind. Applicat., vol. 28, pp. 172180, Jan./Feb. 1992. [2] [3] dsPIC30F reference manual A. R. Millner, Multi-hundred horsepower permanent magnet brushless disc motors, in Proc. IEEE Appl. Power Electron. Conf. (APEC94), Feb. 1317, 1994, pp. 351355. [4] [5] dsPIC30F2010 datasheet Yasuhiko Dote. Servo Motor and Motion Control using Digital Signal Processors Prentice Hall, Eagle Wood, Cliffs, New Jersey, 1990.
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CONTROL OF BLDC MOTOR USING dsPIC30F2010

AMC Engineering College | Dept. of EEE