CHAPTER 9

2008 Pearson Education, Inc.

9-1.
log2 64 = 6 lines/mux or decoder

9-2.*
C = C8 V = C8 C7 Z = F 7 + F6 + F 5 + F4 + F3 + F 2 + F1 + F0 N = F7

9-3.*
X = S0A + S0A Y = S1 Cin B + S1S0 B + S1S0B + S1S0Cin Cin

A0 A0

D0 D1 S

B0

D0 D1 D2

C0 X Adder Y C1 X G0

D3 S1 S0

S1 A1 A1 S0 0
D0 S1 S0 D1 S

Adder Y C2

G1

B1

D0 D1 D2 D3

9-4.* (Errata: Delete 1 after problem number)

S1

X = A S1 + A S0 Y = B S1 S0 + B S1

Ci
S0

Ai
S1 S0

X FA Y CI + 1 Gi

Bi 0 Bi Bi

D0 D1 D2 D3

9-5.
Connect to Cin for first stage. Ci MUX Bi 0 1 Bi 0 1 2 3 Ai X
FA

Y Ci +1 S1 S0 S Cin

Gi

00: G = A + B (Add) 01: G = A + 1 (Increment) 10: G = A 1 (Decrement) 11: G = A + B + 1 (Subtract)

Cascade four such stages, connecting the carries.

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Problem Solutions Chapter 9

9-6.*
a) XOR = 00, NAND = 01, NOR = 10 XNOR = 11 Out = S1 A B + S1AB + S1AB + S1S0AB + (one of S0 A B + S1 S0 A) b) The above is a simplest result.

9-7.+
S2 S1 S0 Operation S2 S1 S0 Operation 0 0 0 1 0 0 sr A A+B 0 0 1 A+B+1 1 0 1 AB 0 1 0 0 1 1 B B+1 1 1 0 1 1 1 sl A
CLi (from stage to right) CL0 = S0 S1 Ai X Y Cin FA Cout MUX 0 1 S S2 MUX 0 1 S S2 CLi+1 - (to stage to left) Fi

AB
Ai Bi

CL - Carry to the left CR - Carry to the right

S0 Bi CRi - (to stage to right) 0 MUX 1 2 3 S1 S0 S1 S0

CRi+1 - (from stage to left) CRn = 0

9-8.*
(a) 1010 (b) 1110 (c) 0101 (d) 1101

9-9.
DA (a) 101 (b) 100 (c) 111 (d) 011 (e) 001 (f) 001 (g) 010 (h) 100 AA 000 ------011 001 001 011 BA 000 101 --011 ----011 101 MB FS 0 0 0 1 0 0 1010 1110 ---1101 0101 0001 1010 0010 MD 0 0 1 0 0 0 0 0 RW 1 1 1 1 1 1 1 1

9-10.*
(a)

(b) (c)

R5 R 4 R5 R6 R 2 + R4 + 1 R5 R0

R5 = 0000 0100 R6 = 1111 1110 R5 = 0000 0000

(d) (e) (f)

R5 R0 R 4 sr Constant R 3 Data in

R5 = 0000 0000 R4 = 0000 0011 R3 = 0001 1011

9-11.
R 3 R 3 + R 1, R 3 = 01100111 R 4 R 4 R 1, R 4 = 01110100 R 5 R 5 R 1, R 5 = 01101100 R 1 R 1, R 1 = 11011111 R 1 R 1 + 1, R 1 = 1100000 R 6 R 6 + R 1 + 1, R 6 = 01100001 R 7 R 7 + R 1 + 1, R 7 = 01101001 R 1 R 7, R 1 = 01101001

R1 ... R7 = i, D, g, t, l, a, i Unscrambled is Digital

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Problem Solutions Chapter 9

9-12.
a) 64 b) 32 c) 0 to 65,535 d) 32,768 to +32,767

9-13.*
a) Opcode = 8 bits b) 18 bits c) 262,144 d) +131,071 and 131,072

9-14.
Distinct Opcodes = 4 + 16 + 127 = 148

9-15.
Instruction Register Transfer DA 000 001 010 011 xxx AA 111 100 101 xxx 100 BA 011 xxx xxx 110 xxx MB 0 x 1 0 x DR 000 001 010 011 100 FS 1010 xxxx 0010 1110 0000 SA 000 110 101 100 010 MD 0 1 0 0 x RW 1 1 1 1 0 MW 0 0 0 0 0 PL 0 0 0 0 1 JB x x x x 0

R [ 0] R [ 7 ] R [ 3 ] R [ 1 ] M [R [ 4 ] ] R[2 ] R[5 ] + 2 R [ 3 ] sl R [ 6 ] if R [ 4 ] = 0 then PC PC + se PC

Instruction Register Transfer

Operation Code 000 1101 001 0000 100 0010 000 1010 000 0101

SB or Operand 111 000 0100 011 001

R [ 0 ] = sr R [ 7 ] R [ 1 ] M[ R [ 6 ]] R [2] R[5] + 4 R [ 3 ] R [ 4] R [ 3 ] R[4] R[2 ] R[1]

9-16.
MB: B15 - Correct for table specification MD: B13 - Correct for table specification RW:B14 - Correct for table specification MW: B15 B14 - Correct for table specification PL: B15 B14 - Correct for table specification JB: B13 - Correct for table specification BC: B9 - Correct for table specification FS: The logic gives 0000 for FS for PL =1 which selects the value on the A input to the Function Unit to be evaluated for branches and blocks the value on bit 9 which is otherwise used as BC for branches. For PL = 0, the normal bits for FS are passed as required from the op code. Correct.

9-17.
Instruction

ADD R0, R1, R2 SUB R3, R4, R5 SUB R6, R7, R0 ADD R0, R0, R3 SUB R0, R0, R6 ST R7, R0 LD R7, R6 ADI R0, R6, 2 ADI R3, R6, 3

Code 000 0101 000 001 010 000 001 011 100 101 000 0101 110 111 000 000 0101 000 000 011 000 0101 000 000 110 010 0000 000 111 000 011 0000 111 110 000 100 0010 000 110 000 100 0010 011 110 011

Registers/Memory changed R0 = 3 R3 = -1 R6 = 4 R0 = 2 R0 = -2 M[7] = -2 R7 = M[4] R0 = 6 R3 = 7

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Problem Solutions Chapter 9

9-18.
R[4 ] R[ 4] R[4] V and C are produced by the arithmetic circuit. For the XOR FS code, S1 = 0, S0 = 1. and Cin = 0, giving arithmetic operation Add. For arbitrary contents in R[4], the values of C and V are a function of the sign and value of the contents of R4 and are unpredicable.

9-19.
Part (a) (b) (c) (d) State EX0 EX0 EX0 EX0 EX0 Opcode 0000101 0001101 1100000 1100000 0000000 VCNZ xxxx xxxx xxx0 xxx1 xxxx Next State EX1 INF INF INF INF IL PS 0 0 0 0 0 DX AX BX MB 0 0 x x x FS MD RW MM MW 0101 1101 0000 0000 0000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0

01 0xxx 0xxx 0xxx 01 1000 xxxx 1000 10 xxxx 0xxx xxxx 01 xxxx 0xxx xxxx 01 0xxx 0xxx xxxx

9-20.
State EX0 EX1 EX2 EX3 EX2 EX3 EX2 EX3 EX2 EX3 EX2 EX3 EX4 INF Instruction R8 0101100111000111 0101100111000111 0010110011100011 0010110011100011 0001011001110001 0001011001110001 0000101100111000 0000101100111000 0000010110011100 0000010110011100 0000001011001110 0000001011001110 0000001011001110 R9 x 5 5 4 4 3 3 2 2 1 1 0 0 Z 0 0 0 0 0 0 0 0 0 0 0 1 0 Next State EX1 EX2 EX3 EX2 EX3 EX2 EX3 EX2 EX3 EX2 EX3 EX4 INF -

R 8 R [ SA ] R 9 zfOP R 8 srR 8 R9 R9 1 R 8 srR 8 R9 R9 1 R 8 srR 8 R9 R9 1 R 8 srR 8 R9 R9 1 R 8 srR 8 R9 R9 1 R [ DR ] R 8

-

9-21.+
Removal of the two decisions on zero operations does not affect the number of states in the state machine diagram. The reason for this is that the same states are required because the datapath of the computer only supports one register transfer per clock cycle. The transfers required by the instruction execution force the state structure. As a consequence, there can be no reduction of the number of clock cycles required to execute the instructions. The new state machine diagram is actually a worst case in terms of execution time for the instruction execution. The two decisions can only improve the execution times. So the analysis suggested is unnecessary.

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Problem Solutions Chapter 9

9-22.
Partial state machine diagram:
EX0

Opcode = 0010001 R 8 R [ SB ]
EX1

Opcode = 0010001 R 9 M [ R [ SA ] ]
EX2

Opcode = 0010001 R [ DR ] R 8 + R 9 ,PC PC + 1

INF
State EX0 EX1 EX2 Opcode 0010001 0010001 0010001 VCNZ xxxx xxxx xxxx Next State EX1 EX2 INF IL 0 0 0 PS DX AX BX MB 0 x 0 FS MD RW MM MW 1100 xxxx 0010 0 1 1 1 1 0 0 0 0 0 0 0

00 1000 xxxx 0xxx 00 1001 0xxx xxxx 01 0xxx 1000 1001

9-23.
Partial state machine diagram: R8 R8 Opcode = 1000110 R8 R8 R8 Opcode = 1000101 EX0 Z ( Opcode = 1000110 )

EX1

Opcode = 1000101 R [ DR ] R [ SA ] + R [ SB ]
V ( Opcode = 1000110 )

V ( Opcode = 1000110 ) PC PC + 1
EX2

Z ( Opcode = 1000110 )
PC PC + 1
EX3

Opcode = 1000101
R8 R8 + 1,

Opcode = 1000110
INF

PC PC + 1

PC PC + se AD

Part

State EX0

Opcode 1000101 1000101 1000101 1000101 1000110 1000110 1000110

VCNZ xxxx 1xxx 0xxx xxxx xxx0 xxx1 xxxx

Next State EX1 EX2 INF INF EX3 INF INF

IL PS 0 0 0 0 0 0 0

DX

AX

BX

MB 0 0 0 0 x x x

FS MD RW MM MW 1010 0010 0010 0001 0000 0000 xxxx 0 0 0 0 0 0 0 1 1 1 1 1 1 0 x x x x x x x 0 0 0 0 0 0

00 0xxx 1000 1000 00 0xxx 0xxx 0xxx 01 0xxx 0xxx 0xxx 01 1000 1000 xxxx 00 1000 1000 xxxx 01 1000 1000 xxxx 10 xxxx xxxx xxxx

AOV

EX1 EX1 EX2 EX0

BRV

EX0 EX3

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Problem Solutions Chapter 9

9-24.
Partial state machine diagram:
EX0

R8 R8 R8 Opcode = 0010001

EX1

Opcode = 0010001 R 9 R [ SA ] R [ SB ]
Z ( O pcode = 0010001 )

EX3

Opcode = 0010001

EX2
Z N ( Opco de = 0010001 ) PC PC + 1 Z N ( Opc ode = 0010001 )

R8 R8 + 1 Opcode = 0010001 R [ DR ] R8 + 1, PC PC + 1

INF
Next State EX1 EX3 EX2 INF EX3 INF 0

PC PC + 1

State EX0 EX1 EX1 EX1 EX2 EX3

Opcode 0010001 0010001 0010001 0010001 0010001 0010001

VCNZ xxxx xxx1 xx00 xx10 xxxx xxxx

IL PS 0 0 0 0

DX

AX

BX

MB 0 0 0 0 x x

FS MD RW MM MW 1010 0101 0101 0101 0001 0001 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

00 1000 1000 1000 00 1001 0xxx 0xxx 00 1001 0xxx 0xxx 01 1001 0xxx 0xxx 00 1000 1000 xxxx 01 0xxx 1000 xxxx

9-25.+ (Errata: Add a + and the following hint. Hint: In order to address all eight registers, it is necessary to provide eight values for SB in the Instruction Register. Since the instruction register can only be loaded from memory, these instructions must be placed in memory temporarily during the instruction execution and loaded into the IR as data without using the normal instruction fetch. ) The operation code used for SMR and these instructions is 0111111 which is easy to generate by complementing all 0s. The word to be stored in memory is built in a register by complementing all 0s and ANDing the result with the value of SB from the original instruction. The register value generated is incremented, stored in memory and loaded into the IR after the execution of each transfer from a register to a memory location.
Register Transfer R8 R[SA] R9 R9 R9 (R9 0) R9 R9 R10 sr R9 R9 R10 zf SB R11 zf SB M[R10] R9 IR M[R10] M[R8] R[SB] R8 R8 + 1 R9 R9 + 1 R11 zf SB, Z : EX5 State EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 EX8 EX9 EX10 EX11 Opcode 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 0111111 VCNZ xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 xxx1 Next State EX1 EX2 EX3 EX4 EX5 EX6 EX7 EX8 EX9 EX10 EX11 EX5 INF IL PS 0 0 0 0 0 0 0 1 0 0 0 0 0 DX AX BX MB 0 0 x x 1 1 0 x 0 x x 1 1 FS MD RW MM MW 0000 1010 1011 1101 1000 1100 xxxx xxxx xxxx 0001 0001 0101 0101 1 0 0 0 0 0 x x 1 0 0 x x 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

00 1000 0xxx xxxx 0 0 0 0 0 0 0 0 0 0 0 1001 1001 1001 1001 1001 xxxx 1010 1001 xxxx 1001 1010 xxxx 1011 xxxx xxxx xxxx 1010 1001 xxxx 1010 xxxx xxxx 1000 0xxx 1000 1000 xxxx 1001 1001 xxxx xxxx 1011 xxxx

R11 zf SB, Z : INF, inc PC EX11

01 xxxx 1011 xxxx

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Problem Solutions Chapter 9

9-26. (Errata: Solution of this problem with the architecture available is too difficult and while it can be solved, any solution is highly impractical. It will be removed in the 2nd and subsequent printings.)

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