IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO.

3, JUNE 1996

441

A New Control Strategy to Achieve Sinusoidal Line Current in a Cascade Buck-Boost Converter
Mohamed C. Ghanem, Kamal Al-Haddad, Senior Member, IEEE, and Gilles Roy, Member, IEEE
Abstruct- This work presents a detailed theoretical analysis and experimental results of a novel means of obtaining sinusoidal input current and unity power factor (UPF) via a cascade buckboost converter. Using the new configuration, sinusoidal line current in phase with the bus voltage is achieved, thanks to a new and simple to implement control strategy. Comparison between the input and output voltages is used to select the instantaneous operating mode of the converter. Off-line references are calculated and stored in two EPROM circuits and then compared to measured currents to generate the gating signals of the appropriate switches. Complete theoretical analysis, simulation results and experimental data on a 500 W converter are presented, to demonstrate the superiority of the new control strategy. Low order harmonicsin the input current are eliminated and the input power factor is found to be over 0.99.

lR

L
0 A

(a)

I. INTRODUCTION
generate high harmonic current which can interfere with and disturb communication networks. These currents also result in distorted line voltage. Different alternatives of dynamic switching patterns of power devices andlor passive filter elements have been proposed earlier to improve the quality of input current waveform of power converters. Active power factor correction techniques have become increasingly desirable in off-line industrial equipment. Several active schemes have been proposed and analyzed for shaping the line current for single-phase applications [ 11, [7]. Power factor correction has been achieved using various power conversion techniques [81, 1121. The most popular methods used in the industry today incorporate the boost topology (Fig. l(a)). The topology is adequate to operate in the continuous conduction mode for high power application or in the discontinuous conduction mode for lower output power. The buck regulator (Fig. l(b)) can also be used for the same purposes, but with reduced efficiency as compared to the boost converter. The principal drawback of this approach is the noticeable sharp turn-off of power conversion as the instantaneous line voltage falls below the output voltage which degrades the power factor and generates high order harmonics.
Manuscript received June 20, 1993; revised June 12, 1995, July 3, 1995, and November 12, 1995. This work was supported by the National Science and Engineering Council of Canada (NSERC), Hydro Quebec, and the Government of Quebec via the FCAR Fund. M. C. Ghanem and K. Al-Haddad are with the Department of Electrical Engineering, Ecole de Technologie SupCrieure, Montreal, QuBbec, Canada, H2T 2C8. G. Roy is with the Department of Electrical and Computer Engineering, Ecole Polytechniqne de MontrCal, Montrkal, QuBbec, Canada, H3C 3A7. Publisher Item Identifier S 0278-0046(96)02378-7.

D S ' L

c 77
v

0
A

ONVENTIONAL off-line switch mode power supplies

Control Circuit
(b)

*"

*D3

I I/

1
Control Circuit

1
D

(c) Fig. 1. Typical converter schemes. (a) Boost converter scheme. (b) Buck converter scheme. (c) Buck-boost converter scheme.

It is desirable to enforce, in the converter, a nearly sinusoidal input line current, in phase with the line voltage. This is a timely subject and a number of articles on this topic were recently published [I]-[3]. In [2], a unity power factor forward converter is proposed. The circuit is split in two independent power stages: the input current shaping and the output voltage regulation. A continuous input current is achieved. However, with this technique only the buck mode is possible. This paper presents a new control strategy applied to the converter topology which combines the buck and boost modes in one power stage (Fig. l(c)) and provides a simpler solution for the unity power factor acldc converter problem (Fig. 2). The proposed topology has two distinct modes of operation. Mode 1 has output voltage less than or equal to the input

0278-0046/96$05.00 0 1996 IEEE

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO. 3, JUNE 1996

coefficients of the higher order harmonics of the input current less dependent on the output voltage. The converter operates with unity power factor independently of the output voltage. Operation Modes: The two operation modes are indicated in Fig. 3. For luil 5 U,, the converter operates in boost mode until point A, and only switch SWP is controlled (SWS being kept on). For luil 2 U,, (the operation falls between A and B), the converter operates in buck mode and the control law is applied only to switch SWS, (SWP being kept off).

A. Sequences in the Boost Operation Mode

Two sequences describing the boost operation with fixed hysteresis and variable switching period are shown in Fig. 4. When SWP is on, (sequence 1-Fig. 4(a)), the inductor current i~ rises and when it exceeds a preset upper limit i u l k (Fig. 5(a)) the transistor SWP turns off, (sequence 2-Fig. 4(b)) allowing the current to fall. When ZL becomes smaller than a lower limit i i l k the transistor SWP turns on and the current raises again. In this way, the rectified line current liil is confined between two boundaries having a peak to peak difference 26 and a mid value centered at the rectified fundamental reference input current irefl(corresponding to the kth switching period (Fig. 5(a))

Fig. 2. Unity power factor buck-boost converter with control circuits scheme.

[VI
200
,an . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

When the transistor SWP is on, the state equations are

dt , I 4
-

diL

and

l u i k l is the value of the rectified input voltage at the kth switching period. 6% and areflare respectively the amplitudes of the sinusoidal input voltage and the fundamental input current for the given power level
0 0.002 0.004 0.006 0.008

0.01

0,012

0.014

0.016

t i n sec

Fig. 3. Input voltage and output voltage.

When the transistor SWP is off, the state equations are rectified voltage and mode 2 has output voltage greater than or equal to the input rectified voltage as shown in Fig. 3. A discussion on the principles of operation is followed by a detailed analysis showing the static and dynamic characteristics of the converter. The converter has boost mode operation with fixed hysteresis and buck mode operation with variable hysteresis. The control strategy proposed for the unity power factor buck-boost converter is described and finally simulation and experimental results are presented. 11. ANALYSIS OF THE PROPOSED CIRCUIT In this circuit (Fig. l(c)) both buck and boost modes of operation are used in each ac half cycle to achieve an output dc voltage lower or greater than the maximum rectified input voltage. It is found that this technique makes, the Fourier
diL
~

dt

- --we L

1 + -luikI L

(4) (5)

and

The inductor current i~ and the capacitor voltage vc are taken as state variables and IC is the state vector. The differential equations associated with sequences 1 and 2 can be expressed in matrix form by (6) and (7)

li: =

0 ["

-& ]

[iL] + [k]
U,

/uikl

(SWP on)

(6)

GHANEM et al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT

443

Ds

*
IC

swe'
Correction Circuit

c=

L 0 A

/ befl(kt1)

i]Power Factor I

b t
t2(k -1) I TPk

Correction Circuit

+t

Power Factor Correction Circuit

(C)

A k j i
113n

--an

toff

ui
2,

ii c

XD1

02

'

Ds 1ED4

f 03

-I
SWP

+t
IC

kn

tcn

cFq
(c)
Fig. 5 . Input current and inductor current in buck and boost modes. (a) Choke current waveform in case of the boost operation. (b) Input current i;in buck mode. (c) Inductor current i~ in buck mode.

Power Factor Correction

Fig. 4. Equivalent circuits of buck-boost converter in buck and boost modes. (a) Sequence 1, switch SWP is on. (b) Sequence 2, switch SWP is off. (c) Sequence 3, switch SWS is on. (d) Sequence 4, switch SWS is off.

In the sequence 3, the switch SWS is on (Ds being off) and the corresponding state equations are

and

B. Sequences in the Buck Operation Mode

Two sequences describing the buck operation with variable hysteresis and fixed switching period are shown in Fig. 4. When SWS is on (sequence 3-Fig. 4(c)), the inductor current rises. When it exceeds a preset upper limit iuan (which is calculated in Section 111), the transistor SWS is turned off, and Ds turns on (sequence 4-Fig. 4(d)), and the inductor current falls. When i~ becomes smaller than the lower limit i / z n (Fig. 5(b) and (c)), SWS turns on and the current starts rising again. In this way, the average line current is confined in a band around the sinusoidal reference irefl which determines the output power.

i L = i,

+ iR

(9)

dvc i, = cdt
Substituting (10) and (11) in the (9) gives

dv, - 1 1 dv, U, then +(12) dt - Z t L dt R In the sequence 4, the switch SWS is off (Ds is on) and the state equations are
i~ = C,

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EEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO.3, JUNE 1996

dw, 1. 1 -2L - -vc. (14) dt C RC The differentiad equations of sequence 3 and 4 can be expressed in matirix form
--

and

vc(t)= vco exp

-~

where the initial condition of the current is

iZlk

= iLlt=tok

and by solving for (4) and assuming that we is fixed we can write for t l k 5 t 5 t 2 k : (Fig. 5(a)) the inductor current as 111. CONTROL STRATEGY The purpose of the new control law introduced here is to change the naturallly non linear impedance of the converter to a linear one. A sinusoidal input current with unity displacement factor is enforced in order to achieve such an operation. The This mode involves boost mode is used when U , 2 /uil. operation with fixed current hysteresis and variable switching period. The buck mode is used when U , 5 I u ; ~ and it involves operation with fixed switching period and variable current hysteresis. A relationship between switching sequence of SWS and SWP and the input current shape is established for the buck and boost modes of operation. The switching scheme of the new control strategy is shown in Fig. 2. A comparison between the measured choke current i~ and the synchronized reference current!; (boost mode) and ire^ (buck mode) defines the control law of the switches. The variable duty cycle of the switches SWP and SWS is controlled by means of a window comparator. The reference current waveforms are generated from tables stored in the memory (EPROM). Regulation of the dc output voltage is accomplished by varying the reference current waveform. This control selects the appropriate input reference current stored in the memory. An output control loop is used to regulate the output power (variation of the load). This control adjusts the input reference current magnitude by an amount in proportion to the difference between the actual and desired values of the power.
A. Duty Cycle Computation in Boost Mode

iLlt=tZk = i Z l ( k t 1 )

=illk
-

+ luL i kI
--(tZk

t O k ) - -(tzrc we

tlk)

- ireflk - 6 (23) and by solving for ( 5 ) ( i is ~ fixed) we can write the output voltage as

The average value of the input rectified current within the switching period T p k is given by the following integrals:

Tpk:

switching period in boost mode (see Fig. 5(a)). From ( 1 8 ) , (22), and (25) we obtain

In boost mode, the inductor current is monitored, and the state of the switch SWP is controlled in each switching period to move the line current magnitude in the desired form. Fig. 5(a) shows the waveform of the current flowing in the choke during one switching period T p k . The upper and lower values of the current boundaries and the fixed current hysteresis are related by the following expressions where i r e f l k is given by (1)

Equation (28) shows the relationship of the power level at the kth switching cycle and a p k

6 =: iu l l i

- ireflk

ireflk - iulk.

(17)
tlk:

The input power can be controlled by changing 5refl. By solving for (2) and (3), we can write for t o k 5 t 5 (Fig. 5 ( 4 )

The duty cycle

(18)

olpk(olpkTpk

=tlk

tOk)

is obtained as

iulk

= iLit=t1,, = Z l l k = treflk

+6

+ -IUik/ (tlk L

tOk)

(19)

Equation (31) is the basis of the control strategy for the boost mode operation. Once the design assumption on the value of

GHANEM et al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT

445

[AI

25

[VI [AI

200

-200

'

'

'

'

'

0.004

0.008
(a)

0.012 0.016

t i n msec

[AI

25

.
I

.
,

.
I

.
'

tin sec

0
4.5 4

0.004 0.008 0.012 0.016

(b)

C A I

3
1 2 3 4 5 6 7 8

2 1
.........................

t in msec
(b) Fig. 6. Reference currents for case 1 and case 2 (simulation results). (a) Case l(Uo = 50 V and Po = 500 W). (b) Case 2 (U, = 100 V and Po = 500 W).

H z
60'

400
(C)

800

1200

the current hysteresis 6 is made the value of a p k is calculable. The switching period of the ( k + 1)th cycle is derived on the basis of the ON/OFF durations in the kth cycle.
Tp(k+l)=t2k
-tOk

Fig. 7. Simulation results for case 1 (U, = 50 V and P, = 500 W). (a) Input voltage U,,output Uoand line current 2 , . (b) Inductor current confined between the two references. (c) Input current harmonics spectrum.

(32)

Calculation of the Upper and Lower Reference Current sulk and &: For a given input power which is a function of a r e f l , after calculating the duty cycle a p k we can compute the upper and the lower current limits i u l k and i l l ( k + ~ ) .

In continuous inductor current mode

B. Duty Cycle Computation in the Buck Mode

T, = tcn - tan, and

t b n - tan=

asnTs

To achieve a sinusoidal input current under buck mode operation, the duty cycle aSn of switch SWS, referred to one switching period T, must be calculated so that the average value of the input current falls proportional to the instantaneous value of the input voltage as shown in Fig. 5(b) and (c). The average line current iiavn during the nth switching period is given by (33)

where T, is the constant switching period in buck mode (Fig. 5(b) and (c)). For tan = 0, (33) can be rewritten as

(34)

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IEEE TRANSACTIONS ON INDUSTNAL ELECTRONICS, VOL. 43, NO.3, JUNE 1996

Then, the duty cycle a,, is found by solving (39)

t . . .. . . . .. ' . ... . . .. . l . .. \ \ ..5i, . : :/:1 . .

-200
0

0.004

0.008 0.012 0.016 (40) The a,, should be in the range of 0 to 1: 0 5 a,, 5 1. Calculation of the Upper and Lower Reference Current iUzn and i1zn: For a given input power which is function of irefl and after calculating the duty cycle a,,, we can compute the upper and lower current limit iuzn and i l z , (Fig. 5(b) and (c)). Fig. 6 shows the typical waveforms of the two reference currents iuzn and 212, for two experimental cases. With the value of a,, calculated from (40), the references current i U 2 , and i12, can be obtained from the following equation (see Fig. 5(b) and (c))

.
- ,-.~

.
.
~

.
-I
~

.
-

[A]

4.5 I 4 ....,....
.

,
........
........

and
L 2 n

....,.........,.....

............................

2 .
P'kefln - z/Zn

......................
.........
- 1 . .

iz2n = iu2n - a i ,
using (13),

Qsn

(42)
(43)

.,. . . - 1 . .

............................
.

....,.

........................
I . .

a i , = (1 - a,,)T,
-Hz

-.

VC

..........

.......:.

.........

(44)

............................

0 1

Equation (44) represents the variable current hysteresis for the buck mode operation.

m. IMPLEMENTATION OF THE CONTROL

STRATEGY w TESTCONVERTER

At each switching period, the duty cycle is calculated in order to obtain

iiavn = irefl sinwtlt=t,, .

(35)

The maximum value of UPF operation by

;refl can

be obtained assuming an

To illustrate the control strategy presented in the previous section, the design procedures of a sample converter are detailed for two loading conditions. The purpose of having two sets of dc load voltages is to show the validity of the control law over a wide range of output voltages at a fixed load power. e Case 1: U, = 50 V; I , = 10 A; input voltage = 120

V(rms).

By combining (35) and (36) we can calculate iiavn. (37) Substitution of (37) into (34) yields

U, = 100 V; I, = 5 A; input voltage = 120 V(rms). Simulation Studies: As shown in the analysis, the converter is assumed to operate with ideal circuit elements and switches. Simulation studies based on MATLAB software were used to select the proper hysteresis levels and the switching device ratings. The state (6), (7), (15), and (16) which describe all the operating sequences of the converter are solved using RungeKutta algorithm. In order to ensure the proper transition of the operating modes, the initial condition of state variables at
e

Case 2:

GHANEM et al. : A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT

447

m1.1

chi
m1.l
ch4

ch4 chl

ch4

mt.i,

100% 3 1.8% \ 10% I 3.1% 0.3%

(C)

(d)
U,,output

Fig. 9. Experimental results for case l(Uo = 50 V and Po = 500 W). (a) Input voltage U,, output U , and line current i,. (b) Input voltage and filtered input current 2 , . (c) Inductor current confined between the two references. (d) Input current harmonics spectrum.

U,

the beginning of each sequence are computed from the final conditions of the state variables of the previous one. Solving (42) and (43), the maximum values of the inductor current obtained by simulation (Fig. 6(a) and (b)) are
iuZmax = 21.7 A

for U, = 50 V for U, = 100 V

and
iuZmax = 12 A

The peak value of the average input current obtained by (36) is irefl = 5.88 A. The voltage and current limit of switch SWP are 170 V and 3.45 A. The voltage and current limit for SWS are 170 V, 21 A. The output voltage ripple is at a frequency of 120 Hz, and the dc current through the resistive load is equal to Solving (10) for C gives

%.

C = i,-

dt

dv,

= i-

at
AV

for AV = 4%, V d = 100 V, I, = 5 A.

C = 10000 pF

function of the ac input voltage ui for both cases and at constant power P, M P i , = 500 W. Fig. 2 shows the block diagram of the controller used for test. The zero crossing signal from the line generates a reset signal to the digital counter (used for EPROMs) in each half cycle. The EPROMs have 256 kbytes of memory. Reference waveforms irefl (in boost mode), and iren (in buck mode) are stored in EPROM-1 (upper limits) and in EPROM-2 (lower limits). These waveforms are amplified and compared with current measured to determine the duty cycle in the boost and buck modes. The first and the second comparator with dual-J-K Flip-Flop are used to determine the duty cycle a p k and asn for switches SWP and SWS. The third comparator is used to select the operating mode. An output control loop is added to regulate the output voltage U,, the reference current magnitude is adjusted every line half cycle as a function of the error between the desired and the measured output voltage. The control law which imposes such a change in ireflis given by
;ref

(new) = $ref (old)

k p (Uoref

- vc)

(45)

and the inductor size is established by series of simulations which yields a value of 0.2 mH. Prototype Studies: A laboratory prototype was built with IGBT switches, and ultra fast recovery diodes. The performance characteristics of the converter were measured as

where kp is a positive design constant. Comparison of Simulation and Experimental Results: Figs. 7 and 8 show simulation results of two cases of operation of the buck-boost converter. Figs. 7(a) and 8(a) show the input

448

LEEE TRANSACTIONS ON INDUSTFUAL ELECTRONICS, VOL. 43, NO. 3, JUNE 1996

mf.1 m2.4
ch 1

m1.1

chl
ch4

m1.4

ml.1,

100% 31.6%

10% 3.1%

Fig. 10. Experimental results for case 2 (U, = 100 V and Po = 500 W). (a) hput voltage U ; , output U, and line current 2;. (b) Input voltage U, and filtered input current 2;. (c) Inductor current confined between the two references. (d) Input current harmonics spectrum.

U;,

output

current, the input voltage, and the output voltage waveforms of the proposed topology for case 1 and case 2, respectively. The calculated displacement factor was 0.9986 for case 1 and 0.999 for case 2. The continuous inductor current ZL confined between the two references irefl (Zul and ill) and irea(iu2 and i l z ) , are shown in Figs. 7(b) and 8(b), respectively, for case 1 and case 2. Figs. 7(c) and 8(c) show the input current harmonic spectrum for case 1 and case 2. The calculated distortion factor was 0.9998 for two cases 1 and 2. The THD of the current was found to be 0.02 for both the cases. The input power factor was 0.9984 for case 1 and 0.9988 for case 2. The experimental results shown in Figs. 9 and 10 confirm the theoretical analysis. It is to be noted that the converter presents boost and buck operation. Fig. 9(a) shows the input voltage, output voltage and the input current waveforms of the proposed topology in case 1. Fig. 9(b) shows the filtered input current and the input voltage waveforms of the proposed topology in case 1. The input-side filter consists of a series source inductance which equal to 2.1 mH and shunt capacitor of 0.47 pF (Fig. l(c)). The line current is nearly sinusoidal, and the measured displacement factor was 0.9991. Fig. 9(c) shows the inductor current confined between the two references and ires (Zu2 and i l 2 ) for case 1. Fig. 9(d) shows the input current harmonic spectrum for case 1. The third, fifth, seventh, ninth, and other harmonics are less than 3% of the fundamental and the rms value of the

harmonic components (up to 23rd) is 4.9% of the fundamental, the Distortion Factor is equal to 0.9988 and hence the THD of the input current is 4.9%. Fig. 10(a) shows the input voltage, output voltage and the input current waveforms of the proposed topology in case 2. Fig. lO(b) shows the filtered input current and the input voltage waveforms of the proposed topology in case 2. The line current is sinusoidal, and the measured displacement factor was 0.999. Fig. lO(c) shows the inductor current confined between the two references z,,fl and i , ~ and iz2 for case 2. Fig. lO(d) shows the input current harmonic spectrum for case 2. The third, fifth, seventh, ninth, and other harmonics are less than 2.6% of the fundamental and the rms value of the harmonic components (up to 61st) is 4.0% of the fundamental, the Distortion Factor is equal to 0.9992 and hence the THD of the input current was 4.0%. A comparison of the results obtained for two output voltage levels of the proposed buck-boost converter shows that the power factor obtained is as good as that possible with a boost converter. Moreover, the buck mode has near unity power factor under all load conditions. The output dc voltage of the proposed circuit can be varied in a broad range maintaining the unity power factor operation. V. CONCLUSION This paper proposes a new cascade buck-boost topology that offers a high degree of power factor correction. Using a

GHANEM er al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT

449

simple control strategy, elimination of lower-order harmonic in the input current is achieved and the input power factor is improved to over 0.99, at power levels of 500 W, in typical application. In this strategy both buck and boost mode of operation are used in each ac half cycle to achieve an output dc voltage of desired level. A broad range of output voltage and output power are obtained with unity power factor. The analysis performed and the design equations presented enable the design to be adapted to a wide range of output power. The effect of the cascade buck-boost inductance and current ripple on the size and efficiency of converter power stage have been taken into consideration [l]. Due to the source impedance and the EM1 filter, the harmonic interference on adjacent communication systems is expected to be negligible.

Mohamed C. Ghanem received the diploma in

electrical engineering from Ecole Polytechnique dAlger, Algeria, in 1986, and the M.Sc. degree in industrial electronics from University of Quebec in Trois-Rivikres, Canada, in 1990. He is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering at &ole Polytechnique, Montreal University, Canada. His areas of interest include modeling and control of switching converter, power factor correction and new circuit configuration of soft switching converters.

REFERENCES [l] R. Ridley et al., Analysis and design of a wide input range power factor correction circuit for three-phase application, in APEC 8th, 1993, pp. 299-305. [2] C. Zhou, R. B. Ridley, and F. C. Lee, Design and analysis of a hysteretic boost power factor correction circuit, in IEEE PESC, Aug. 1990, pp. 800-807. [3] D. M. Divan, G. Venkataramanan, and C. Chen, A unity power factor forward converter, in IAS, IEEE, Westin Galleria, Houston, TX, Oct. 4 9 , 1992, pp. 666672. [4] B. Andreycak, Active power factor correction using zero current and zero voltage switching techniques, in HFPC, Proc., June 1991, pp. 46-60. [5] K. K. Sen et al., Unity power factor single phase power conditioning, in IEEE PESC, June 1987 [6] I. Takahashi et al., High power factor switching regulator with no rush current, in IEEE IAS, Jan. 1992, pp. 673-680. [7] M. S. Elmore et al., A power factor enhancement circuit, in IEEE APEC, June 1991, pp. 407-414. [8] G. Rim and R. Krishnan, AC to DC power converter with unity power factor and sinusoidal input current, in IEEE APEC, June 1991, pp. 400406. [9] L. Dixon, High power factor preregulators for off-line power supplies, unitrode switching regulated power supply design, Sem. Man., SEM700, 1990. [lo] C. Silva, Power factor correction with the UC3854, Application Note, Unitrode Integrated Circuits. [ l l ] C. A. Canesin and I. Barbi, A unity power factor multiple isolated outputs switching mode power supply using a single switch, in IEEE APEC, June 1991, pp. 430436. [12] M. Kazerani, P. D. Ziogas, and G . Joos, A novel active current waveshaping technique for solid-state input power factor conditioners, IEEE Trans Ind. Electron., vol. 38, no. 1, Feb. 1991. [13] M. Albach, Conducted interference voltage of AC-DC converter, in IEEE, PESC, June 1986, pp. 203-212.

Kamal AI-Haddad (S82-M88-SM92) was bom in Beirut, Lebanon, in 1954. He received the B.Sc.A. and the M.Sc.A. degrees from the UniversitC du QuCbec 2 Trois-Rivikres, Canada, and the Ph.D. degree from the Institut National Polytechnique, Toulouse, France, in 1982, 1984, and 1988, respectively. From June 1987 to June 1990, he was a professor at the Engineering Department, UniversitC du QuBbec, Trois-Rivitres. In June 1990, he joined the teaching staff as a professor of the Electrical Engineering Department of the Ecole de Technologie SupCrieure (UniversitC du Quebec) in Montreal, Canada. His fields of interest are static power converters, harmonics and reactive power control, switch mode and resonant converters, including the modeling, control, and development of industrial prototypes for various applications. Dr. Al-Haddad is a member of the Order of Engineering of Quebec and the Canadian Institute of Engineers.

Gilles Roy (S70-M75) was bom in Quebec, PQ, Canada, on August 1, 1947. He received the B.E. degree in electrical engineering and the M.Eng. degree from Ecole Polytechnique de Montreal, Montreal, PQ, Canada, in 1971 and 1975, respectively. From 1971 to 1978, he was a consulting engineer for the Montreal Transit Office, Metro Department, working on different projects relative to the subway transit system. He developed an inboard pressure monitoring system for the rubber tire wheels subway car; he took also an active part in settling the specifications for the power electronic apparatus of the regenerative chopper driven subway, in operation since 1976. In 1979, he became assistant professor at Ecole Polytechnique where he developed a program in power electronics for both undergraduate and graduate students. He also established a research laboratory in industrial electronics focusing on static converters, simulation models for industrial drives and instrumentation for power electronics. His research activities deal with direct frequency changers, application of fiber optics in power electronic control and development of software tools for drives applications. He currently works at Ecole Polytechnique as a professor in the department of electrical and computer engineering.