SSM6679GM

P-CHANNEL ENHANCEMENT MODE POWER MOSFET

PRODUCT SUMMARY
D D D D G

Simple Drive Requirement Low On-resistance Fast Switching Characteristic

BVDSS RDS(ON) ID

-30V 9m -14A

SO-8

S S

DESCRIPTION
The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters.

G S

Pb-free; RoHS-compliant

ABSOLUTE MAXIMUM RATINGS

Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current
1 3 3

Rating -30 25 -14 -8.9 -50 2.5 0.02 -55 to 150 -55 to 150

Units V V A A A W W/

Continuous Drain Current Total Power Dissipation Linear Derating Factor

Storage Temperature Range Operating Junction Temperature Range

THERMAL DATA
Symbol Rthj-a Parameter Thermal Resistance Junction-ambient
3

Value Max. 50

Unit /W

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SSM6679GM

ELECTRICAL CHARACTERISTICS
(TJ=25 C unless otherwise specified)
Symbol BVDSS
BVDSS/Tj
o

Parameter Drain-Source Breakdown Voltage

Test Conditions VGS=0V, ID=-250uA

Min. -30 -1 -

Typ. -0.03 26 37 3 25 13 11 58 43 950 640

Max. Units 9 13 -3 -1 -25 100 60 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF

Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA

RDS(ON)

Static Drain-Source On-Resistance2

VGS=-10V, ID=-14A VGS=-4.5V, ID=-11A

VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss

Gate Threshold Voltage Forward Transconductance

Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C)
o o

VDS=VGS, ID=-250uA VDS=-10V, ID=-14A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 25V ID=-14A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3,VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz

Gate-Source Leakage Total Gate Charge

2

Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
2

2860 4580

SOURCE-DRAIN DIODE
Symbol VSD Parameter Forward On Voltage
2 2

Test Conditions IS=-2A, VGS=0V IS=-14A, VGS=0V, dI/dt=100A/s

Min. -

Typ. 48 46

Max. Units -1.2 V ns nC

trr
Qrr

Reverse Recovery Time

Reverse Recovery Charge

Notes:
1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 125 /W when mounted on Min. copper pad.

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SSM6679GM
280 150

T A = 25 C
240

-10V -7.0V -ID , Drain Current (A)

T A = 150 o C

-10V -7.0V -5.0V -4.5V

-ID , Drain Current (A)

200

100

160

-5.0V -4.5V

120

50

80

V G = -3.0 V

V G = -3.0 V
40

0 0 1 2 3 4 5

0 0 1 2 3 4 5 6

-V DS , Drain-to-Source Voltage (V)

-V DS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

14

1.8

I D = -11 A T A =25
12

1.6

I D = -14 A V G =-10V

Normalized R DS(ON)

1.4

RDS(ON) (m)

10

1.2

1.0

0.8

0.6 3 5 7 9 11 -50 0 50 100 150

-V GS , Gate-to-Source Voltage (V)

T j , Junction Temperature ( o C)

Fig 3. On-Resistance v.s. Gate Voltage

Fig 4. Normalized On-Resistance v.s. Junction Temperature

3

14

12

10

T j =150 o C

T j =25 o C

-VGS(th) (V)
1 0 -50

-IS(A)

0.2

0.4

0.6

0.8

1.2

1.4

50

100

150

-V SD , Source-to-Drain Voltage (V)

T j , Junction Temperature ( o C)

Fig 5. Forward Characteristic of

Reverse Diode
08/10/2007 Rev.1.00

Fig 6. Gate Threshold Voltage v.s. Junction Temperature

3

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SSM6679GM
f=1.0MHz
12 10000

-VGS , Gate to Source Voltage (V)

10

I D = - 14 A V DS = -24V
Ciss

C (pF)

1000

Coss Crss

0 0 20 40 60 80

100 1 5 9 13 17 21 25 29

Q G , Total Gate Charge (nC)

-V DS , Drain-to-Source Voltage (V)

Fig 9. Gate Charge Characteristics

Fig 10. Typical Capacitance Characteristics

100

1ms
10

Normalized Thermal Response (Rthja)

Duty factor=0.5

0.2

0.1

0.1

10ms -ID (A)

1

0.05

100ms 1s
0.1

0.02

PDM
0.01

0.01
Single Pulse

t T
Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W

T A =25 C Single Pulse

0.01

DC

0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000

-V DS , Drain-to-Source Voltage (V)

t , Pulse Width (s)

Fig 7. Maximum Safe Operating Area

Fig 8. Effective Transient Thermal Impedance

VDS 90%

VG QG -4.5V QGS QGD

10% VGS td(on) tr td(off) tf Charge Q

Fig 11. Switching Time Waveform

08/10/2007 Rev.1.00

Fig 12. Gate Charge Waveform

4

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SSM6679GM

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.

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