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Topic: Introduction to Microelectronics I.

History of Microelectronics 1930s Lilienfield and Hell discussed the predecessor to what is now called the FET. Technological challenges delayed the practical utilization of this device. 1947-1948 Brattain, Bardeen, and Shockley from Bell Labs introduced the BJT. This development marked the practical beginning of the microelectronics industry. BJTs replaced vacuum tubes in many applications and provided the impetus for a host of new electronics system. A large number of BJTs were produced and applied in a wide range of systems. 1958 An engineer at Texas Instrument named Jack Kilby invented the first integrated circuit. 1959 Robert Noyce from Fairchild independently reported on a procedure that more closely resemble ICs today. The specific details of Kilbys circuit are inconsequential but the impact of his approach has been phenomenal. Their (Kilby and Noyce) works marked the beginning of what has become the field of VLSI design. II. Base Materials Germanium was widely used as a semiconductor in some of the early discrete devices. Silicon has been the dominant semiconductor material for the past two decades and most experts agree that it will remain dominant for the next decades. Since 25% of the Earths crust is made of silicon, a real silicon shortage is highly unlikely. Other materials such as GaAs are gaining acceptance in the markets.

III. Discrete Fabrication The first step in fabrication is gathering of semiconductor materials such as Germanium and Silicon. These raw materials are first subjected to a series of chemical reaction and zone refining process to form a polycrystalline crystal of the desired purity level. A. Zone Refining Process It consists of a graphite or quartz boat for minimum contamination, a quartz container and a set of RF (radio frequency) inducting coils. Either coils or boat must be movable along the length of the quartz container which produces the same effect. The moving coil approach is more popular.

B. Czochralski Technique The next step in IC fabrication sequence is the formation of single crystal of a germanium or silicon performed by the Czochralski technique. In this technique the seed of the desired impurity level is immersed in the molten silicon and gradually withdrawn while the shaft holding the seed is slowly turning. As the seed is withdrawn, a single crystal silicon lattice structure will grow on the seed as demonstrated by the neck. C. Discrete Diode Fabrication There are four methods presently used in discrete diode fabrication: 1. Grown Junction - Formed during the Czochralski crystal pulling process. Impurities of P and N type material can alternately be added to the molten semiconductor material in the crucible. Then large area can be cut into large number. 2. Alloy A process that will result in a junction type semiconductor diode that will have a high current and large PIV rating. Junction capacitance is also large, due to large junction area. In this process heat is applied until liquefaction occurs where the two materials meet. An alloy result when cooled. 3. Diffusion A process requiring more time than the alloy process but it is relatively inexpensive and can be very accurately controlled. It is a process by which heavy concentration of particles will diffuse into a surrounding region of lesser concentration. This type of method may either employ solid or gaseous diffusion. 4. Epitaxial Growth Came from the Greek terms epi meaning upon and taxis meaning arrangement. It gives manufacturer definite design advantage p and n type material as arranged and diffusion process is used. D. Transistor Fabrication Method used in transistor fabrication are simply extension of the methods used in semiconductor diodes. 1. Grown Junction - Czochralski technique is used to form the two pn junction of a transistor. The process requires that the impurity control and withdrawal rate be such as to ensure the proper base width and doping levels of the n type and p type materials. 2. Alloy Junction It is an extension of the alloy method, two dots of the same impurity are deposited on each side of the semiconductor wafer. The entire structure is heated until melting occurs and each dot is alloyed to the base wafer resulting in the pn junction. 3. Diffusion the most frequently employed method of manufacturing transistor today. It permits very tight control of the doping levels and thickness of various regions.

IV. Integrated Circuit Fabrication Tools ICs today contain very large number of transistors. Conventional methods of circuit design that involved iteration at the breadboard level proved impractical for designing ICs. This is due to poor designer productivity and the high cost of fabricating ICs. Requirements Methods of efficiently handling large quantities of design data. Models of transistors that accurately predict experimental performance. Methods of increasing designer productivity and reducing design cycle time as the size and complexity of circuits are increased. Powerful and dynamic tools for the IC designer. Large computers or powerful graphics-intense workstations. Investment in both hardware and software. As powerful and dynamic as these tools may be, the fierce competition in the market place has resulted in the evolution of user friendly software. Jargons Integrated Circuit is a combination of interconnected circuit elements inseparably associated on or within a continuous substrate. Substrate is the supporting material upon or within which an IC is fabricated or to which an IC is attached. Wafer (or Slice) Basic physical unit used in processing. It generally contains a large number of identical ICs. Typical wafer is circular; production wafers have diameters of 4, 5, or 6 inches. Chip One of the repeated ICs on a wafer. A typical wafer may contain as few as 20 or 30 ICs or as many as several hundred or even several thousands depending on the complexity and size of the circuit being fabricated. Terms Die and Bar are used interchangeably in some companies. Test Plug (Process Control Bar/Monitor) Is a special chip that is repeated only a few times on each wafer. It is used to monitor the process parameters of the technology. After processing, the validity of the process is verified by measuring, at the wafer probe level, the characteristics of the devices and/or circuits or the test plug. If the test plug levels are not acceptable, the wafer is discarded.

Test Cell (Test Lead) Is a special chip repeated a few times on each wafer. It differs from the test plug in that the circuit designer includes this cell specifically to monitor the performance of elementary sub circuits or subcomponents.

V. Types of Integrated Circuits The most noticeable characteristic of an IC is its size. Built in a manner like the discrete components. The disadvantage of using an IC is when a single component within an IC fails; the entire structure is replaced. A. Monolithic IC It came form the Greek words monos meaning single and lithos meaning stone. Thus, it means single stone or single solid structure. It is constructed within a single wafer of semiconductor material. Wafers are 1/1000 inch obtained through a slicing process. Mask a selective diffusion required in the formation of the various active and passive elements of an IC. Photolithographic process selective etching of the SiO2 layer is accomplished through the use of this process. The wafer is first coated with a thin layer of photosensitive material, called photoresist. It uses ultraviolet light that can not penetrate the masking pattern. B. Thick and Thin Film It is not formed within a semiconductor wafer but on the surface of an insulating substrate such as glass or an appropriate ceramic material. Passive elements are used in thick and thin film. Active elements are added as discrete elements. The only difference between thin and thick film is the method employed for its formation. The thin film uses evaporation or cathode sputtering technique, while the thick film employs the silk screen technique. C. Hybrid IC Hybrid IC is simply the combination of both monolithic and thick/thin film integrated circuit.

VI. Goals of IC Design Manufacturing of Semiconductor and/or IC has its emphasis on the following: 1. The goal of the IC designer is to design an IC that meets a given set of specifications while expending minimal labor (expanding the automation level, meaning less hand on requirements) and physical resources in a short time frame. 2. High yield rate. (Increase number of good elements in a batch) Yield a. Percentage of dies that meet performance specifications. b. In general, yield decreases with increasing die area. c. Yield is dependent on the type of circuit, design methodology, layout and the physical fabrication process. Factors Affecting Yield a. Dust particles. b. Crystal defects c. Mark defects d. Alignment errors e. Breakage and human handling errors f. Parameter drift 3. Simple production process. 4. Small die area. 5. Increasing the density level. VII. Two Approaches in IC Design 1. Bottom-Up The designer starts at the transistor or gate level and designs sub circuits of increasing complexity which are then interconnected to realize the required functionality. 2. Top-Down The designer repeatedly decomposes system-level specifications into groups and subgroups of simpler tasks. VIII. Wafer-Scale Integration

Considerable effort has been expended toward using the entire wafer as a single IC, but this approach is challenged by defects in processing and the associated decline in yield and by the inherent delay in signals that must traverse the wafer. Size and Complexity of ICs ICs are usually classified in terms of the number of devices or potential devices used in the design of the circuit and in terms of the feature size of the process. The device count is generally restricted to the number of active devices (either FETs or BJTs).

Small Scale Integration (SSI) Year: 1961 Active Device Count: 1 100 Typical Functions: gates, op-amps, many linear circuits Medium Scale Integration (MSI) Year: 1967 Active Device Count: 100 1,000 Typical Functions: registers, filters Large Scale Integration (LSI) Year: 1972 Active Device Count: 1,000 100,000 Typical Functions: microprocessors, ADCs, DACs Very Large Scale Integration (VLSI) Year: 1977 Active Device Count: 105 106 Typical Functions: memories, signal processors Ultra Large Scale Integration (ULSI) Year: 1985 Active Device Count: > 106 Typical Functions: special processors, real-time image processors Feature Size
Specifications Preliminary Stage Computer Simulation

Acceptable? Computer Simulation Acceptable? Initial Production Test and Evaluation Acceptable? Production Layout

Period early to mid-1970s late-1970s to early-1980s Mid-1980s Early-1990s

Minimum Feature Size 7 to 10 5 2, 1.25, 1 0.75 to 0.25

Benefits in Reducing Feature Size Speed Increase the speed of the circuit increases linearly (approximate) with feature size reduction. Yield Increase the yield increase is a function of the active silicon area.

Disadvantages of Reducing Feature Size Deteriorating of matching characteristics. Increase cost of equipment required for processing. Additional capability requirements for the software design aids. Increased power dissipation density Examples T.I. 1M DRAM Die Size: 0.54 cm2 Minimum Feature Size: 1 Number of transistors: 1,048,576 transistors in the basic memory array (together with an equal amount of capacitors) along with 52,000 transistors in the control unit. T.I. 16M DRAM Die Size: 1 cm2 Minimum Feature Size: 0.6 Number of transistors: 16,770,000 transistors in the basic memory array (together with an equal amount of capacitors) along with 150,000 transistors in the control unit. Advantages of Using a Smaller Die Size Results in more chips per wafer, thus a reduction in the effective cost per chip. Yield decreases rapidly with increasing chip size. Since rectangular chips are fabricated on round wafers, the amount of space wasted around the periphery is reduced with smaller chips.