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Outline
In-depth discussion of CMOS logic families
Static and Dynamic Dynamic circuits Domino loigc Np Np- logic TspcTspc -logic NoraNora -logic Area, Speed, Energy or Robustness
Dynamic logic
Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of N requires 2N devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires only N + 2 transistors takes a sequence of precharge and conditional evaluation phases to realize logic functions
Nitin Chaturvedi
Dynamic logic
Dynamic Gate
CLK In1 In2 In3 CLK
Mp
CLK Out CL
Mp
on off
1 Out !((A&B)|C) C
PDN
A B
Me
CLK
Me
off on
Dynamic logic
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in high impedance state during and after evaluation (PDN off), state is stored on CL
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails
Nitin Chaturvedi
Dynamic logic
Full swing outputs (VOL = GND and VOH = VDD) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) Low noise margin (NML)
PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
Nitin Chaturvedi
Dynamic logic
Nitin Chaturvedi
Dynamic logic
However overall power dissipation is usually higher than static CMOS due to
higher transition probabilities extra load on CLK
Nitin Chaturvedi
Dynamic logic
Dynamic Behavior
CLK Out In1 In2 In3 In4 CLK
0.5 1.5 2.5
Evaluate
In & CLK
Out
Precharge
-0.5 0 0.5 1
#Trs 6
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VOH 2.5V
VOL 0V
VM VTn
NMH 2.5-VTn
Dynamic logic
The duration of the precharge cycle can be adjusted by changing the size of the PMOS precharge transistor. But making it too large increases the gates Cint as well as increasing the capacitive load on the clock.
Nitin Chaturvedi
Dynamic logic
CLK
Vout (VG=0.45 45) )
Voltage (V)
1.5
Vout (VG=0.5)
0.5
-0.5 0 20 40 60 80 100
Time (ns)
Nitin Chaturvedi
Dynamic logic
Out CL PDN
Eliminates Static power Consumption
Me
Dynamic logic
Assume signal probabilities PA=1 = 1/2 PB=1 = 1/2 Then transition probability P01 = Pout=0 x Pout=1 = 3/4 x 1 = 3/4
Dynamic logic
Charge Leakage
CLK
Mp
Out
1
A= A=0 0
2
CL
Me
CLK
VOut Precharge
Evaluate
Leakage sources
Dynamic logic
Dynamic logic
Out
1.5 0.5 -0.5 0 20 40
Time (ms)
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Dynamic logic
If PDN is on, there is a fight between the PDN and the PUN - circuit must be ratioed so that PDN wins, eventually
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Dynamic logic
Charge Sharing
Out CL Ca Cb
Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.
When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.
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Dynamic logic
Load inverter
a
Ca=15 15fF fF B
Cy=50 50fF fF
!B !C
b
B C !B
Cb=15 15fF fF
Cc=15 15fF fF
Cd=10fF Vout = - VDD [(Ca + Cc)/((Ca + Cc) + Cy)] = - 2.5V*( V*(30 30/( /(30 30+ +50 50)) )) = -0.94 94V V
CLK
Nitin Chaturvedi
Dynamic logic
V = -0.94 V so the output drops to 2.5 - 0.94 = 1.56 V which is below the switching threshold of the Load inverter.
Nitin Chaturvedi
Dynamic logic
CLK Out
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
Nitin Chaturvedi
Dynamic logic
Backgate Coupling
Susceptible to crosstalk due to 1) high impedance of the output node and 2) capacitive coupling
CLK
Mp M1 M2 Me
Out1 Out 1 =1 C L1
M6 M5
C L2 In
Static NAND
Dynamic NAND
Out2 capacitively couples with Out Out2 Out1 1 through the gate-source and gate-drain capacitances of M4
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Dynamic logic
Out1
1
CLK
In
0 2
Out2
-1 4 6
Time (ns)
Nitin Chaturvedi
Dynamic logic
Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage is reduced. Out1 overshoots VDD (2.5V) due to clock feedthrough
Nitin Chaturvedi
Dynamic logic
Clock Feedthrough
A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node
CLK
A B
Mp
Out CL
CLK
Me
Coupling between Out and CLK input of the precharge device due to the gate- drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
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Dynamic logic
0.5
Clock feedthrough
Time (ns)
Signal levels can rise enough above VDD that the normally reversereversebiased junction diodes become forwardforward-biased causing electrons to be injected into the substrate.
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Dynamic logic
CLK
Out1
Out2 Out 2
In
CLK
Me CLK Me
In
Out1 Out 1
VTn V t
Out2 Out 2
Only a single 0 1 transition allowed at the inputs during the evaluation period!
Nitin Chaturvedi
Dynamic logic
Domino Logic
CLK In1 In2 In3 CLK
Mp
11 10
CLK
Out1 Out 1
00 01
PDN
In2 In3
PDN
Me
CLK
Me
Dynamic logic
Why Domino?
CLK
PDN
Ini Inj
PDN
Ini Inj
PDN
Ini Inj
PDN
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Dynamic logic
P0
P1 3
P2 2
P3 1
3 Ci, i,4 4 1 2
Ci,0
CLK
4 5 G0 6
4 G1 5
3 G2 4
2 G3 3
Dynamic logic
Domino Comparator
CLK A3 A2 A1 A0
Out
B3
B2
B1
B0
Dont need isolation NMOS in the pullpull-down, since the PDN is forced off during precharge.
Nitin Chaturvedi
Dynamic logic
Dynamic logic
on
Mkp Mp
CLK
1
!B
0 !Out = !(AB)
AND/NAND Due to its highhigh-performance, differential domino is very popular and is used in several commercial microprocessors!
Nitin Chaturvedi
Dynamic logic
Nitin Chaturvedi
Dynamic logic
npnp-CMOS (Zipper)
CLK In1 In2 In3 CLK
Mp 11 10
!CLK
Out1 Out 1
Me
PDN
PUN
00 01
Me
Mp
Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN
Nitin Chaturvedi
Dynamic logic
!CLK
Out1
Me
PDN
PUN
00 01
Me
Mp
to other PUNs
Dynamic logic
Increase complexity
Have two clock signals to generate and route - CLK and !CLK
Nitin Chaturvedi
Dynamic logic
1x
Sum1
!A1
!B1
!B1
!CLK
CLK
0x
1 x !C1
A0 B0 CLK B0
A0
B0
1x
C0
A0 C0
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B0 A0 C0
!CLK
Dynamic logic
0x
!Sum0
Example
Multiple precharge trans.
# Trans 8 12 + 2 6+2 10
Ease 1 2 4 3
Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.
Nitin Chaturvedi
Dynamic logic