Lecture 020 Submicron CMOS Technology (3/24/10)

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LECTURE 020 - SUBMICRON CMOS TECHNOLOGY

LECTURE ORGANIZATION Outline CMOS Technology Fundamental IC Process Steps Typical Submicron CMOS Fabrication Process Summary CMOS Analog Circuit Design, 2nd Edition Reference Pages 18-29

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CMOS TECHNOLOGY
Classification of Silicon Technology
Silicon IC Technologies

Bipolar

Bipolar/CMOS

MOS

Junction Isolated

Dielectric Isolated

Oxide isolated

CMOS

PMOS (Aluminum Gate)

NMOS

060112-02

SiliconGermanium

Silicon

Aluminum gate

Silicon gate

Aluminum gate

Silicon gate

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Categorization of CMOS Technology Minimum feature size as a function of time:

1 Minimum Feature Size (m) Submicron Technology

Deep Submicron Technology 0.1 Ultra Deep Submicron Technology

0.01 1985

1990

1995

Year

2000

2005

070215-01

2010

Categories of CMOS technology: 1.) Submicron technology Lmin  0.35 microns 2.) Deep Submicron technology (DSM) 0.1 microns
Lmin
0.35 microns 3.) Ultra-Deep Submicron technology (UDSM) Lmin
0.1 microns
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Why CMOS Technology? Comparison of BJT and MOSFET technology from an analog viewpoint: Comparison Feature BJT MOSFET Cutoff Frequency(fT) 100 GHz 50 GHz (0.25m) Noise (thermal about the same) Less 1/f More 1/f DC Range of Operation 9 decades of exponential 2-3 decades of square law current versus vBE behavior Transconductance (Same current) Larger by 10X Smaller by 10X Small Signal Output Resistance Slightly larger Smaller for short channel Switch Implementation Poor Good Capacitor Voltage dependent More options Performance/Power Ratio High Low Technology Improvement Slower Faster Therefore, Almost every comparison favors the BJT, however a similar comparison made from a digital viewpoint would come up on the side of CMOS. Therefore, since large-volume mixed-mode technology will be driven by digital demands, CMOS is an obvious result as the technology of availability.
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How Does IC Technology Influence Analog IC Design? Characteristics of analog IC design: Continuous in signal amplitude Discrete or continuous in time Signal processing primarily depends on ratios of values and time constants - Ratios are generally resistance, conductance, or capacitance - Time constants are generally products of resistance and capacitance Dynamic range is determined by the largest and smallest signals Influence of IC Technology: Accuracy of signal processing depends on the accuracy of the ratios of values The dynamic range depends upon the linearity of the circuit elements and the noise The value of components is limited by area considerations IC technology introduces resistive, capacitive and inductive parasitics that cause deviation from desired behavior The analog circuit is subject to the influence of other circuits fabricated in the same substrate

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FUNDAMENTAL IC PROCESS STEPS

Basic Steps Oxide growth Thermal diffusion Ion implantation Deposition Etching Shallow trench isolation Epitaxy Photolithography Photolithography is the means by which the above steps are applied to selected areas of the silicon wafer. Silicon Wafer
125-200 mm (5"-8")

0.5-0.8mm

n-type: 3-5 -cm p-type: 14-16 -cm

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Fig. 2.1-1r
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Oxidation Description: Oxidation is the process by which a layer of silicon dioxide is grown on the surface of a silicon wafer.
Original silicon surface Silicon dioxide 0.44 tox tox

Silicon substrate
Fig. 2.1-2

Uses: Protect the underlying material from contamination Provide isolation between two layers. Very thin oxides (100 to 1000) are grown using dry oxidation techniques. Thicker oxides (>1000) are grown using wet oxidation techniques.
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Diffusion Diffusion is the movement of impurity atoms at the surface of the silicon into the bulk of the silicon. Always in the direction from higher concentration to lower concentration.
High Concentration Low Concentration
Fig. 150-04

Diffusion is typically done at high temperatures: 800 to 1400C

N0 N(x) NB t1 t2 t3 ERFC t1 < t2 < t3 Gaussian N0 N(x) NB t1 t2 t3 t1 < t2 < t3

Depth (x) Infinite source of impurities at the surface.

CMOS Analog Circuit Design

Depth (x) Finite source of impurities at the surface.

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Ion Implantation Ion implantation is the process by which impurity ions are accelerated to a high velocity and physically lodged into the target material.
Fixed Atom Annealing is required to activate the impurity atoms and repair the physical Impurity Atom damage to the crystal lattice. This step final resting place is done at 500 to 800C. Ion implantation is a lower temperature process compared to diffusion. N(x) Can implant through surface layers, thus it is useful for field-threshold adjustment. Can achieve unique doping profile such as buried concentration peak. NB

Path of impurity atom Fixed Atom

Fixed Atom
Fig. 150-06

Concentration peak

Depth (x)

Fig. 150-07

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Deposition Deposition is the means by which various materials are deposited on the silicon wafer. Examples: Silicon nitride (Si3N4) Silicon dioxide (SiO2) Aluminum Polysilicon There are various ways to deposit a material on a substrate: Chemical-vapor deposition (CVD) Low-pressure chemical-vapor deposition (LPCVD) Plasma-assisted chemical-vapor deposition (PECVD) Sputter deposition Material that is being deposited using these techniques covers the entire wafer and requires no mask.

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Etching Etching is the process of selectively Film removing a layer of material. Underlying layer When etching is performed, the etchant may (a) Portion of the top layer ready for etching. remove portions or all of: a Selectivity The desired material Mask The underlying layer c Film Anisotropy The masking layer b Selectivity Underlying layer Important considerations: (b) Horizontal etching and etching of underlying layer. Fig. 150-08 Anisotropy of the etch is defined as, A = 1-(lateral etch rate/vertical etch rate) Selectivity of the etch (film to mask and film to substrate) is defined as, film
etch
rate Sfilm-mask = mask
etch
rate A = 1 and Sfilm-mask =
are desired. There are basically two types of etches: Wet etch which uses chemicals Dry etch which uses chemically active ionized gases.
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Mask

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Epitaxy Epitaxial growth consists of the formation of a layer of single-crystal silicon on the surface of the silicon material so that the crystal structure of the silicon is continuous across the interfaces. It is done externally to the material as opposed to diffusion which is internal The epitaxial layer (epi) can be doped differently, even opposite to the material on which it is grown It is accomplished at high temperatures using a chemical reaction at the surface The epi layer can be any thickness, typically 1-20 microns
Gaseous cloud containing SiCL4 or SiH4
Si Si Si Si Si Si Si Si Si Si Si Si Si Si + Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si

+
Si

Si Si

Si Si Si Si

Si

+
Si

Si Si Si Si Si

Si Si Si Si Si Si

Si

+
Si

+
Si

- Si Si
Si Si

Si

Si

Si

Si

Si

Fig. 150-09

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Photolithography Components Photoresist material Mask Material to be patterned (e.g., oxide) Positive photoresist Areas exposed to UV light are soluble in the developer Negative photoresist Areas not exposed to UV light are soluble in the developer Steps 1. Apply photoresist 2. Soft bake (drives off solvents in the photoresist) 3. Expose the photoresist to UV light through a mask 4. Develop (remove unwanted photoresist using solvents) 5. Hard bake (
100C) 6. Remove photoresist (solvents)

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Illustration of Photolithography - Exposure The process of exposing Photomask selective areas to light through a photo-mask is called printing. Types of printing include: Contact printing Proximity printing UV Light Projection printing
Photomask

Photoresist Polysilicon
Fig. 150-10

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Illustration of Photolithography - Positive Photoresist

Develop Polysilicon Photoresist Photoresist Polysilicon Etch

Remove photoresist

Polysilicon

Fig. 150-11

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TYPICAL SUBMICRON CMOS FABRICATION PROCESS

N-Well CMOS Fabrication Major Steps 1.) Implant and diffuse the n-well 2.) Deposition of silicon nitride 3.) n-type field (channel stop) implant 4.) p-type field (channel stop) implant 5.) Grow a thick field oxide (FOX) 6.) Grow a thin oxide and deposit polysilicon 7.) Remove poly and form LDD spacers 8.) Implantation of NMOS S/D and n-material contacts 9.) Remove spacers and implant NMOS LDDs 10.) Repeat steps 8.) and 9.) for PMOS 11.) Anneal to activate the implanted ions 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) 13.) Open contacts, deposit first level metal and etch unwanted metal 14.) Deposit another interlayer dielectric (CVD SiO2), open vias, deposit 2nd level metal 15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads
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Major CMOS Process Steps

Step 1 - Implantation and diffusion of the n-wells n-well implant

Photoresist p- substrate

SiO2

Photoresist

Step 2 - Growth of thin oxide and deposition of silicon nitride Si3N4 SiO2 n-well p- substrate
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Major CMOS Process Steps Continued

Step 3.) Implantation of the n-type field channel stop n- field implant

Photoresist

Si3N4

Photoresist n-well

Pad oxide (SiO2)

p- substrate

Step 4.) Implantation of the p-type field channel stop p- field implant Si3N4

Photoresist n-well

p- substrate
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Major CMOS Process Steps Continued

Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon) Si3N4 FOX p- substrate
FOX

n-well

Step 6.) Growth of the gate thin oxide and deposition of polysilicon. The thresholds can be shifted by an implantation before the deposition of polysilicon. Polysilicon

FOX p- substrate

FOX

n-well

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Major CMOS Process Steps Continued

Step 7.) Removal of polysilicon and formation of the sidewall spacers Polysilicon FOX p- substrate SiO2 spacer Photoresist FOX n-well
FOX FOX

Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown) n+ S/D implant Polysilicon FOX p- substrate
070523-04

Photoresist FOX n-well

FOX FOX

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Major CMOS Process Steps - Continued

Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains n- S/D LDD implant Polysilicon FOX p- substrate Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown), remove the sidewall spacers and implant the PMOS lightly doped source/drains FOX Photoresist n-well
FOX FOX

Polysilicon FOX p- substrate

LDD Diffusion FOX n-well

070209-03
FOX FOX

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Major CMOS Process Steps Continued

Step 11.) Anneal to activate the implanted ions n+ Diffusion FOX p- substrate p+ Diffusion FOX n-well Polysilicon FOX

Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) n+ Diffusion FOX p- substrate p+ Diffusion FOX n-well Polysilicon BPSG FOX

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Major CMOS Process Steps - Continued

Step 13.) Open contacts, deposit first level metal and etch unwanted metal CVD oxide, Spin-on glass (SOG) Metal 1

FOX p- substrate

FOX n-well

BPSG FOX

Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts, deposit second level metal Metal 2 Metal 1

FOX p- substrate

FOX n-well

BPSG FOX

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Major CMOS Process Steps Continued

Step 15.) Etch unwanted metal and deposit a passivation layer and open over bonding pads Metal 2 Passivation protection layer Metal 1

FOX p- substrate

FOX n-well

BPSG FOX

070523-07

p-well process is similar but starts with a p-well implant rather than an n-well implant.

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Approximate Side View of CMOS Fabrication

Passivation

Metal 4 Metal 3

Metal 2 2 microns Metal 1 Polysilicon

Diffusion
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Planarization Planarization attempts to minimize the variation in surface height of the wafer. Planarization techniques Repeated applications of SOG Tungsten Plug Resist etch-back highest areas of oxide are exposed longest to the etchant and therefore erode away the most.

Influence of planarization on analog design: + Number of levels of metal and the metal integrity depends on planarization + Thin film components at the surface require good planarization + Without planarization, resistance of conductors increases + Planarization at the top level leads to less package induced stress (trimming?) + Planarized passivation helps printing when the depth of field is small. - With planarization, the capacitance of the interdielectric isolation can vary (a good reason to extract capacitance!) - Significant difference in contact aspect ratio (deep versus shallow contacts)
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Chemical Mechanical Polishing CMP produces the required degree of planarization for modern submicron technology.

Both chemical effect (slurry) and mechanical (pad pressure) take place. Although CMP is superior to SOG and resist etchback, large areas devoid of underlying metal or poly produce low regions in the final surface. Challenge: Achieve a highly planarized surface over a wide range of pattern density.

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Chemical Mechanical Polishing Continued Impact on analog design: + Makes the surface flatter - Vias and plugs can become longer adding resistance + More uniform surface giving better metal coverage and foundation for thin film components - Thickness varies with pattern density CMP Planarization
CMP Planarization

Pattern Fill
070810-01

Examples of pattern fill:

Layout with white space Horizontal Stripe Fill Vertical Stripe Fill

070810-02

Pattern density design rules are both local and global.

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Silicide/Salicide Technology Used to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of polysilicon Salicide technology (self-aligned silicide) provides low resistance source/drain connections as well as low-resistance polysilicon.
Polysilicide Metal Polysilicide Metal Salicide

FOX

FOX

FOX

FOX

Polycide structure

Salicide structure

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SUMMARY Fabrication is the means by which the circuit components, both active and passive, are built as an integrated circuit. Basic process steps include: 1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation 4.) Deposition 5.) Etching 6.) Epitaxy The complexity of a process can be measured in the terms of the number of masking steps or masks required to implement the process. Major CMOS Processing Steps: 1.) Well definition 2.) Definition of active areas and substrate/well contacts (SiNi3) 3.) Thick field oxide (FOX) 4.) Thin field oxide and polysilicon 5.) Diffusion of the source and drains (includes the LDD) 6.) Dielectric layer/Contacts (planarization) 7.) Metallization 8.) Dielectric layer/Vias

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