Tutorial Problems: Bipolar Junction Transistor (DC Analysis)

1. For the circuit shown in Figure 1, assume = 50, VBE(on) = 0.7 V and VCE(sat) = 0.2 V. Determine VO, IB, and IC for: (a) VI = 0.2 V, and (b) VI = 3.6 V. Then calculate the power dissipated in the transistor for the two conditions. (c) Determine VI such that VBC = 0. Calculate the power dissipated in the transistor under such condition.

Figure 1

Solution: (a) VI = 0.2 V: Since VI < VBE(on) the transistor is biased in the cut-off region. Therefore IB = IC = 0, VO = 5 V and the power dissipated in the transistor P = 0. (b) VI = 3.6 V: Assume that the transistor is initially biased in the forward-active region,

Therefore the initial assumption is incorrect. The transistor is actually biased in the saturation region. Hence:

(c) When VBC = 0,

This is the boundary condition between the transistors saturation and forward-active region. If VBC > 0 the base-collector junction will be forward-biased and the transistor will enter the saturation region. Conversely, if VBC < 0 the base-collector junction will be reversed biased and the transistor will enter the forward-active region. At the boundary condition, IC = IB is still valid, and the maximum VI which can be applied to the base before the transistor is biased into saturation can be found by:

2.

For the circuit shown in Figure 2, the measured value of VC is VC = +6.34 V. Determine IB, IE, IC, VCE, , and . Assume VBE(on) = 0.7 V.

Figure 2

Solution: Since VBC = VB VC = 6.34 V < 0, the transistor is biased in the forward-active mode. Other circuit parameters can be calculated as:

3.

Design the common-base circuit shown in Figure 3 such that IEQ = 0.50 mA and VECQ = 4.0 V. Assume transistor parameters of = 120 and VEB(on) = 0.7 V.

Figure 3

Solution: From Figure 3, the following equations can be written:

From (1):

From (2):

4.

Calculate the characteristics of an npn bipolar transistor circuit with a load resistance. The load resistance can represent a second transistor stage connected to the output of a transistor circuit. For the circuit shown in Figure 4, the transistor parameters are: VBE(on) = 0.7 V, and = 100.

Figure 4

Solution: The load circuit containing V+, RC and RL can be transformed into the Thevenin equivalent circuit with:

The simplified circuit becomes:

The collector and emitter current are:

The collector (or output) voltage VC (or VO) and the collector-emitter voltage VCE are:

From Figure 4, I1 and IL can be calculated as:

5.

The circuit shown in Figure 5 is to be designed such that ICQ = 0.8 mA and VCEQ = 2 V for the case when (a) RE = 0 and (b) RE = 1 k. Assume = 80 and VBE(on) = 0.7 V. The transistor in Figure 5 is replaced with one with a value of = 120 and = 150. Calculate the new Q-point values ICQ and VCEQ for each case. Which design (RE = 0 or RE = 1 k) shows a smaller change in Q-point values when changes? What can you conclude about the advantage of adding RE?

Figure 5

Solution: The circuit is to be designed with ICQ = 0.8 mA and VCEQ = 2 V. Let = 80 and RE = 0,

If RE = 1 k is present, RB and RC are re-calculated as:

RE = 0
(RB = 130 k , RC = 3.75 k )

RE = 1 k
(RB = 49 k , RC = 2.74 k )

= 80 = 120

ICQ = 0.8 mA VCEQ = 2.0 V ICQ = 1.2 mA VCEQ = 0.5 V ICQ = 1.5 mA VCEQ = 0.625 V
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ICQ = 0.8 mA VCEQ = 2.0 V ICQ = 0.92 mA VCEQ = 1.56 V ICQ = 0.98 mA VCEQ = 1.35 V

= 150

From the tabulated results, with the addition of the emitter resistor RE, the Q-point values become less sensitive to the variation in the current gain hence a more stable dc design is achievable. Referring to the circuit with RE,

Therefore if RE is chosen such that (1 + )RE is much larger than RB, e.g. (1 + )RE = 10RB, the quiescent collector current IC becomes a function of RE only and is not affected by the variation in . It is a common practice to add this resistor in practical circuit design. 6. The circuit shown in Figure 6 is to be designed such that ICQ = 0.5 mA and VCEQ = 2.5 V. Assume = 120 and VBE(on) = 0.7 V. Sketch the load line and mark the Q-point. If the resistor values vary by 10 %. Plot the load lines and mark the Q-point values for the maximum and minimum values of RB and RC (four Q-point values).

Figure 6

Solution: The circuit is to be designed with ICQ = 0.5 mA and VCEQ = 2.5 V. Let = 120,

Since both resistors have a tolerance of 10 %, the base resistor can vary between 928.8 k RB 1135.2 k and the collector resistor between 4.5 k RC 5.5 k. For extreme values of RB and RC, the Q-point values are computed as follows: RC = 4.5 k RB = 928.8 k ICQ = 0.556 mA VCEQ = 2.5 V ICQ = 0.455 mA VCEQ = 2.95 V RC = 5.5 k ICQ = 0.556 mA VCEQ = 1.94 V ICQ = 0.455 mA VCEQ = 2.5 V

RB = 1135.2 k

The load line equation is given by:

With 10 % tolerance of the resistance values of RB and RC, the resulting Q-point value (VCEQ, ICQ) will lie within the shaded region.

7.

Develop the voltage transfer curves (VO versus VI) for the amplifier circuits shown in Figure 7(a) and 7(b). Assume npn transistor parameters of VBE(on) = 0.7 V, = 120, and VCE(sat) = 0.2 V, and pnp transistor parameters of VEB(on) = 0.7 V, = 80, and VEC(sat) = 0.2 V. Amplifier circuits are often biased to give a maximum swing of input and output voltage. Mark this dc bias point (or Q-point) on the voltage transfer curves. What is the amplification factor (or voltage gain)?

Figure 7 Solution: (a) Given VBE(on) = 0.7 V, = 120, and VCE(sat) = 0.2 V for the npn transistor Qn, the voltage transfer characteristics of the amplifier circuit can be analyzed as follows: For 0 VI < 0.7 V, Qn is biased in the cut-off mode, so that IB, IC, and VO are given by:

For VI 0.7 V, Qn is turned on and initially biased in the forward-active mode. We have:

This equation for VO is valid for 0.2 VO 5 V. When VO = VCE(sat) = 0.2 V, the transistor Qn enters into saturation mode. The input voltage VI is found from:

Therefore, for VI 1.9 V, the output voltage remains constant at VCE(sat) = 0.2 V.
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The voltage transfer curve for the npn transistor amplifier circuit is plotted in the figure below. Maximum input and output swing can be achieved by designing the Q-point so that it lies at the middle of the forward-active region.

The amplification factor (or voltage gain) is given by the ratio between VO and VI within the forwardactive region.

(b) The analysis of the pnp transistor amplifier circuit is similar to part (a). Given VEB(on) = 0.7 V, = 80, and VEC(sat) = 0.2 V for the pnp transistor Qp, For VI > 4.3 V, Qp is biased in the cut-off mode, so that IB, IC, and VO are given by:

For VI 4.3 V, Qp is turned on and initially biased in the forward-active mode. We have:

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This equation for VO is valid for 0 VO 4.8 V. When VO = V+ VEC(sat) = 4.8 V, the transistor Qp enters into saturation mode. The input voltage VI is found from:

Therefore, for VI 2.8 V, the output voltage remains constant at VEC(sat) = 0.2 V. The voltage transfer characteristics for the pnp transistor amplifier circuit is plotted in the figure below. Maximum input and output swing can be achieved by designing the Q-point so that it lies at the middle of the forward-active region.

The amplification factor (or voltage gain) is given by the ratio between VO and VI within the forwardactive region.

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