Академический Документы
Профессиональный Документы
Культура Документы
Dr. A. Amalin Prince BITS Pilani K.K. Birla Goa Campus Department of Electrical , Electronics and Instrumentation Engineering
MEL G642
Contents
MAC fundamentals MAC implementations A MAC case study MAC integration
MEL G642
PM
DM1
DM2
AGU1
AGU2
MAC general
MEL G642
MAC instructions
Multiplication arithmetic's MAC & Iterative instructions Double-precision arithmetic instructions Move data from and to MAC Data format conversions Other instructions
MEL G642
Why MAC
MAC: Multiplication and accumulation unit
Performs convolution based algorithms
o FIR, IIR, Auto correlation, Cross correlation
Z-1
x(n-1)
Z-1
x(n-2)
Z-1
x(n-3)
Z-1
x(n-4)
c(1)
c(2)
c(3)
c(4)
y(n)
MEL G642
Why MAC
y (n) = x( n i )c(i )
i =0 m 1
Data x(n) is shifted through a FIFO buffer consisting of 4 registers So that x(n) become x(n-1) and x(n-1) become x(n-2) the next clock cycle All arithmetic executions are mapped to hardware in parallel There are four multipliers and four full adders A sample of y(n) is computed per clock cycle y(n) = x(n)*c(0) + x(n-1)*c(1) + x(n-2)*c(2 )+ x(n3)*c(3 )+ x(n-4)*c(4)
MEL G642
MAC basics
MAC: Multiplication and accumulation unit
Adder = accumulator; Accumulator register
MOA MOA MOB MOB Multiplier Pipeline AOB Accumulator
Multiplier AOA ACR ACR = Accumulating register Accumulator AOB ACR ACR = Accumulating register AOA
Flag circuit
Flag circuit
MUL circuit
MEL G642
Multiplications
How to manage double precision? How to manage signed?
Signed multiplication
Unsigned multiplication
Multiplications
How to manage double precision? The 16-bit signed and 16bit unsigned multiplication How to manage signed? can be implemented based
Hardware multiplication Fractional multiplication Integer multiplication
on a 17b17b signed multiplier. In general, a (N+1)(N+1) bits signed multiplier can give N bits signed and unsigned multiplication
Signed multiplication
Unsigned multiplication
ACR [47:0] <= {X[31], X[31:16]} * {Y[15], Y[15:0]} + 2-16*( 0, X[15:0]} * {Y[15], Y[15:0]});
ACR [64:0] <= {X[31], X[31:16]} * {Y[31], Y[31:16]} + 2-16*({ 0, X[15:0]} * {Y[31], Y[31:16]}) + 2-16*({X[31], X[31:16]} * {0, Y[15:0]}) + 2-32*({0, X[15:0]} * {0, Y[15:0]});
MEL G642
An example of MUL
MEL G642
MAC circuit
MEL G642
MAC instructions
MEL G642
MEL G642
MAC circuit
MEL G642
MEL G642
Control Signals
MAC instructions
Single step (signed) MAC
Integer Fractional
(Signed) Convolution
Integer Fractional
MEL G642
Double-Precision Arithmetic
MEL G642
MEL G642
MEL G642
MEL G642
Control Signals
MEL G642
MEL G642
MEL G642
MEL G642
MEL G642
MEL G642
MAC Modified
MEL G642
MEL G642
Specifications on the result 1 2 3 4 5 6 Rn <= ACRn[31:16] //Rn is a register in RF Rn <= ACRn[15:0] //Rn is a register in RF Rn <= ACRn[31:16]; Rn+1 <= ACRn [15:0] //Rn and Rn+1 in RF M1 <= ACRn[31:16]; M2 <= ACRn[15:0]; //M1 M2: memories Rn <= ACRn[31:16]; Rn+1<=ACRn[15:0]; Rn+2<=ACRn[39:32] Rn <= {8h00, ACRn[39:32]}; // guard to register file RF
MEL G642
MAC integration
MEL G642
Flags in MAC
Usually control code is implemented using ALU instructions
Flags in MAC is not used much
MEL G642
MEL G642
MEL G642
D-mem 1
D-mem 2
D-mem3
D-mem4
R F OPB
32 to1
R F OPA
32 to1
C onstant
Long wires
Long wires
As MAC input
MEL G642
MEL G642
Pipeline
* *
ACR ACR ACR
Accumulator
Accumulator
Accumulator
Flag circuit
Flag circuit
Flag circuit
(a) MAC in one clock cycle (b) MAC using two clocks
MEL G642
Constraints: A and B are 8 bits, registers are 8 bits ACR is 20 bits (including 4 guard bits). Only one multiplier may be used. You should select as small a multiplier as necessary. You also need to annotate whether it is signed or unsigned.
MEL G642
MEL G642
MEL G642
Questions?
MEL G642