CHANNEL CODING TECHNIQUES IN TETRA V Satheesh Prabhu & O M Vasudevan Broadcast & Communications Group ABSTRACT

The main concern in any communication system is the reliable transmission of signals of information from a transmitter to a receiver. The signals are transmitted via a channel which corrupts the signal. It is necessary that the distorting effects of channel and noise are minimized and that the information sent through the channel in any given time is maximized. Channel coding techniques are employed to do this. In this paper we discuss the different channel coding techniques employed in TErrestrial Trunked Radio (TETRA) mobile communication system. The base station and the mobile terminal conforming to this standard are currently under development in our centre. In our implementation of the base station controller, two DSP cards are used one for the transmitter and other for the receiver. These employ the TMS320C6416 processor from Texas Instruments as the main processing unit. TMS320C6416 is o ne of the highest-performance fixed-point DSPs available presently (around 4800 MIPS, operating at 600 MHz). It is based on the second-generation high-performance, VLIW architecture making it an excellent choice for multichannel and multifunction applications. The transmitter side DSP handles burst building, channel encoding, timing synchronisation, power control, rate adaptation, etc.The receiver side DSP demodulates the base band signal from the Down Converter module and applies channel decoding, burst deformatting, type detection, and demodulation. It also handles equlisation, diversity selection, timing synchronisation and the measurement functions (BER, RSSI, etc.). The processed data, is either passed to the MSC through the E1 link or passed to the BS C through an internal (cPCI) system bus.

This paper describes the different FEC schemes as applied in TETRA. The four coding blocks, viz., Block coding, RCPC, Interleaving and Scrambling are explained with examples. The performance criteria for different logical channels are listed. The scheme for base station implementation and the various DSP functions are is explained briefly. The channel codec algorithm has been fully developed, verified, and is presently under performance evaluation.
Keywords :TETRA, Channel Coding, Mobile Communication

INTRODUCTION Error correcting coding is included in a transmission system to protect against errors introduced by the transmission medium. 3 techniques are prevalent: (1) Error concealment: The errors are detected, the corrupted information is discarded. By interpolation, the error could be concealed. (eg., speech) (2) Automatic Repeat Request (ARQ): If error is detected, the transmitter is asked to send the data again (eg., packet data, control data). (3) Forward Error Correction (FEC): Additional data are added to the message so that the receiver can detect errors and correct them (eg., pay-load data). TETRA uses a comprehensive range of error control techniques to make efficient use of the air interface. Four basic stages are used, which have different parameters depending on the logical channels being sent. We elaborate further upon the different FEC techniques employed in TETRA.

TYPES OF CHANNELS TETRA employs a TDMA (Time Division Multiple Access) scheme. In this, several mobile units use the same carrier frequency divided into different time slots. In this, a r.f. carrier is divided into 4 time slots. A time slot is of duration 14.167 ms during which 510 bits of information could be transmitted to achieve a modulation rate of 36 kbps. All the bits do not convey same type of information (or logic). That is, a particular time slot do not carry a single information; these bits are grouped into several logical channels). Accordingly, we have different logical channels: (1) Access Assignment Channel (AACH) of 30 bits length, are used to indicate the assignment (means, who is authorized to use?) of the uplink and downlink slots. (2) Broadcast Synchronization Channel (BSCH) of 120 bits used for time and scrambling synchronization. (3) Broadcast Network Channel (BNCH) of 216 bits used for informing mobile about the network. (4) Signalling Channel (SCH) to carry messages of a mobile (5) Traffic Channel (TCH) of 432 bits that carry user information (of different data rates) FEC CODING for TETRA TETRA signaling and data channels use a four stage coding scheme for forward error correction and error detection. These are Block Coding, Convolutional Coding, Interleaving and Scrambling. (Fig.1) Data bits Block Coder

Convolutional Coder Interleave

Scrambling Data out Fig.1. TETRA Coding Scheme The first stage is Block coding. This provides error detection, and error reporting. No error correction is meant at this stage. FEC is provided by the Convolutional Coding, which is p unctured and called Rate Compatible Punctured Convolutional (RCPC) code. The rates used for puncturing are different for different logical channels. This offers different levels of protection against errors. (By rate, we mean the ratio of the no. of input bits to the no. of output bits)

Interleaving changes the bit positions within a block of data which helps to spread the errors effectively. Scrambling is a means of randomizing the data. This ensures that regular bit pattern do not occur which may affect synchronization, power amplification, etc. It also gives protection against false reception since different codes are used by each of the cells for scrambling purpose. In TETRA, different logical channels have different coding strategies. (Logical channels mean a group of bits which convey a logic or are meant for specific purpose) (Table 1). Table 1. Coding Steps used in TETRA AACH STCH BSCH BNCH SCH /HD y SCH SCH /HU /F y y TCH /2.4 n TCH TCH /4.8 /7.2 n n

Block coding

y (30, 14)

y (140, 124)

y (76, 60)

y (140, 124)

(140, (108, (284, 124) 92) 268)

RCPC Coding

2/3

2/3

2/3

2/3

2/3

2/3

148/ 432

292/ 432

Inter Leave

Block

Block

Block

Block

Block Block Burst 1,4,8

Burst n 1,4,8

Scrambling

(legend:y=yes, n=no). The speech channel is coded similarly, but not described here. DETAILS OF LINEAR CODES This is a simple method of coding. The code is defined by a generator matrix. A codeword is formed by multiplying (ANDing) the message bits with the generator matrix. The output codeword will contain original message bits as such wit h extra parity bits appended to it. This can be shown as: [ m1 m2 m3 mN] * G = [ m1 m2 m3 mN p1 p2 p3 .pK] where, m1, m2, etc are N message bits, G is the generator matrix, p1, p2, etc are K parity bits.

Eg: (7,4) Hamming code with 1000 0100 0010 0001 110 101 011 111

G=

for message bits [1010], we have the code word = [1010101] The parity bit p1 is found as bit by bit multiplication of [1010] with [1 1 0 1 ]T ie., with the fifth column of G and then adding (xor) of the resulting bits. Thus, p1 = (1*1) ^ (0*1) ^ (1*0) ^ (0*1) = 1 ^ 0 ^ 0 ^ 0 = 1. Other bits are obtained similarly. Decoding is also easy. When a codeword is received, its message part and parity part are separated. Once more we find the parity word for the message part. Now, we have two parity words: (1) received parity word and 92) the parity word calculated from the received message word. The calculated parity word is compared (xor) with the received parity word. This will be the syndrome of the received word. If syndrome is zero, there is no error in the received word. Otherwise, there is error, and this can be corrected using a look-up table. CYCLIC CODES In cyclic codes, each code word is the cyclic shift of the other code words. The parity bits are found to be the remainder obtained by dividing a shifted version of the message bits by a generator polynomial. Each bit in the code word is considered as the coefficients of a polynomial of (n-1)th degree. These codes are used to detect errors in a received code word. An example is given: the code polynomial is given by g(x) = 1+ x2 + x3, message bits = (m0, m1, m2, m3) = (1110). In this, g0 = 1, g1 = 0, g2= 1, g3 = 1.The encoder circuit is given fig.2. The codeword is obtained by appending parity bits to the message bits.

G0

g1

g2

g3

SR1

ADD SR2

ADD

SR3

A DD

Message bits Fig.2 Cyclic Encoder In this fig., SR is a shift register such that the arrangement represents the code polynomial. Initially, all the SRs will be reset to 0 state. For each cloc k, one bit of the message bit gets added to the circuit, the result is circulated. Depending on the polynomial coefficients, paths are closed to get the new states of each SR. After all the data bits have been entered, the SR outputs are equal to the parit y bits. These are read and appended to the message bits. For the above example, we will get 100 as the parity bits.

For detecting errors, same circuit is used to generate parity bits out of received message bits. If these generated parity bits match with those of the received parity bits, then there is no error. CONVOLUTIONAL CODES In this code, the current output bits depend not only on the current input but also on previous bits (memory of the code). A simple code with rate is generated with the circ uit of fig.3. The generating polynomials are (1) g1(x) = 1+x+x2, and (2) g2(x) = 1+ x2. ADD G1 output bits

Input bits Delay 1 Delay 2

ADD Fig. 3 Convolutional Encoder

G2 output bits

This code generates two output bits for each input bit. The output bits of the delays are called states. The states assume a new value for each clock depending on the input bit. The present input bit goes as the bit1 of the state for next clock. The present bit1 goes as the bit2 of the state for next clock. The two bits of the state can represent four states (00, 01, 10, 11). A present 00 state becomes 00 state for next clock if input bit is 0, giving an output 00. A present 00 state becomes 10 state for next clock if input bit is 1, giving an output 11. This is shown below in fig.4

Present 0in / 00 out S0

Next clock S0 (00)

1in / 11out S1 S2 S1 (01) S2 (10)

S3

S3 (11)

Fig. 4. Trellis ( State Transition Diagram) [partial]

By forming the complete state transition diagram, it is possible to deduce the output bits. The first bit is assumed to start with S0 state. (fig.5) Present 0in / 00 out S0 0\11 1in / 11out S1 0\10 S2 1\01 S3 1\10 S3 (11) 0\01 S2 (10) 1\00 S1 (01) S0 (00) Next clock

Fig. 5 Trellis ( State Transition Diagram ) The decoding follows a reverse process known as Viterbi decoding. Here, not only the initial state, but the final state will also be S0. The algorithm can be explained as follows: consider the states in any instant. At any instant, we have present states (S0, S1, S2 and S3) and next states (S0, S1, S2 and S3) . Assume that we have received 10 as the code word. If we consider the S0 state of next instant, two paths can reach that state (marked as path0 and path1). This is shown in fig. 6.

Present acc-wt0|k S0

Received : 10 0in / 00 out path0, metric=1

Next instant S0 : acc-wt0| k+1

0in / 11out acc-wt1|k S1 S2 S3 path1, metric =1 S1 S2 S3

Fig. 6. Trellis ( State Transition Diagram) [for decoding] Associated with each state is a parameter called accumulated weight. Associated with each path is a parameter called path metric. Path metric is nothing but the number of bits that differ between the received code at that instant and the generated output for that path in the Trellis. For example, 00 is the generated output for path 0 in the above fig. If the received code is 10, it differs by one bit from the should be path output. So, the path0-metric is 1. Similarly, path1-metric is 1. Now, we have to calculate the accumulated weight for S0. Since next S0 could be reached by two paths, the next accumulated weight is either (accumulated-weight of previous S0 + path0_metric) or (accumulated-

weight of previous S1 + path1_metric). Select the minimum of these as the next accumulatedweight of S0. We have also to store the path number which helped us to reach that state (either 0 or 1). Now proceed like this to complete the Trellis for all the states of one instant and then for all the instants. To start with, the accumulated weight of S0 will be set to 0, and the accumulated weight of other states will be set to a higher value. Since the end state is S0, we can trace back the paths from the end to the start. Once the paths are thus identified, the bits that caused those paths could be deduced (as we had done for encoding) (Simply pluck the MSB of the bits representing the state from which we move backwards). Fig.7 shows the Trellis decoding (Viterbi Algorithm) for the above example.

Fig.7 Trellis En-/De - coding Structure The generator polynomial used for TETRA are: 4 g1(x) = 1+ x + x ; 2 g2(x) = 1 + x + x3 + x 4; g3(x) = 1 + x + x2 + x4; g4(x) = 1 + x + x3 + x4 ; Accordingly, each input data bit generates 4 output bits. PUNCTURING Puncturing is the process of removing some of the additional parity bits. Some ability to correct errors will be lost by puncturing. But the process allows a trade -off between the number of bits added, and the resulting ability of the code to correct errors and the transmission requirements in terms of number of bits. For example, TETRA uses a rate code which means that for one bit of input, four output bits will be generated. If we have to send two bits, the code will thus generate eight output bits. However, if a 2/3 puncturing is used, only three output bits will be generated instead of eight for the two input bits. This made clear in the following: 7

Two input bits ------------- out put bits 1, 2, 3, 4, 5, 6, 7, 8 (2/8 without puncturing) Two input bits ------------- out put bits 1, 2, , , 5, , , (with 2/3 puncturing) Decoding follows the Viterbi Algorithm with slight modification. (The missing code bits are replaced with dont care bits while decoding). TETRA uses punctured code rates of 2/3, 148/432, 292/432, 8/17 and 8/18. INTERLEAVING Multipath fading can cause short term impairments of the received signal. These are called burst errors which affect a group of adjacent bits. The convolutional coding works best when errors occur randomly. It cannot cope with the burst errors. So the adjacent bits are separated and spread in a block while transmitted. At the receiver, they will be put back into their original position. The change in ithe index (order) of the bit will follow a linear algebraic equation. For example, a (120, 11) block interleave (used for BSCH) will input 120 bits with index i and output same 120 bits at the output with index j, such that jth index = 1 + (( ith index * 11) mod 120) Thus interleaving changes the bit order but does not transform the bits. Interleaving can be done on a single burst (block of data) or over several bursts (blocks of data). The number of bursts used is called the depth of interleav e. In TETRA, interleave depth of 1, 4, or 8 are used. If interleaving depth is more than one, it introduces delay both in transmission and reception. SCRAMBLING In TETRA, the scrambling sequence is generated using a 30 bit colour code, by means of a 32-bit long linear feedback shift registers. The scrambling polynomial is given by C(x) = 1 + x1 + x2 + x4 + x7 + x8 + x10 + x11 + x 12 + x16 + x22 + x23 + x26 + x32 The colour code forms the 30 bit initial values for the shift registers x1 to x30. The remaining two bits (x31 and x32) will be initialized with bits 1 each. Colour codes are different for different base stations. The scrambled bit stream is generated by a modulo two summation of the user bit stream with the random sequence generated by the maximal length feedback shift register. The polynomial identifies the shift registers which supply bits to the random sequence generator. For descrambling, the scrambled stream is modulo two summed with the output of another identical random sequence generator. (fig.8) ADD Input data Scrambled out ADD DeScrambled out

Random Sequence

Registers Fig.8 Scrambling/ De-scrambling process

Shift Registers

CODING PERFORMANCE The performance of the coding scheme depends on the radio channel conditions. The number of errors and the positioning of the errors are dependent on the type of channel. Different paths may exist between a Base Station and a Mobile due to large distant reflectors and due to scattering near mobile, giving rise to a number of waves arriving with different amplitudes and delays. When the mobile is moving, each path gets a Doppler shift depending on the speed of the mobile. The cumulative effect is fading of the signal. Two types of channels are considered: (1) TU50 (Typical Urban, with mobile unit moving at a speed of 50 kmph) and (2) HT200 (Hilly Terrain, with mobile unit moving at a speed of 200 kmph). The two performance parameters used are (1) Message Error Rate (MER) and (2) Bit Error Rate (BER), defined as: MER = (No. of messages received in Error after error correction) / (Total no. of messages transmitted), Expressed as a percentage for a given signal to interference ratio. BER = (No. of bits received in Error after error correction) / (Total no. of bits transmitted), Expressed as a percentage for a given signal to int erference ratio. An example of typical performance for a class A mobile with a signal to interference ratio of 19dB is given in Table 2. A third parameter used is called Probability of Undetected Erroneous Messages (PUEM). This is nothing but the ratio of messages that are erroneous, but detected wrongly as corrected messages to the total no. of messages received. Sometimes, a parameter called Block error rate (BLER) is also used. BLER = (No. of Blocks received in error, after error correction) / (No. of Blocks received). Table 2 Coding performance used in TETRA AACH STCH BSCH BNCH SCH SCH SCH /HD /HU /F MER 7% TCH TCH TCH /2.4 /4.8 /7.2 BER 2% BER 4%

TU50

MER 9%

MER 7% MER 9.2%

MER 6% MER 10%

MER 7%

MER MER BER 7% 6.5% 1.2%

HT200 MER 16%

MER MER MER MER BER BER BER 9.2% 9.2% 9.2% 7.5% 1.3% 3.8% 4%

DSP IMPLEMENTATION The coding algorithm developed in C is implemented on a DSP module for TETRA Base Station (BS) project. The features of the DSP module are listed below. There are two DSP cards in the base station; one for the Receiver (Rx) and the other for Transmit (Tx) processing. Rx DSP processes A/D output and decoded data is passed to the Tx DSP from where it is passed to BSC (Base Station Controller/ L2 stack) or to MSC (Main Switching Centre/ L3 stack) or to Tx Block (L1 stack). Both DSP cards are similar. DSP cards are cPCI-bus based. DSP selected is TMS 320C6416 of TI (Texas Instruments).

 Mc BSP (Multi-channel Buffered Serial Port) of the DSP can be synchronized through external clock (from GPS Rx block). Rx DSP interfaces A/D through McBSP 1. Rx DSP interfaces with Tx DSP through McBSP 2. Tx DSP interfaces with the Tx signal processor through a McBSP1. Tx DSP interfaces with the MSC through a full duplex McBSP using an E1 interface module. Both DSPs can interrupt the PC (controller) for communication purposes. The functional block diagram is as shown in the fig. 9. The DSP demodulates the base band signal from the Down Converter module and applies channel decoding, burst deformatting and other algorithms on the received data. The processed data, depending on the type of the data is either passed to the MSC through the E1 link or passed to the BSC through the cPCI bus. The Tx DSP has the additional task of E1 data formatting, Rate adaptation etc. apart from the transmit data processing. RF out PA ADC Clock From Ant ADC

TSP RS232
GPS/ Sync.

Down Convrt McBSP0

McBSP1 McBSP0 MSC (L3 Stack)

E1 Transceiver

Tx DSP McBSP2

Rx DSP

cPCI-BUS Fig. 9 BS Functional Block Diagram BSC (L2 stack)

The DSP works under DSP -BIOS and communicates with L2 upper layer protocol using interrupts. DSP also implements L2 lower layer, namely channel encoding/decoding, modulation/demodulation, burst formatting/deformatting etc. The software part of DSP could be divided mainly into two parts: device driver software and algorithmic software. Device driver software consists of DSP programs that are required to interface other devices to DSP and apply control over their operations. These are mainly

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DDC device driver Filter design of DDC E1 card interface Synchronizer interface Interface with upper layer Interface with lower layer Interface with RTOS

The main algorithms run on DSP are: Receive DSP : Transmit DSP: Burst building Channel encoding Timing synchronization Power control Rate adaptation (E1 i/f) Channel decoding Burst deformatting Burst detection Demodulation Equalizer Diversity selection Timing synchronization Measurements on BER,RSSI etc

After careful study of the processing power required, it was decided to use TMS320C6416 DSP for the purpose. The TMS320C64x DSPs (including the TMS320C6416 device) are the highestperformance fixed-point DSP generation in the TMS320C6000DSP platform. The TMS320C6416 (C6416) device is based on the second-generation high-performance, advanced VelociTI...verylong-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x is a codecompatible member of the C6000 DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6416 device offers cost-effective solutions to high-performance DSP programming challenges. The C6416 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional unitstwo multipliers for a 32-bit result and six arithmetic logic units (ALUs) with VelociTI.2...extensions. The VelociTI.2...extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C6416 can produce two 32-bit multiply -accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6416 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6416 uses a two-level cache -based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2)

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consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes three multi channel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 32-bit peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C source code of the coding algorithm is compiled using Code Composer Studio and embedded into the DSP module. CONCLUSION This paper has described the different FEC schemes as applied in TETRA. The four coding blocks, viz., Block coding, RCPC, Interleaving and Scrambling were explained with examples. Finally, we have listed the performance criteria for different logical channels. The channel codec algorithm has been fully developed and verified in C. The performance of the algorithm developed in C-DAC (T) is under evaluation. This paper is a presentation from Broadcast Communication Group. REFERENCES [1] ETR 300-1: Radio Equipment and Systems (RES); Trans -European Trunked Radio (TETRA); Voice plus Data (V+D); Designers guide; Part I: Overview, technical description and radio aspects, ETSI, 1997. [2] ETS 300-392-2: Radio Equipment and Systems (RES); Trans -European Trunked Radio (TETRA); Voice plus Data (V+D); Part II: Radio aspects, ETSI, 1997. [3]Rappaport, T.S., Wireless Communications: Principles and Practice, Prentice-Hall, 1996. [4] Stuber, G.L., Principles of Mobile Communication, Kluwer Academic Publishers, Boston, 1996. [5] Gibson, J.D., (ed), The Mobile Communication Handbook , CRC Press, Boca Raton and IEEE Press, 1996. [6] Proakis, J.G., Digital Communications, New York: Mc Grawhill, 1987. 7] John Dunlop, Demessie Girma, and James Irvine, Digital Mobile Communications and the TETRA System, John Wiley & Sons Ltd., New York, 1999.

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