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Purpose
Contents
1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 i.MX50 Microprocessor Overview . . . . . . . . 2 4 i.MX50 Power Management Design with MC13892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 i.MX50 Power Management Design with the MC34709 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 References . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Revision History . . . . . . . . . . . . . . . . . . . . . 44
The present document is intended to teach the reader how to supply the power management to the i.MX50x family of processors using either the Freescale MC13892 or the MC34709 as the main power management device.
Introduction
The i.MX50x family of microprocessors requires complex power management distribution along with specific sequencing for proper power up. To supply integrated power management to the i.MX50 processors, Freescale provides two highly integrated PMICs solutions for different specific scenarios. The MC13892, provide a highly integrated solution which provides most of the required voltage rails as well as integrated battery charger, 10 bits ADC and backlight LED drivers. Likewise, the MC34709 is a reduced solution providing as well the majority of the required power rails for applications with less system requirements.
The i.MX50 Applications Processors (i.MX50) is part of a growing family of multimedia-focused products, offering high performance processing optimized for lowest power consumption. The i.MX50 is optimized for portable multimedia applications and it features Freescale's advanced implementation of the ARM Cortex-A8 core, which operates at speed as high as 800 MHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). In addition, i.MX508 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, and displays. i.MX50 power requirements are summarized in Table 1. Table 1. i.MX50 Power requirements Voltage Domain Name
VDDGP
Voltage TYP
1.05 0.95 0.9 0.85 0.95 1.05 1.225 1.2 0.95 1.2 0.95 3.0 2.5 1.8 1.8 1.875 or 2.775 1.8 1.2
Current Units
V V V V V V V V V V V V V V V V V V 350 mA 10 150 10 10 mA mA mA mA 250 mA 400 mA
Description
400< fARM 800 MHz 167< fARM 400 MHz 24< fARM 167 MHz Stop Mode
Max
1250
Units
mA
VCC
VDDA
VDDAL1
Bandgap and 480 MHz PLL supply Efuse, 24 MHz oscillator, 32 kHz oscillator mux supply PLL digital supplies PLL analog supplies GPIO digital power supplies DDR2/LPDDR1 LPDDR2
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Voltage TYP
1/2 NVCC_E MI_DRAM 2.5 HVIO_L=1.875 HVIO_H=3.0
Current Units
V
Description
DRAM Reference Voltage Input
Max
0.004
Units
mA
VDDO25 NVCC_NANDF NVCC_SD1 NVCC_SD2 NVCC_KEYPAD NVCC_EIM NVCC_EPDC NVCC_LCD NVCC_MISC NVCC_SPI NVCC_SSI NVCC_UART NVCC_SRTC NVCC_RESET USB_H1_VDDA25 USB_OTG_VDDA25 USB_DDA33 USB_OTG_VDA33
V V
10
mA
SRTC core and I/O supply (LVIO) LVIO USB_PHY analog supply USB PHY I/O analog supply
V V V V 50 16 mA mA
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
3.1
VCC
VDDGP
VDDA VDDAL1
VDD3P0
VDDO2P5
VDD2P5
NVCC_EMI_DRAM
VDD1P8 VDD1P2
VREF
NVCC_EIM NVCC_EPDC NVCC_JTAG NVCC_KEYPAD NVCC_LCD NVCC_MISC NVCC_NANDF NVCC_RESET NVCC_SD1 NVCC_SD2 NVCC_SSI NVCC_UART
NOTE The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. No power-up sequence dependencies exist between the supplies shown shaded in gray.
3.2
Power-Down Sequence
The power-down sequence is recommended to be the opposite of the power-up sequence. In other words, the same power supply constraints exist while powering off as while powering on.
The MC13892 is a power management IC that includes the necessary sources to supply the i.MX50. Its main features are:
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Power control logic with processor interface and event detection Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC Touch screen interface SPI/I2C bus interface for control and register access
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
4.1
Typical Application
Buck regulators for processor core(s) Buck regulators for processor SOG, etc.
Buck regulators for internal processor memory and 0.600-1.375; 1.100-1.850 peripherals Buck regulators for external memory and peripherals
0.600-1.375; 1.100-1.850
800
Boost regulator for USB OTG, Tri-color LED drivers 5.0 IO and Peripheral supply, eFuse support Quiet Analog supply (PLL, GPS) Low voltage digital (DPLL, GPS) SD Card, external PNP External USB PHY supply TV DAC supply, external PNP Audio supply Camera supply, internal PMOS Camera supply, external PNP 2.775 1.2/1.25/1.5/1.8 1.05/1.25/1.65/1.8 1.8/2.0/2.6/2.7/2.8/2.9/3.0/ 3.15 2.4/2.6/2.7/2.775 2.5/2.6/2.7/2.775 2.3/2.5/2.775/3.0 2.5/2.6/2.75/3.0 2.5/2.6/2.75/3.0 1.2/1.5/2.775/3.15 1.2/1.5/1.6/1.8/2.7/2.8/3.0/ 3.15 1.8/2.9 1.8/2.9 3.3
300 100 50 50 250 50 350 150 65 250 200 350 50 250 100
General peripherals supply #1, external PNP General peripherals supply #2, external PNP General peripherals supply #3, internal PMOS General peripherals supply #3, external PNP
VUSB
4.2
The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators. Supply enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. Tying the PUMSx pins to ground corresponds to 00, open to 01, VCOREDIG to 10, and VCORE to 11. The recommended power up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the bare essentials, to allow processor startup and software to run. With such a strategy, the startup transients are controlled at lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering where specific sequences may be required, as well as supply default values. Software code can load up all of the required programmable options to avoid sneak paths, under/over-voltage issues, startup surges, etc., without any change in hardware. For this reason, the Power Gate drivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any peripheral loading is introduced.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
The power up defaults Table 3 shows the initial setup for the voltage level of the switching and LDO regulators, and whether they get enabled. Table 3. Power Up Defaults Table PUMS1 PUMS2
SW1 (1) SW2 (1) SW3
(1)
GND Open
0.775 1.025 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 3.150 Off
Open Open
1.050 1.225 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 Off Off
VCOREDIG Open
1.050 1.225 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 3.150 Off
VCORE Open
0.775 1.025 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 Off Off
GND GND
1.200 1.350 1.800 1.800 5.000 3.300 (4) 2.600 1.500 1.250 2.775 3.150 3.150
Open GND
1.200 1.450 1.800 1.800 5.000 3.300 (4) 2.600 1.500 1.250 2.775 3.150 3.150
SW4 (1) SWBST VUSB VUSB2 VPLL VDIG VIOHI VGEN2 VSD
Not initialized during power-up VCAM VGEN1 VGEN3 VVIDEO VAUDIO Notes
1. The SWx regulators are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer. 2. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 3. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO 4. SWBST = 5.0 V powers up and does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
The power up sequence is shown in Table 4. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer startup. Once VCOREDIG is activated (i.e., at the first-time power application), it will be continuously powered as long as a valid coin cell is present. Table 4. Power Up Sequence Tap x 2ms
0 1 2 3 4 5 6 7 8 9 Notes
5. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column. 6. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 7. SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
PUMS2 = Open
SW2 SW4 VIOHI VGEN2 SW1 SW3 VPLL VDIG VUSB (6), VUSB2
PUMS2 = GND
SW2 VGEN2 SW4 VIOHI, VSD SWBST, VUSB (7) SW1 VPLL SW3 VDIG VUSB2
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Power on event
VUSB VUSB2
2ms 2ms
4ms
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
4.3
Table 5, shows all the i.MX50 voltage rails, their power requirements and their associated MC13892 regulator. Most of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on each application needs Table 5. i,MX50 voltage domain supplies with the MC13892 I.MX50 Power Rail of i.MX50
NVCCSRTC VCC VDDA VDDAL1 VDDGP VDDO2P5 VDD2P5
MC13892 TYP
1.2 1.2 1.2 1.2 1 2.5 2.5
Power Domain
32 kHz osc. power (when chip off) LP Transistor power Peripheral Memory + L2 Cache power L1 Cache power Core and G Transistor power Predriver for EMI pads Power to 24 MHz osc, efuse, xtalok, 32 kHz osc. power mux Power to EMI pins DRAM Reference
Associated Regulator
VSRTC SW2 SW3 SW3 SW1 External LDO External LDO
PUS
0 5 5 4 -
NVCC_EMI_DRAM VREF
1.2 0.9
250
NVCC EIM NVCC JTAG NVCC SPI NVCC SD NVCC NANDF NVCC SSI NVCC MISC NVCC KEYPAD ALL 3.3V IO NVCC NVCC EPDC NVCC LCD NVCC UART NVCC_SD2 VDD3P0
3.0 V I/Os
3 3 3 3 3
3.0
350
3.0 V I/Os 3.15 3.15 3.15 3.15 VDD2P5 LDO input + power to Bandgap, DCDC predriver, tempsensor, 480 MHz PLL 3
External Buck
3.15
5000
VSD VGEN2
3.15 3.0
250 350
10
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Table 5. i,MX50 voltage domain supplies with the MC13892 I.MX50 Power Rail of i.MX50
USB_OTG_VDDA33 USB_H1_VDDA33 All 1.8 IO NVCC VDD DCDCI VDD DCDCO NVCC_RESET (LVIO)
MC13892 TYP
3.3 3.3 1.8 Not used
Power Domain
Power to USB Host Power to USB OTG 1.8 V I/Os
Associated Regulator
VUSB VUSB SW4
PUS
9 9 1
Power to POR_B,RESET_IN_B, TESTMODE, & BOOTMODE[0:1] Power to USB Host Power to USB OTG Power to all PLLs Power to all PLL digital, 32 kHz osc. (when chip on), much of analog, digital
1.875 or 2.775
VPLL
1.8
50
50 50 50 50
9 9 6 7
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
11
4.3.1
The following block diagrams show all the power connections needed for the interface, as well as how the communication signals must be connected between the i.MX50 and MC13892.
MC13892 SW1 5.0V SW2 SW4B VUSB 4.2V regulator 1.2V Buck VDDGP VCC NVCC_EIM_DRAM i.MX50
USB_VDDA33 USB_VDDA25 VDD1P2 VDD1P8 NVCC_RESET VDDA VDDAL1 VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_NANDF NVCC_KEYPAD NVCC_SSI NVCC_JTAG
VIN
VUSB2 VDIG
VPLL
VSW3
VGEN2
VDD2P5
Peripherals 3.15V Buck regulator 3.15V CODEC HDMI ETHERNET 3G PCIe RS-232
12
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
MC13892
RESETBMCU RESETB STANDBY POWERON1
SWx
i.MX50
POR_B RESET_IN_B PMIC_STBY_REQ PMIC_ON_REQ
SWx
WDI INT
SWx
WDOG GPIOX_X
CLK
4.3.1.1
For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current requirements (for example a 3G module or Wi-Fi card). The MC34709 has limited 3.15 V output ability.
4.3.1.2
A 1.2V Buck regulator is required to provide voltage to the 1.2V LPDDR2 module and the NVCC_EMI_DRAM domain in the i.MX50 processor. Regulator SW4 will supply the input of this regulator at 1.8V and will also be used as the 1.8V supply on the LPDDR2 Module as well.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
13
4.3.1.3
Due to the Power-up sequence dependency, two 2.5V LDO regulators are required to power up the VDD2P5 and VDDO25 domains in the i.MX processor. The first one is enabled by the SW2 voltage rail, while the second LDO is enabled with the VGEN2 voltage rail. See Figure 3.
4.3.2
NVCCSRTC VSRTC
The resulting power-up sequence of the interface is shown in the following figure
VCC VDD2P5 2.5V LDO regulator 1.8 NVCC I/O rails VDD DCDCI VDD DCDCO NVCC_EMI _DRAM 1.2V DC-DC regulator
SW2
SW4
N/A
VIOHI
VDD3P0 NVCC EIM NVCC JTAG NVCC SPI NVCC SD NVCC NANDF NVCC SSI NVCC MISC NVCC KEYPAD
VGEN2
VDDO25
VDDGP
SW1
VDDA VDDAL1
SW3
VPLL
VDD1P2
VDIG
USB_OTG_VDDA33 USB_H1_VDDA33
USB_OTG_VDDA25 USB_H1VDDA25
VUSB
VUSB2
SD2
14
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
4.4
The following schematic is simplified application example for interfacing the MC13892 with an i.MX50 processor. note that this schematic only includes the block related to the power section as well as power management controlling signals.
U12E PCIMX508DJV1A 3V_VGEN2 SH4 DNP VDD3P0 C66 0.1UF VDD2P5 SH8 DNP GND VDD2P5 C74 0.1UF 1V8_ANA_PLL C89 0.1UF GND VDD1P8 C75 22UF JP3 HDR 1X2 DNP VDDGP 1V_SW1
VDD3P0
AD4
VDD2P5
AD7
VDD1P8
VDDGP_1 VDDGP_2 VDDGP_3 VDDGP_4 VDDGP_5 VDDGP_6 VDDGP_7 VDDGP_8 VDDGP_9 VDDGP_10 VDDGP_11 VDDGP_12 VDDGP_13 VDDGP_14 VDDGP_15 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VDDA_1 VDDA_2
C68 0.22UF
C69 0.22UF
C85 0.22UF
C70 0.22UF
C86 0.22UF
C87 0.22UF
C71 0.01UF
C88 0.01UF
C72 10UF
C73 22UF
JP2 HDR 1X2 DNP VCC 1V2_SW2 C76 0.22UF GND C90 0.22UF C77 0.22UF C91 0.22UF C78 0.22UF C92 0.01UF C79 0.01UF C80 10UF C93 22UF
1V2_DIG GND VDD1P2 C81 22UF GND 1V8_SW4 SH6 DNP VDD_DCDCI C84 0.1UF GND DNP TP11 C97 68uFDNP C82 0.1UF
AD6
VDD1P2
H14 H15 H16 H17 J17 K14 K15 K17 L15 P17 VDDA R17
Y6
VDD_DCDCI
VDDAL_1 VDDAL_2 Y5 W5
GND
SH10 0
L8 1 VDD_DCDCO
VDD_DCDCO
VDDO2P5 SH11 0 JP4 HDR 1X2 DNP 1V2_DDR C101 0.22UF GND C102 0.22UF C103 0.22UF C104 0.22UF C105 0.22UF C106 0.22UF C107 0.22UF C108 0.22UF C109 0.01UF C110 0.01UF C111 10UF C112 10UF
GND_DCDC VDDO25
N23
C99 0.1UF GND
NVCC_KEYPAD
C100 0.1UF GND 3V_VGEN2 SH14 DNP NVCC_MISC C113 0.1UF GND NVCC_UART C117 0.1UF GND 3V_VGEN2 SH17 DNP
P8
NVCC_MISC
T8
NVCC_EMI_DRAM_1 NVCC_EMI_DRAM_2 NVCC_EMI_DRAM_3 NVCC_EMI_DRAM_4 NVCC_EMI_DRAM_5 NVCC_EMI_DRAM_6 NVCC_EMI_DRAM7 NVCC_EMI_DRAM8 NVCC_EMI_DRAM9 NVCC_EMI_DRAM10 NVCC_EMI_DRAM11 NVCC_EMI_DRAM12 NVCC_EMI_DRAM13 NVCC_EMI_DRAM14 NVCC_EMI_DRAM15 NVCC_EMI_DRAM16 NVCC_EIM1 NVCC_EIM2 NVCC_EIM3
NVCC_EIM 3V_VGEN2 C114 0.1UF GND C115 0.1UF C116 0.1UF C118 0.01UF C119 0.01UF C120 10UF NVCC_EPDC C122 0.1UF C123 0.1UF C124 0.1UF C125 0.01UF C126 10UF SH18 DNP SH16 DNP
NVCC_UART
L7 M7 M8
R8
DCDC_3V15
3V3_USB
AD11 AC11
C129
SH20 DNP C130 0.1UF 2V5_VUSB2 SH22 DNP C133 0.1UF C134 0.1UF 1V2_RTC SH24 DNP C136 0.1UF GND 3V_VGEN2 R56 DNP C138 0.1UF SH26 DNP GND GND 1V8_ANA_PLL 3V_VGEN2 0 1V8_SW4 C143 22UF C144 0.01UF
V10 V9
GND
U8
NVCC_SD2 NVCC_SRTC
GND AA1 NVCC_SRTC
T7
NVCC_SD1
NVCC_JTAG
GND 3V_VGEN2 SH27 DNP NVCC_SPI C145 0.1UF
U9
NVCC_JTAG
R7
NVCC_SPI
NVCC_RESET
GND
V8
NVCC_RESET
NGND_SRTC
GND_KEL GND1P2
A1 A18 A24 B18 G20 G21 G23 H12 H13 K12 K13 L12 L13 L14 L17 M11 M14 M15 M17 M18 M20 M21 N11 N14 N15 N17 P11 P12 P13 P14 R11 R12 R13 R14 T17 T18 U12 U13 U14 U15 U16 U17 U18 V17 V18 V20 V21 V23 AA9 AA11 AC18 AD1 AD18 AD24
AA7 AC6
AA2
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54
GND
GND
FCP: ___
1 2
NVCC_KEYPAD
N8
A21 B21 D21 D23 D24 K21 K23 K24 R21 R23 R24 AA21 AA23 AA24 AC21 AD21
1 2
SH5 0
1 2
AD3
i.MX50 - POWER
SH7 0
SH13 0
FIUO: X
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
15
C1 C2
C2 C1
B1 B2 A2
A2 B2 B1
Q1 FDZ193P
Q2 FDZ193P
5V Selection
5V_APL SH88 0 5V_MAIN USB_5V R313 0
1.2V LPDDR2
1V8_SW4 SH85 0
A1
B1 B2 A2
SH83 0 DNP
Q3 FDZ193P
GND
C1 C2
A1
BATTFET
A1
DNP
1
LED_ORANGE GND
C6 0.1UF R6 0 DNP
DNP
SH30
CHGR_DET_B_TO_PMIC
VCC_BP C7 10UF
C13
D10
D12
C12
A10
B10
B11
A11
E9 D8 E8
A7 D5 F5 B6 A6
U2 GND GPO1 R8 GND 4,5 BATT_NTC R320 DNP 4,5 0 TP3 BATT_NTC 10K R9 10K GND
GND
B7 E4 B5 E5
R7 47K DNP
C8
C9 GND
C11 4.7uF
C12 4.7uF
10UF 10UF
CHRGCTRL1
CHRGRAW
BATTISNS
CHRGISNS
BATTFET
BP
BPSNS
BATT
PUMS2 PWGTDRV1 PWGTDRV2 SW1IN SW1OUT SW1FB GNDSW1 SW2IN SW2OUT SW2FB GNDSW2 SW3IN SW3OUT SW3FB GNDSW3 SW4IN SW4OUT SW4FB GNDSW4
E7 K4 M7
GND
GND
GND
GND
Put 4.7UF capacitors at pins G13, H13, H1 and J1. (PUS_4) +/- 1%
SW1 C17 10UF GND 1V2_SW2 1V_SW1
GNDADC ADIN5 ADIN6 ADIN7 TSX1 TSX2 TSY1 TSY2 TSREF_1 TSREF_2 TSREF_3 ADTRIG BATTISNSCC CFP CFM SPIVCC CS CLK MOSI MISO GNDSPI VCORE VCOREDIG Reference Generation REFCORE GNDCORE
SW1 1050mA Buck SW2 800mA Buck Touch Screen interface SW3 800mA Buck
E11 B12 K7
VCC_BP 1.5UH G13 1 2 F13 L2 H10 R10 0 E13 VCC_BP H13 1 2 J13 L3 2.2UH C18 10UF J10 R11 0 GND K13 VCC_BP H1 1 2 G1 L4 2.2UH C19 10UF F4 F1 VCC_BP GND J1 1 2 K1 L5 2.2UH G4 L1 VCC_BP L6 1 D2 2 3.3uH
(PUS_0)
SW2
(PUS_5)
1V2_SW3 SW3 1V8_SW4 SW4 C21 10UF GND SWBST VCC_BP
(PUS_1)
VCC_BP
TO-2.0A
SWBST 350mA Boost SPI/I2C interface VVIDEO 350mA
K2 L2 M2 J2 H2 H4 A9 B9 D7 B8
GND
SWBSTIN SWBSTOUT SWBSTFB GNDSWBST VVIDEODRV VVIDEO VINUSB2 VUSB2_1 VUSB2_2 VUSB2_3 VINAUDIO VAUDIO
A4 B4 D4 A5 K12 L13 A3 A1 A2 B1
MBR120LSFT1G GND VVIDEODRV VCC_BP C24 C26 VCC_BP 2.2UF GND 2.2UF GND 3V_VAUDIO
3
Q6
4
NSS12100XV6T1G 2V775_VVIDEO
1 2 5 6
(PUS_9)
2V5_VUSB2
VUSB2 50mA
N7 N8
VCC_BP C31 C32 VCC_BP 2.2UF
UNUSED
2V775_VIOIH
NOTE: (PUS_X) means the Power Up Sequence index number during turn on.
GND
N10 N9
2.2UF GND
(PUS_2)
1V8_ANA_PLL GND (PUS_6) VCC_BP C33 C34 2.2UF 1V2_DIG
UNUSED
C1 E2 M9 M8
E6 E1 F2 G2 D1
(PUS_7)
2.2UF GND GND C35 2.2UF GND
VDIG 50mA
VPLL 50mA
UNUSED
VCC_BP 3V_VCAM Q8 NSS12100XV6T1G 3 VCC_BP
VCAM 250mA
C37
2.2UF GND
VSDDRV VSD
VSD 250mA
1 2 5 6
C36
2.2UF GND
(PUS_9)
C2 D2 M10 N11 N4 M3 N3 M1 N1 N2
VSDDRV
M6 K6
1 2 5 6
VCAMDRV
3V15_VSD
UNUSED
3V_VGEN1 Q10 NSS12100XV6 3
D9
C39 0.1UF GND
LICELL
VGEN1 200mA
1 2 5 6
C38 VGEN2DRV
2.2UF GND
VGEN1DRV
(PUS_3)
C40 VGEN3DRV VCC_BP Q11 NSS12100UW3 DNP 2.2UF GND
BT1 2994TR
VGEN2 350mA
2 1
Coin cell.
RESETB STANDBYSEC STANDBY INT WDI RESETBMCU CLK32K CLK32KMCU VSRTC
VGEN3 50mA
XTAL1
GND
1 3
UNUSED
1V8_VGEN3
N5 M5 H9 A8 G9 D13 E10 J8
F12 H12
K5 J4 M4
B2 F10 F9 G12
R21
0 R20
10M Y1 1 GND TP59 TP8 R22 0 GPO1 15pF GND ECKIL 0 0 R27 R25 4.7K 0 0 0 0 PWRON2 4,9 C46 1uF GND WDOG_B 4,8 PWR_INT(GP4_18) 4,8 PWRON3 4,15 PWRON1 1V2_RTC U5 VCC GND 1V2_RTC APL_GPIO2 5
1V2_RTC
GND C44
32.768KHz
C45
15pF
GND
VCCA
VCCB
B3 D6 H5 G5 J7
F6 F7 F8 G6 G7 G8 H6 H7 H8
N6
4,9 PMIC_STBY_REQ
A GND
B NC
4 5
R26
1 2
PMIC_ON_REQ
4,9
U6 NLSV1T34
Open-drain 4,9
required
GND NC7SP125P5X
GND GND
16
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
1 2 5 6
3V_VG
+ -
VSOURCE SH1 0 C47 100UF + C48 100UF + C49 100UF + C50 4.7uF C51 VDDI 0.1UF R31 9.31K GND U7
18
19
20
22
5 8 7
DDR2/DDR3 Power
DCDC_3V15
R34 R37 0
5.1K
3 2
0.7V
ILIM FREQ
L7 1.0UH
2
R35 4.12K 15K R39 17.4K 560PF C57 470pF C58 100UF R44 4.99K +
SH2 0
10 4
C59 100UF
+ C60 100UF
C61 0.1UF
12
13
14
25 MC34713EP
GND
DNP
3 7 4 2
C3 10uF
5
1V2_DDR
6 1 8
L1 1
2.2UH
2
R2 127.0K C4 20PF
E_PAD
C5 10uF
SH87 DNP
R5 133.0K
GND
Vout = 0.613 * [ R(Vout-Vfb) / R(Vfb-Gnd) + 1 ] Vout = 1.2V for R(Vout-Vfb) = 127K & R(Vfb-Gnd)=133K
VDDO2P5 LDO
VSOURCE U3 VDDO2P5
1
C16 2.2uF C15 100 PF
VOUT
5
C14 4.7uF GND
4 3 2
3
R306 100K
1 2
GND
3
Q5 MMBT3904
1V2_SW2
VDD2P5 LDO
3V_VGEN2 U4 VDD2P5
1
10K R16
VOUT
5
C29 22UF GND
4
C30 100 PF
3 2
GND
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
17
U12C PCIMX508DJV1A
1V8_SW4
NVCC_JTAG
AC1 AD2
RESET_IN_B POR_B
NVCC_RTC
EXTAL XTAL
AC5 AD5
GND R74 1.0M Y3 1V8_ANA_PLL
2
C149 18PF DNP SH31 SH0603 DNP
32.768KHZ DNP
Y2 GND
OSC.
3 2
GND
4 1 2
10K R76 C154 0.1UF
4 1
C152 15PF
GND
3
C153 15PF
OUT
GND
24MHZ
4,6
ECKIL
GND
4.5
The following example shows the PMIC layout section for a reference design of the i.MX50 using the MC13892 power management. It is design in 10 layers with 4 inner planes (GND and PWR) form layer 4 to layer 7. For simplicity, only top, bottom and Inner signal layers are shown in figures x to y.
10 R319
D2 1 L6 U2
R315
C48 TP4 TP5 C47 L4 L5 C49 1 4 C21 JP3 SH13 R93 R92 JP4 TP SH
18
1 R66 1 S
1 Y3 S
TP15
L9
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
C37 R316
TP8
C 1
02
1HS
01
2 91C 8Q
04
1 02J 1TB
023R
6Q
2HS
4PJ1
02HS 57C 7HS 62HS 36R 8HS 4HS 53C 43C 7R 23C
421C 121C
01Q 11Q 1
3PJ
7Q
19Q
51PT
2 10 1 1 1 1 1 1 4 1 1 1 C A 1 5 4 10 1
02C
92C
6C
72R 2 82R 52R 92R 62R 71C 34C 81C 22R 24C 5PJ 1 5 1 51 71
1 + 1
19
1 1
1
Figure 14. Top Layer
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
20
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
21
02
01
04
2 03 1 02 01 1 1
1 1 1 1 1 1
Figure 19. Bottom Layer
1 2
1 1
1 51 71
22
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
The MC34709 is a power management IC that includes the necessary sources to supply the i.MX50. Its main features are:
5.1
Supply
SW1 SW2 SW3 SW4A SW4B SW5 SWBST VSRTC VPLL
VGEN1 VGEN2
General peripherals supply #1 General peripherals supply #2, internal PMOS General peripherals supply #2, external PNP
VUSB
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
23
5.2
The MC34709 has 5 PUMS signals that enable to program the power up sequence as well as the default output voltage for specific rails, making the part suitable to supply DDR2, DDR3, LPDDR2, LVDDR3 memories with the correct power up sequence for many processors of the i.MX family. The following table shows the power up sequence and all possible voltage combinations to supply the i.MX50 in all possible modes. Table 7. Power-up Defaults i.MX50 PUMS[4:1]
PUMS5=0 VUSB2/VGEN2 PUMS5=1 VUSB2/VGEN2 SW1A (VDDGP) SW1B (VDDGP) SW2(8) (VCC) SW3(8) (VDDA) SW4A(8) (DDR/SYS) SW4B(8) (DDR/SYS) SW5(8) (I/O) VUSB(9) VUSB2 VSRTC VPLL VREFDDR VDAC VGEN1 VGEN2
mDDR 1010
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 1.8 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1
LPDDR2 1011
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 1.2 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1
LPDDR2 1100
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1
mDDR 1101
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1
LPDDR2 1110
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 2.5
mDDR 1111
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 2.5
Not used on System SWBST Off Off Off Off Off Off
Notes 8. The SWx node are activated in APS mode when enabled by the start-up sequencer. 9. VUSB is supplied by SWBST.
24
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer start-up. See Figure 2
Turn On Event Sequencer time slots System Core Active Turn On Verification Power Up Sequencer UV Masking RESETB INT WDI 8 ms 1 - Off 8 ms 20 ms 2 - Cold Start 12 ms 128 ms 3 - Watchdog 4 - On 3- Watchdog 1 - Off ow WDI Pulled Low
Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high Turn on Event is based on PWRON being pulled low = Indeterminate State
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
25
Power on event
SW5
2ms 2ms
2ms
2ms
26
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
5.3
Table 9, shows all the i.MX voltage rails, their power requirements and their associated MC34709 regulator. Most of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on each application needs Table 9. i.MX50 voltage domain supplies with the MC34709 I.MX50 Power Rail of i.MX50
NVCCSRTC VCC VDDA
Power Domain
32 kHz osc. power (when chip off) LP Transistor power Peripheral Memory + L2 Cache power L1 Cache power Core and G Transistor power Predriver for EMI pads Power to EMI pins DRAM Reference 3.0 V I/Os VDD2P5 LDO input + power to Bandgap, DCDC predriver, tempsensor, 480 MHz PLL Power to USB Host Power to USB OTG 1.8 V I/Os
MAX
1 2 3 4
SW4A
3.15
500
VUSB VUSB
3.3 3.3
100 100
9 9
SW5
1.8
1000
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
27
Table 9. i.MX50 voltage domain supplies with the MC34709 I.MX50 Power Rail of i.MX50
VDD2P5
Power Domain
Power to 24 MHz osc, efuse, xtalok, 32 kHz osc. power mux Power to USB Host Power to USB OTG Power to all PLLs Power to all PLL digital, 32 kHz osc. (when chip on), much of analog, digital
MAX
6 6 7 8
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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
5.3.1
The following block diagrams show all the power connections needed for the interface, as well as how the communication signals must be connected between the i.MX50 and MC34709.
MC34709 SW1A/B SW2 SW4 5.0V VUSB 4.2V regulator VDDGP VCC NVCC_EIM_DRAM USB_VDDA33 i.MX50
VIN SW5
VPLL VGEN2
VSW3
VUSB2
VDAC
VDDO25 VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_SD2 POP_NAND_VCC NVCC_NANDF NVCC_KEYPAD NVCC_SSI NVCC_UART NVCC_LCD NVCC_EPDC
VSW4A
VGEN1
VDD1P2
29
MC34709
RESETBMCU RESETB STANDBY POWERON1
SWx
i.MX50
POR_B RESET_IN_B PMIC_STBY_REQ PMIC_ON_REQ
SWx
WDI INT
SWx
WDOG GPIOX_X
CLK
5.3.1.1
For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current requirements (for example a 3G module or Wi-fi card). The MC34709 has limited 3.15 V output ability to supply al peripherals, however, in cases where Ethernet, 3G, or Wi-fi are not required, this buck converter may be eliminated from the power three.
30
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
5.3.2
The resulting power-up sequence of the interface is shown in the following figure
VCC
SW2
SW3
SW1A/B
VDDO2P5 VDAC
VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_SD2 POP_NAND_VCC NVCC_NANDP NVCC_KEYPAD NVCC_SSI NVCC_UART NVCC_LCD NVCC_EPDC POP_LPDDR2_18V NVCC_RESET NVCC_JTAG SW4A SW4B VREFDDR
VDD2P5 USB_VDDA25
VGEN2 VUSB2
VDD1P8
VPLL
VGEN1
USB_VDDA33
VUSB
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
31
5.4
The following schematic is simplified application example for interfacing the MC34709 with an i.MX50 processor. note that this schematic only includes the block related to the power section as well as power management controlling signals.
U6E 5_VGEN2 DCDC_3V15 3V15_SW4A_CPU 1V_SW1 C63 0 DNP 0 VUSB2_2V5 2V5_VGEN2 0 R479 R92 C68 0 DNP 0.1UF 1V8_VPLL 0 R93 C84 0.1UF 1V2_VGEN1 0 R95 C90 22UF GND 1V8_SW5 0 R463 C76 0.1UF GND L10 1 VDD_DCDCO L17 VDDO2P5 C94 0.1UF GND GND GND 2V5_VGEN2 3V15_SW4A_CPU R465 R466 0 0 DNP C97 0.1UF GND 3V15_SW4A_CPU J5 C110 0.1UF GND L5 C114 0.1UF GND 3V15_SW4A_CPU K5 C124 0.1UF GND 3V15_SW4A R368 3V15_SW4A_CPU 0.001 C126 0.1UF GND 3V15_SW4A_CPU SH12 DNP C130 0.1UF GND 3V15_SW4A_CPU P5 C134 0.1UF 3V15_SW4A_CPU GND N5 C136 0.1UF NVCC_JTAG GND 3V15_SW4A_CPU M5 C138 0.1UF NVCC_RESET GND P6 NVCC_RESET C139 0.1UF GND_KEL GND NC1 NC2 NC3 NC4 NVCC_SPI GND 1V8_SW5 R460 R461 0 0 DNP 3V15_SW4A_CPU P9 NVCC_JTAG C137 0.1UF NVCC_SD1 GND R101 R459 0 0 DNP 1V8_SW5 3V15_SW4A_CPU NVCC_SD2 NVCC_SRTC R5 GND NVCC_SRTC C135 0.1UF 1V2_RTC SH14 DNP C131 0.1UF 0.1UF P11 P12 NVCC_NANDF2 NVCC_NANDF1 USB_OTG_VDDA25_1 USB_H1_VDDA25_1 W9 Y9 C132 0.1UF GND USB_2V5 C133 0.1UF R100 0 0.1UF VUSB2_2V5 P10 NVCC_LCD USB_OTG_VDDA33 USB_H1_VDDA33 Y11 W11 C128 USB_3V3 C129 R98 R99 0 0 DNP GND GND 3V3_USB 3V15_SW4A_CPU C125 22UF C127 0.01UF NVCC_SSI NVCC_EPDC1 NVCC_EPDC2 NVCC_EPDC3 NVCC_EPDC4 F9 F10 F11 F12 GND C118 0.1UF C119 0.1UF C120 0.1UF C121 0.1UF C122 0.01UF NVCC_EPDC C123 10UF SH10 DNP 3V15_SW4A_CPU 3V15_SW4A_CPU NVCC_UART NVCC_EIM1 NVCC_EIM2 NVCC_EIM3 NVCC_MISC H5 K14 N14 J15 K15 L15 N15 P15 H16 J16 K16 L16 M16 N16 P16 R16 F6 F7 F8 NVCC_EMI_DRAM C98 C99 C100 0.22UF GND 0.22UF 0.22UF JP4 HDR 1X2 DNP 1V2_SW4 NVCC_KEYPAD NVCC_EMI_DRAM_1 NVCC_EMI_DRAM_2 NVCC_EMI_DRAM_3 NVCC_EMI_DRAM_4 NVCC_EMI_DRAM_5 NVCC_EMI_DRAM_6 NVCC_EMI_DRAM7 NVCC_EMI_DRAM8 NVCC_EMI_DRAM9 NVCC_EMI_DRAM10 NVCC_EMI_DRAM11 NVCC_EMI_DRAM12 NVCC_EMI_DRAM13 NVCC_EMI_DRAM14 NVCC_EMI_DRAM15 C101 0.22UF C102 0.22UF C103 0.22UF C104 0.22UF C105 0.22UF C106 0.01UF C107 0.01UF C108 10UF C109 10UF 1 2 R97 0.001 FIUO: X VDD_DCDCI R7 VDD_DCDCI C91 0.1UF C69 22UF GND VDD1P2 U6 VDD1P2 GND VDD1P8 V6 VDD1P8 R462 0.1UF R499 GND VDD2P5 V5 VDD2P5 VDD3P0 VDDGP_1 VDDGP_2 VDDGP_3 VDDGP_4 VDDGP_5 VDDGP_6 VDDGP_7 VDDGP_8 VDDGP_9 VDDGP_10 VDDGP_11 VDDGP_12 VDDGP_13 VDDGP_14 VDDGP_15 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VDDA_1 VDDA_2 VDDAL_1 VDDAL_2 C64 0.22UF GND C65 0.22UF C66 0.22UF C77 0.22UF C78 0.22UF C79 0.22UF C80 0.22UF C67 0.01UF C81 0.01UF C82 10UF C83 22UF R91 1 2 0.001 1V2_SW2 K10 L10 M10 K11 L11 M11 J12 K12 L12 K9 J11 J9 J10 C70 0.22UF GND C85 0.22UF C71 0.22UF C86 0.22UF C87 0.22UF C88 0.01UF C72 0.01UF JP3 HDR 1X2 DNP C73 10UF C89 22UF R94 1 2 VCC 0.001 FCP: ___ DNP 0 R412 VDD3P0 U5 G6 H6 J6 K6 L6 G7 H7 J7 K7 G8 H8 G9 H9 G10 H10 VDDGP JP2 HDR 1X2 DNP
i.MX50 - POWER
1V2_SW3
C74 0.1UF
C93 0.1UF
C75 0.1UF
R96
1 2
VDDA
0.001
2V5_VDAC DNP 2 C95 68uFDNP C96 DNP 0.1UF 2.2UH R6 VDDO25 T6 VDD_DCDCO GND_DCDC R370 0
3V15_SW4A_CPU
NVCC_EIM 3V15_SW4A_CPU C111 0.1UF C112 0.1UF C113 0.1UF C115 0.01UF C116 0.01UF C117 10UF SH8 DNP
T7
T5 W5 M6 N6 L7 M7 N7 P7 J8 K8 L8 M8 N8 P8 L9 M9 N9 N10 R10 G11 H11 N11 R11 G12 H12 M12 N12 R12 G13 H13 J13 K13 L13 M13 N13 P13 R13 G14 H14 J14 L14 M14 P14 R14 H15 M15 R15
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47
MCIMX508
A1 Y1 A20 Y20
GND
PU
32
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
F15
L9 2.2UH
SWBSTIN
SW1IN1 SW1IN2
P11 P10
2 1
G14
D6 MBR120LSFT1G
GND C46 22UF GND VCC_BP C20 4.7uF 1V8_SW5 GND 0.02 R367 BRL3225 2 L8 1 C252 0.01UF
SWBSTLX
GND
1V_SW1 BRL3225
R9 1
L3
H15 1
SWBSTFB
P7
C27 0.1UF
SW5IN
2
C30 22UF C31
SW1BLX
R11
(PUS_3)
22UF
R8
SW5LX
SW5LX
(PUS_6)
C45 22uF
M8
GND VCC_BP C19 4.7uF 1V2_SW4B 1V2_SW4B for EMI_DRAM_PAD GND C26 0.1UF
B11
P5
R6
(PUS_5)
C39 22UF
BRL3225 2
L7 1
SW4BLX
SW4BLX
GND
1V2_SW2
A10
L4 SW2LX 1
BRL3225 2 C33
(PUS_1)
P2
GND VCC_BP C18 4.7uF 3V15_SW4A R369 0.02 C38 22UF VCOREDIG GND VCORE DNP 0 DNP 0 0 GND R56 R57 R58 GND C25 0.1UF
SW4BFB SW4AIN
P4
2
L6
1
BRL3225
SW4ALX
R3 N2 M6
1V2_SW3 GND
(PUS_5)
1 L5
2 BRL3225
(PUS_2)
C35 10UF GND
MC34709
PC34709VK
VCORE for Parallel Dual Phase Mode VCOREDIG for Parallel Single Phase Mode GND for separate independent output mode
J14
VREFDDR 0 R378 C49 1uF 0.1UF GND VCC_BP C48 C47 0.1UF
LDOVDD VINREFDDR
N15 R363
K15
VREFDDR
VREFDDR
MC34709
VCC_BP
J15
Q8
(PUS_10)
VUSB2_2V5 0 R401
NSS12100XV6T1G
P14 R14
VUSB2DRV VUSB2
65mA INT. 350mA EXT. PNP VGEN1 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55V 250mA INT VUSB LDO 3.3V
VPLL LDO 1.2, 1.25, 1.5, 1.8V 50mA LDO VDAC LDO 2.5, 2.6, 2.7, 2.775V 250mA
VINPLL
L15
C158 2.2UF
1V8_VPLL R366 0
(PUS_8)
VPLL K14
GND
6 5 2 1
1V8_SW5 0 R373
VCC_BP
VDACDRV VDAC
3 1 2 5 6
H14
VINGEN1
C50 2.2UF
2V5_VDAC 0
(PUS_9)
(PUS_4)
H12
C57 2.2UF
VGEN1
VGEN1 has an internal PMOS pass FET and is powered from the SW5 for an efficiency advantage and reduced power dissipation in the pass devices.
buck
3V3_USB
R65 R375
0 0 C52
D1 D2
VINUSB VUSB
VGEN2DRV VGEN2
L14 M15
VGEN2DRV
3 1 2 5 6
R362 C59 2.2UF GND 0
SWBST
GND
VGEN2 LDO 2.5, 2.7, 2.8, 2.9, 3.0, 3.1, 3.15, 3.3V, 50mA INT. 250mA EXT. PNP
(PUS_7)
(PUS_10)
100mA INT.
2.2UF GND
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
33
3.15V/2A Regulator
VSOURCE R1 0 U30 L13 DCDC_3V15
5
J84 3V15_SW4A R8 C3 22UF R475 332K R474 13K GND C290 1000PF 0 DNP DCDC_3V15_EN R78 0
PVDD
LX
1
2.2uH
2
R2 294K
1 2
HDR 1X2
R1
VDD SHDN/RT COMP GND PGND PAD FB 7
6 1 8 2
4 9
R2
C2 22UF R3 100K
GND GND
GND
J1
2 1
B2B-PH-K-S
J2
J3
Silkscreen Labels:
THERM CON_1X3
DNP
3 2 1
GND
3 2 1
HDR_1X3
+
VCC_BP C4 47uF
THERMISTOR
(pg6)
3 2 1
HDR_1X3 J4
BATT_NTC
GND
U2
REG_4V2
2 1 3 6
IN EN
OUT
4 5
R4 42.2K C6 20PF C5 10UF R7 17.4K
R1
TPS78601
R2
GND
34
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
U3A
ADIN9
H6 J5 J6
N1
R1 A14 B15
U10 NCP4682
D14
3 4
BP
C32 GND
2.2UF
K6 K5 L4 L6 L3
NC_3
VIN
GND TAB_GND
CE
VOUT
VDDLP
2 5
VSRTC WORKAROUND
3V15_SW4A
PWM1 PWM2
A8 A7
PWM1
(pg10)
GPIOVDD
1.75V~3.6V SPI: Hold low when cold start I2C: Hold high when cold start. (pg9) (pg12,9) (pg12,9) (pg12,9) CSPI_SS0 CSPI_SCLK CSPI_MISO CSPI_MOSI GND
C8 C7 B7 B9 E10
R72 GPIOLV1
0 R77 0
1V8_SW5 DNP
A4
R49 R48 R51 R52 0 0 0 0
TP6
B2 B1 A2 B3
GPIOLV2 GPIOLV3
GPIOLV4
R82
DNP
TP7
Output, 0~SPIVCC
E3 G3 F3 H2
R76 0 Output, 0~1V2_RTC ECKIL 3V15_SW4A R73 C249 0 1V2_RTC 3V15_SW4A (pg10)
R54
4.7K GND
CLK32KVCC VSRTC
VCOREDIG 1.5V
VCORE R34
L1 J1 J2 K1
2.775V 1.2V
Reference Generation
C40
C41
C42 1uF
VCC
1 2
R86
WDOG_B
(pg9)
0.1UF 1uF
GND NC7SP125P5X
3
GND SYSTEM_DOWN(GP4_17) RESETB RESETBMCU (pg9)
GND
M2
C56 0.1UF GND
Coincell
LICELL WDI
K3 D6 B5 D5 B4 P1 A5 A6 E5 G6 G5 F6 F5 E6 A9
R75 0 DNP PWNON1 PWRON2 PUMS1 PUMS2 GND PUMS3 PUMS4 PUMS5 High: ICTEST mode Low: normal mode R74 0 10K R90 DNP VCOREDIG R89 R88 R87 R85 R84 R83 0 0 0 0 0 0 Output, 0~SPIVCC (active high) STANDBY GLBRST PMIC_INT(GP4_18) (pg9) Input, 0~3.6V, high level (1.0~3.6V) Input, 0~VCOREDIG(1.5V) open drain output (active low)
Battery Backup
2 1
+ BT1 2994TR
Coin cell.
3
-
GND
QZ1
E1 2
C62 15pF
Crystal Oscillator
XTAL1
1
C61 15pF
32.768KHZ
MC34709
GND PC34709VK GND
Power Up Mode
VCOREDIG 1V2_RTC C36 0.1UF R45 C37 0.1UF GND 0
1V8_SW5 VCOREDIG R66 10K GLBRST C54 (active high) GND (pg10,6) PMIC_STBY_REQ 1.2V level input R53 10K 0.1UF 1V8_SW5 GND GLBRST (pg17)
RESET
SW2
STANDBY
1 VCCA
R29 0 DNP R27 0 R30 0 R31 0 R32 0 DNP GND
3 4
SPST PB
1 2
GND
0 1 1 1 0
PUMS5 PUMS4 PUMS3 PUMS2 PUMS1 R37 0 R38 0 DNP R39 0 DNP R40 0 DNP R41 0
VCCB 4 5
B NC
R50
STANDBY
U4 NLSV1T34
GND RESETBMCU GND GND (pg10,6) PMIC_STBY_REQ R55 0 DNP RESETB R71 0 D13 BAT54A-7-F 1 C60 R70 0 POR_B (pg10) (pg10)
GLBRST
R67
DNP
R68 68K
R69 68K
RESET_IN_B
3
(pg10) U3D JTAG_RESET_B R397 0
0.1UF GND
SUBSLDO SUBSGND SUBSPWR SUBSPWR3 SUBSPWR2 SUBSPWR1_8 SUBSPWR1_7 SUBSPWR1_6 SUBSPWR1_5 SUBSPWR1_4 SUBSPWR1_3 SUBSPWR1_2 SUBSPWR1_1
GNDSWBST
GNDSW1B1
GNDSW5
A3 H1 M1 C1 C9 F1 B6
P8
K8 K12 F10
H5
P6 P3 P9
P12
F14
GND
GND
PC34709VK
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
D14
GNDSW3
GNDADC
35
U6C
1V8_SW5 R8 R9 U8 T9 U7 T8 V4 SH21 JTAG_TCK (pg10) JTAG_TMS (pg10) JTAG_TDI (pg10) JTAG_TDO (pg10) JTAG_TRST_B (pg10) DNP R129 1K W6 Y6 GND R130 1.0M 1V8_VPLL Y1 VCC EN/DIS DGND 22.5792MHZ DNP GND GND 4 1 2 10K R134 C142 0.1UF R119 10K DNP JTAG_MOD
V3 U3 U4 Y2 Y3 Y4 W4
NVCC_JTAG
W3 Y5
RESET_IN_B POR_B
(pg6) (pg6)
NVCC_RTC
EXTAL XTAL
32.768KHZ DNP
OSC.
3 2
GND
3 C143 15pF
OUT
GND
24MHZ
(pg6)
ECKIL
Figure 30. i.MX50 Control Signals If an external battery charger is required, it is recommended to use a charger with power path management which isolates the battery from the system node while charging. The main system voltage from the charger will be connected directly to the BP node while the external charging voltage and the battery are connected on the chargers end.
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5.5
The following is a layout example of the MC34709 implemented on a four layer board with all component on the top layer and using standard 8 mils vias.
2 J125 16 J122 2 12 VSWBST_SENSE1 BH2
BH1
15
11 C A D23 R141 C A R142 C75 D18 C A R140 C76 D19 C A R143 C74 D24 C A D22 C A D21
R162
R163
R164
R161
4 5
U7 3 1 C D17
F1
TP1 1 L11
S3
S1 1 5 J121
S4 L12
S2 1
1 R153 BH4
5 J123
D3
J58 CLKVCC1 1 1
2012 FREESCALE
KIT34709VKEVBE
S/N
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
R165
R157
R160
1 J68 J120 J3 1
J2
4 U2 5
4 U4 5
Q8
R147 R146 R148 R149 SW3 SW2 2 2 GLBRST1 J29 1 1 C80 J69 1 J37 2 5 6 J31 1 J30 1 1 INT1 PWM2 PWRON1 R151 C84 A
C41 R58 R127
J60 1
J62 1
J67 1
J74
20
19
L10 D9 R48 R47 GNDSW4A1 D10 1C66 C6 1 U1 GNDSW3 A BC D16 R124 J21 DE C59 C28 FG 1 C3 1 HJ C32 KL C30 C49 C40 Q3 M C31 C23 C46 VGEN2 VHALF1 PN C22 R Q4 C44 C21 C20 D11 VREFDDR1 VDAC1 C58 D13 D7 C37 R49 C15 L7 R53 C27 C13 D12 1 D8 LDOVDD1 C9 TSY2 L8 L9 J52 J56 VUSB2 1 Q6 C16 B 1 1 1 1 1 1 B SW4ALX1 C Q5 C19 GNDSWBST1 GNDSW4B1 1 C25 2 2 R125 SW4BLX1 R60 R128 VPLL1 Q2 J32 J43 1 J47 1 BAT1 1 1 Q1 1 J78 J79 J77 1 R41 1 J81 R44 SW1ALX1 SW1BLX1 1 R43 1 C R40 L2 L3 1 R38 R42 R35 J76 R37 C60 R121 C62 TSX1 J80 1 1 R66 R67 C53 R52 C57 TSREF1 C45 R59 R126 C7 C8 R55 GNDSW1A1 TSY1 SW5LX1 GNDSW5 SW1FB1 C29 R45 R39 R36 TSX2 J70 1 J71 1 J73 1 J72
GNDSW2 VUSB1
STANDOFFS REQUIRED
Figure 31. KIT34709VKEVBE FAB Drawing
C26 C14 1
BH6
J117
9 19 J66 20 8 BH3
37
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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
A VER 83372-071
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
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5.6
For customers migrating from the MC34708 platform to the MC34709 a very low design effort is required due to the high compatibility system between the to devices. Table 10 shows the main difference between both power management devices. Table 10. MC34708 and MC34709 difference Features
Control Logic Power control logic with processor interface and event detection Single SPI/I2C bus for control & register access Real time clock and crystal oscillator circuitry with coin cell backup Support for external secure real time clock on a companion system processor IC 10 bit ADC 4 wire resistive touchscreen interface 7 External ADC inputs. Dedicated ADC channel for Battery voltage sensing Dedicated ADC channel for battery current sensing Dedicated ADC channel for BP voltage Dedicated ADC channel for Die temperature Dedicated ADC channel for VBUS voltage. (USB device detection) Dedicated ADC channel for coin cell voltage Power Supplies(10) 5 Buck regulator 1 Boost regulator 8 LDO Regulators with internal and external pass devices. Auxiliary Circuits USB/UART/Audio switching for mini-micro USB connector Four general purpose low voltage I/Os with interrupt capability Two PWM outputs Two General purpose LED drivers Package 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch Notes:
10. All Power supplies have the same voltage and current rating on both devices.
MC34708
MC34709
No Yes Yes No
Yes Yes No
No No Yes
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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
References
Firmware portability is straights forward, since register maps are bit to bit compatible. However, the MC34709 uses a reduced set of register which eliminate all registers/bits related to the functionality not supported on the MC34709, therefore care must be taken that RESERVED registers/bits are not addressed on the firmware when porting the application to the MC34709.
References
Description
Data Sheet Data Sheet Development Guide Reference Manual Data Sheet
Document Number
MC34709 MC13892 IMX50SDG IMX50RM IMX50CEC
Description / URL
http://cache.freescale.com/files/analog/doc/data_sheet/MC34709.pdf?fsrch=1&sr=2 http://cache.freescale.com/files/analog/doc/data_sheet/MC13892.pdf?fsrch=1&sr=1 http://cache.freescale.com/files/32bit/doc/user_guide/IMX50SDG.pdf?fsrch=1&sr=1 http://cache.freescale.com/files/32bit/doc/ref_manual/IMX50RM.pdf?fsrch=1&sr=10 http://cache.freescale.com/files/32bit/doc/data_sheet/IMX50CEC.pdf
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
43
Revision History
Revision History
Revision
1.0
Date
12/2012 Initial release
Description of Changes
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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
Revision History
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor
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