HIGHSPEEDANDLOWPOWERDESIGNOFCONTENT ADDRESSABLEMEMORY

Athesissubmittedtothe DEPARTMENTOFELECTRICALANDELECTRONICENGINEERING OF BANGLADESHUNIVERSITYOFENGINEERINGANDTECHNOLOGY inpartialfulfillmentof therequirementsforthe degreeof BachelorofScienceinElectricalandElectronicEngineering

By

MD.NAIMULHASAN(0306017) MD.TAUHIDURRAHMAN(0306035) MD.MEHEDIHASAN(0306071)

Supervisor

DR.A.B.M.HARUNURRASHID
Professor,DepartmentofEEE, BUET,Dhaka1000

BANGLADESHUNIVERSITYOFENGINEERINGANDTECHNOLOGY
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Declaration
We hereby declare that the work presented in this thesis entitled High Speed and Low Power Design of ContentAddressable Memory is the outcome of the investigation carried out by us and neither this thesis nor any part thereof has been submitted or is being currently submitted anywhere else for the award of any degreeordiploma.
..

Md.NaimulHasan
(0306017)

Md.TauhidurRahman
(0306035)

Md.MehediHasan
(0306071)

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Our parents.

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ACKNOWLEDGEMENTS
Atfirst,wewouldliketoconveyourgratitudetoAlmightyAllahwithout whosewishnothingispossible. Wewouldliketoexpressourprofoundgratitudeandappreciationtoour Thesis supervisor, Professor Dr. A. B. M. HarunUr Rashid for his benign attitude towards us and whose supervision gave us the opportunity to get involved in this stateoftheart and greatly emerging research of lowpower and highspeed design of circuits specially ContentAddressable Memory (CAM). His generous help, encouragement and constant guidance accelerated thecompletionofthisthesis. We also would like to express our special thanks to Mr. Ataur Rahman Patwary, School of Electrical and Computer Engineering, Oregon State University, USA for his suggestions and different kinds of help to complete the work. We would like to thank the alumni of BUET (also members of Yahoo! GroupBUETian)fortheirhelpbyprovidingalotofnecessaryworks. We also would like to acknowledge the help of the Department of ElectricalandElectronicEngineering,BUETforlettingustousetheVLSIserver computertosimulatelargeHSpicefile.
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CONTENTS
Page Declarationii Dedication.iii Acknowledgementiv Contents.v List of Figures viii List of Tables.xi Abstractxii

CHAPTER 1: INTRODUCTION ...................................................................................................... 2 1.1 INTRODUCTION .................................................................................................................. 2 1.2 MOTIVATIONS ................................................................................................................... 3 1.3 OBJECTIVES ....................................................................................................................... 4 1.4 THESIS ORGANIZATION ..................................................................................................... 4 CHAPTER 2: DIFFERENT TYPES OF LOGIC ................................................................................ 7 2.1 INTRODUCTION .................................................................................................................. 7 2.2 RATIOED LOGIC................................................................................................................. 7 2.2.1 Load Resistance RL ................................................................................................... 7 2.2.2 nMOS depletion mode transistor pull up .................................................................. 8 2.2.3 nMOS enhancement mode pull up ............................................................................ 8 2.2.4 Pseudo-nMOS logic .................................................................................................. 9 2.3 COMPLEMENTARY TRANSISTOR PULL-UP (CMOS) ............................................................ 9 2.3.1 Components of Total Power Dissipation in CMOS Circuits .................................. 10 2.4 DYNAMIC CIRCUITS......................................................................................................... 11 2.5 DOMINO LOGIC ............................................................................................................... 16 CHAPTER 3: CONTENT ADDRESSABLE MEMORY (CAM) REVIEW ........................................ 19 3.1 INTRODUCTION ................................................................................................................ 19 3. 2 CORE CELLS AND MATCHLINE STRUCTURE .................................................................... 22 3.2.1 Structure of NOR Cell ............................................................................................. 22 3.2.2 Structure of NAND Cell .......................................................................................... 23
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CONTENTS (Continued) Page 3.2.3 Ternary Cells ........................................................................................................... 23 3.3 MATCHLINE SENSING SCHEMES ...................................................................................... 25 3.3.1 Conventional (Precharge-High) Matchline Sensing................................................ 25 3.3.1.1 Basic Operation ................................................................................................. 26 3.3.1.2 Matchline power .............................................................................................. 27 3.3.1.3 Charge Sharing.................................................................................................. 27 3.3.1.4 Power Consumption .......................................................................................... 28 3.4 LOW-SWING SCHEMES ................................................................................................... 29 3.5 CURRENT-RACE SCHEME ................................................................................................ 30 3.6 SELECTIVE-PRECHARGE SCHEME .................................................................................... 31 3.7 PIPELINING SCHEME ........................................................................................................ 32 3.8 CURRENT-SAVING SCHEME ............................................................................................. 34 3.9 CONCLUSION ................................................................................................................... 35 CHAPTER 4: PROPOSED CHARGING CONTROL SCHEME & SENSE AMPLIFIER ..................... 37 4.1 INTRODUCTION ................................................................................................................ 37 4.2 PROPOSED CHARGE CONTROLLING SCHEME ................................................................... 37 4.3 SIMULATION RESULTS AND ANALYSIS ............................................................................ 39 4.4 CORNER SIMULATION OF THE SCHEME ............................................................................. 41 4.5 CONCLUSION ................................................................................................................... 42 CHAPTER 5: PROPOSED SIMPLIFIED DESIGN OF CHARGING CONTROLLER .......................... 44 5.1 INTRODUCTION ................................................................................................................ 44 5.2 PROPOSED ML CHARGING TECHNIQUE ........................................................................... 46 5.3 SIMULATION RESULTS AND ANALYSIS ............................................................................ 48 5.4 CONCLUSION ................................................................................................................... 50 CHAPTER 6: PROPOSED CAM WITH IMPROVED NOISE MARGIN ............................................... 52 6.1 INTRODUCTION ................................................................................................................ 52 6.2 OPERATION OF THE SCHEME ............................................................................................ 52 6.2.1 Charging controller.................................................................................................. 53 6.2.2 The sense amplifier ................................................................................................. 54 6.3 SIMULATION RESULT....................................................................................................... 55
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CONTENTS (Continued) Page 6.4 CONCLUSION ................................................................................................................... 57 CHAPTER 7: Conclusion ........................................................................................................... 59 7. 1 CONCLUSION .................................................................................................................. 59 7.2 FUTURE WORK ................................................................................................................ 59 Reference ................................................................................................................................. 61 Bibliography ............................................................................................................................ 69 RESEARCH PAPERS FROM THIS THESIS ..................................................................................... 70 APPENDIX A ............................................................................................................................. 71 A.1 HSPICE CODE FOR CHARGING CONTROL SCHEME........................................................... 71 A.2 HSPICE CODE FOR SIMPLIFIED DESIGN OF CHARGING CONTROLLER .............................. 122 A.3 HSPICE CODE FOR IMPROVED NOISE SCHEME [CHAPTER 6] ........................................... 124 APPENDIX B............................................................................................................................ 128 B.1 INTRODUCTION ............................................................................................................. 128 B.2 INSTALLATION AND USAGE OF HSPICE 2007 ................................................................ 128 B.3 BASIC RULES OR QUICK MANUAL [2] ........................................................................ 131 B.3.1. Input File .............................................................................................................. 131 B.3.2. Element Description ............................................................................................ 132 B.3.3. Analysis ............................................................................................................... 134 B.3.4 References............................................................................................................. 135

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LIST OF FIGURES PAGE

Fig. 2. 1: Resistor Pull-up...................................................................................................................... 7 Fig. 2. 2: nMOS depletion mode transistor pull up................................................................................ 8 Fig. 2. 3: nMOS enhancement mode pull up......................................................................................... 8 Fig. 2. 4: Pseudo-nMOS Logic.............................................................................................................. 9 Fig. 2. 5: Complementary transistor pull-up (CMOS)........................................................................... 9 Fig. 2. 6: CMOS inverter current versus Vin....................................................................................... 10 Fig. 2. 7: Precharge and evaluation of dynamic gates.......................................................................... 11 Fig. 2. 8: Footed dynamic inverter....................................................................................................... 12 Fig. 2. 9: Unfooted dynamic gates....................................................................................................... 12 Fig. 2. 10: Generalized footed gates.................................................................................................... 13 Fig. 2. 11: Logical effort of footed and unfooted dynamic gates.........................................................13 Fig. 2. 12: Monotonicity problem........................................................................................................ 14 Fig. 2. 13: Incorrect connection of dynamic gates............................................................................... 15 Fig. 2. 14: Standard Domino Logic circuit.......................................................................................... 16 Fig. 2. 15: Weak keeper implementation............................................................................................. 17 Fig. 3. 1: Simple schematic model of a 4x3 CAM array showing the core memory cells, differential search lines, match lines and encoder.................................................................................................. 20 Fig. 3. 2: Profile of CAM capacity (log scale) versus year of publication [33][40]...........................21 Fig. 3. 3: CAM core cells for (a) 10-T NOR-type CAM and (b) 9-T NAND-type CAM. The cells are shown using SRAM-based data-storage cells...................................................................................... 22 Fig. 3. 4: Structure of Ternary core cells for (a) NOR-type (b) NAND-type CAM [41], [42]............24 Fig. 3. 5: (a) the schematic with precharge circuitry for matchline sensing using the precharge-high scheme, and (b) the corresponding timing diagram showing relative signal transitions. [34] ..............26 Fig. 3. 6: Matchline power for NAND and NOR architecture [33] ......................................................27 Fig. 3. 7: Two possible congurations for the NOR cell: (a) the stored bit is connected to the bottom transistors of the pulldown pair, and (b) the stored bit is connected to the top transistors of the pulldown pair.......................................................................................................................................28 viii

LIST OF FIGURES PAGE

Fig. 3. 8: Low-swing matchline sensing scheme of [33]. .....................................................................29 Fig. 3. 9: (a) Circuit implementation including precharge circuitry and (b) a timing diagram for a single search cycle. For current-race matchline sensing [51]. ..............................................................31 Fig. 3. 10: Sample implementation of the selective-precharge matchline technique [52]....................32 Fig. 3. 11: Pipelined matchlines reduce power by shutting down after a miss in a stage.....................33 Fig. 3. 12: Simulated wave forms in the pipelined match-line architecture for (a) the full-match case consisting of a match in every stage, and (b) a miss case where the third stage results in a miss and turns off the subsequent stages.[58]..................................................................................................... 33 Fig. 3. 13: Current-saving matchline-sensing scheme......................................................................... 34 Fig. 4. 1: Structure of the CAM of the proposed scheme: (a) basic architecture and (b) NOR-type TCAM cell used in the scheme............................................................................................................ 38 Fig. 4. 2: Internal circuit of the charging controller............................................................................. 39 Fig. 4. 3: Proposed sense amplifier (SA)............................................................................................. 40 Fig. 4. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched), ML1 (onebit miss), ML2 (two-bit miss), MLC and MLP.................................................................................... 41 Fig. 4. 5: Corner Simulation results for FHL (when threshold voltage= -10%,VDD=+5%, and temparature=273K) .............................................................................................................................. 42 Fig. 4. 6: Corner Simulation results for SLH (when threshold voltage= +10%,VDD=-5%, and temparature=343K) .............................................................................................................................. 42 Fig. 5. 1: Simplified conventional CAM architecture.......................................................................... 45 Fig. 5. 2: Structure of the CAM array with the proposed scheme: (a) the basic architecture and (b) internal circuit of the NOR-type TCAM cell used in this scheme. Here the usual SRAM access transistor and associated bitlines are omitted for simplicity................................................................47 Fig. 5. 3: The ML charging unit proposed in this work and the sensing unit proposed in [84]............47 Fig. 5. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched), ML1 (onebit miss), ML2 (two-bit miss), MLC and MLP.................................................................................... 48 Fig. 6. 1: Structure of the CAM array.................................................................................................. 53 Fig. 6. 2: Internal circuitry of improved Charging............................................................................... 53 Fig. 6. 3: Waveforms for CAM ............................................................................................................ 54 ix

LIST OF FIGURES PAGE

Fig. 6. 4: Conventional sense amplifier............................................................................................... 55 Fig. 6. 5: Charging in different match-lines......................................................................................... 55 Fig. 6. 6: Controlled signals and output of each match-line.................................................................56

LIST OF TABLES PAGE

Table 3. 1: Truth Table for NOR Cell .................................................................................................. 24 Table 3. 2: Truth Table for NAND Cell............................................................................................... 24 Table 3. 3: Comparison between the schemes[62]............................................................................... 35 Table 4. 1: Comparison of Different Schemes..................................................................................... 41 Table 5. 1: Comparison of Different Schemes..................................................................................... 49 Table 6. 1: Comparison of Different Schemes with improved noise margin scheme..........................56 Table 6. 2: Comparison of Noise Immunity of different schemes.......................................................57

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ABSTRACT
The growing market demand of the integrated circuits and energy crisis in the whole world accelerate the researchers to find out new process technology with smaller transistors, to design the circuits more efficiently which needs less power and operate in higher speed. The purpose of this dissertation is the same i.e. to find a way to design digital circuit specifically Content-Addressable Memory (CAM) which needs low power and operates in higher speed with maintaining the noise immunity. Content-addressable memory (CAM) is an attractive component in network routers for packet forwarding and packet classification and also in other applications that require high-speed searches. This dissertation presents three techniques to increase speed and reduce the energy per bit per search. In the first technique, the charging of fully matched matchline is reduced from VDD to VDD/3 and this voltage is sensed by our proposed sense amplifier. This reduces the power consumption greatly. In the second scheme, the charging controller is made simple (to get a low cost circuit) with the cost of some energy. In the third scheme with high noise margin, only probable matched matchlines are charged to almost VDD. Most of the matchlines are not charged so much. So in most of the matchlines, the power consumption is very low. All the schemes (conventional current saving and current race scheme also) are simulated in TSMC 0.18 m technology with 64 x 72 Ternary CAM. For first charging control technique, simulation shows that the match-line energy reduction is 57% and 54% compared to the current-race and current-saving schemes respectively and 55% compared to the conventional current-race scheme while speed of operation is increased by over 3 times. For the second simplified scheme, the energy efficiency is little bit lower. The third scheme provides very good noise margin with maintaining sufficient energy reduction and speed of operation. The more accurate result can be obtained by doing Layout of the proposed schemes. We can say that this dissertation provides some good schemes for the content addressable memory. We hope that the proper layout of the schemes would provide good results also. We also hope that we would get some good alternatives for existing CAM after fabrication of the chip.

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CHAPTER1 INTRODUCTION

CHAPTER 1 INTRODUCTION
1.1INTRODUCTION
A CONTENT-ADDRESSABLE memory (CAM) compares input search data against a table of stored data, and returns the address of the matching data. CAMs have a single clock cycle throughput making them faster than other hardware- and software-based search systems. CAMs can be used in a wide variety of applications requiring high search speeds. These applications include cache memory, parametric curve extraction, Hough transformation, Huffman coding/decoding, LempelZiv compression, and image coding [1]. The primary commercial application of CAMs today is to classify and forward Internet protocol (IP) packets in network routers. In networks like the Internet, a message such an as e-mail or a Web page is transferred by first breaking up the message into small data packets of a few hundred bytes, and, then, sending each data packet individually through the network. These packets are routed from the source, through the intermediate nodes of the network (called routers), and reassembled at the destination to reproduce the original message. The function of a router is to compare the destination address of a packet to all possible routes, in order to choose the appropriate one. A CAM is a good choice for implementing this lookup operation due to its fast search capability. CAM is also used in neural networks. The two main strategies available for implementing a CAM with a neural network architecture, feedback networks and two-stage CAMs, and in particular their ability to retrieve patterns from corrupted input data. The storage capacity of the Hopfield network is very poor although it can be improved with the use of an iterative algorithm, such as the threshold algorithm which is described. However, the possibility of generating spurious patterns always remains with feedback networks. Two-stage CAMs are much more efficient, provided that an appropriate algorithm is used for the input classification stage. Perceptron and least-mean squares algorithms need to be modified if they are to cope with corrupted input patterns, but the optimal classifier for the type of problem under consideration is the minimum-distance classifier (or Hamming network for binary patterns). Dynamic CMOS logic in general and domino logic in particular has a number of advantages to design high speed and low power CMOS circuits. However, the main difficulty with domino logic is that it can implement only non-inverted logic. To implement inverted polarity it is required to duplicate several circuit parts using inverted polarities of inputs and
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hence increasing area and power dissipation. With static CMOS logic, on the other hand, it is simple to realize gate with both inverted and non-inverted logic unlike dynamic CMOS logic [2]. Domino logic is known as a better logic for implementing high-speed CMOS circuits. However, domino circuits have some inherent problems like charge sharing, clock routing overhead, clock skew etc. Another difficulty with the domino logic is that it can only implement non-inverting functions. As domino logic cannot implement inverters driving other domino gates, all parts of the gate that follows an inverter has to be implemented again with opposite polarities of inputs, which increases area and power dissipation. The advantages of domino logic may come into question when there is a large number of inverters and having trapped in points where substantial duplication of domino gates is unavoidable.

1.2MOTIVATIONS

The speed of a CAM comes at the cost of increased silicon area and power consumption, two design parameters that designers strive to reduce. As CAM applications grow, demanding larger CAM sizes, the power problem is further exacerbated. Reducing power consumption, without sacrificing speed or area, is the main thread of recent research in large-capacity CAMs. The literature shows that a major portion of power is consumed in Match lines (ML) and search lines (SL). A lot of researches have been done to reduce the ML and SL power consumption. Previous works present some schemes such that low-swing scheme [3], [4], [5], selective precharge scheme [6], current-race scheme [7], current-saving scheme [8], [9] etc. The low-swing scheme reduces the ML power by reducing the ML voltage. The selective precharge scheme reduces match-line power consumption by breaking the search into two segments and observing that the second segment is rarely activated. The current-race scheme limits the ML voltage swing by VDD/2 and precharges the MLs to ground instead of VDD. In our scheme, as SL is not precharged, there is almost a 50% reduction in SL power consumption [1], compared to the precharge-high scheme [10], [11]. The current-saving scheme is the improved version of current race scheme which allocates less power to match decision involving a large number of mismatched bits. It is reported in a survey [1] that the current saving scheme consumes less power than other schemes [10], [6], [7]. So to compare our proposed schemes, we have selected the current-race and current-saving scheme. In our proposed schemes, the match-lines are precharged to ground at precharge stage unlike the conventional precharge high scheme so that power consumption in the matchlines is low. Another thing is that pre-charging the matchline eliminates the need of searchline precharge. So in the typical case, about 50% of the search data bits toggle from cycle to cycle, there is a 50% reduction in searchline power, compared to the precharge-high matchline-sensing schemes that have an SL precharge phase. Secondly, in our proposed charging control scheme, the charging of fully matched matchline is reduced from VDD to VDD/3 and this voltage is sensed by our proposed sense amplifier. This reduces the power
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consumption greatly. In the scheme with high noise margin, only probable matched matchlines are charged to almost VDD. Most of the matchline is not charged so much. So in most of the matchlines, power consumption is very low.

1.3OBJECTIVES

The objective of this investigation and research was to find out a way or scheme to design high speed and low power dynamic circuits. We specifically tried to design some good schemes for Content Addressable Memory (CAM). CAM is a special type of memory array which provides hardware search system where the information or data to be searched enters into the two-dimensional memory array and provides the search result (the address of memory where the data is found). To design very high speed CAM we have investigated the CAM cells, the charging controller and sense amplifiers. As satisfactory works is present on CAM cells, our objective was to design an appropiate scheme of charging controllers and sense amplifier which consume less power and operate in high speed. As most of the power is consumed in matchlines and matchlines are charged by the charging controller, the charging controller is responsible for most of the power consumption. So, one of our objectives was to design the charging controller intelligently. On the other hand, the higher the matchline voltage, the higher the power consumption. For that reason, our objective was to charge the matchline as VDD/3 and design a sense amplifier which can sense this voltage as a high.

1.4THESISORGANIZATION
Continued increase in leakage current of the transistors with the advancement of process technology, impacts the leakage power and noise sensitivity of dynamic circuits more than those of static circuits. This thesis proposes methods and techniques to achieve the goal of power-efficient design of CAM circuits used commonly in high-performance cache memory while improving or maintaining their area, performance and noise robustness. Chapter 2 describes different type of logic circuits-study of which is needed to understand the significance of dynamic circuits. As CAM is based on dynamic logic investigation of dynamic logic is very important. Chapter 3 underscores the significance of previous schemes and compares their performances and structure in details to reduce power consumption. Chapter 4 describes one of the proposed schemes. In this chapter, a scheme named charging control scheme is proposed. This work is also accepted and presented in International Conference on Solid State Device and Materials (SSDM) 2008, Tsukuba, Japan.

Chapter 5 describes another scheme which contains the simplified version of charging controller of the scheme described in chapter 4. It is also accepted in TENCON 2008, Hyderabad, India. Chapter 6 narrates a scheme which have high noise margin. The principle of this technique is carry coal to Newcastle. This scheme charges only a negligible number of matchline to VDD. For that reason, a high amount of power is saved. Finally, Chapter 7 presents a summary of proposed methods and techniques mentioned in the thesis for low-power CAM circuits in high-performance memory arrays. It also mentions suggestions for extending the current research for possible future work.

CHAPTER2 DIFFERENTTYPESOFLOGIC

CHAPTER 2 DIFFERENT TYPES OF LOGIC

2.1INTRODUCTION

In this chapter, different types of logic circuits are described. Logic circuits such as ratioed logic, CMOS logic, dynamic logic and domino logic are studied. This study is needed to realize the significance of dynamic circuits. As CAM is based on dynamic logic investigation of dynamic logic is very important.

2.2RATIOEDLOGIC

Ratioed logic is an attempt to reduce the number of transistors required to implement a logic function, often at the cost of reduced robustness and extra power dissipation.

2.2.1LoadResistanceRL
The main goal is to reduce the number of transistors at the cost of reduced robustness and extra power dissipation. This arrangement is not often used because of the large space requirements of resistors produced in a silicon substrate. If Pull down network is off, Static Power = 0. If Pull down network is on, then there is some Static Power dissipation.

VDD Resistive Load

RL

F Input PDN

VSS

Fig. 2. 1: Resistor Pull-up

2.2.2nMOSdepletionmodetransistorpullup
Power dissipation is high since rail to rail current flows when input = logical 1. Switching of output from 1 to 0 begins when input voltage exceeds the Vt of the pull down device.
VDD Depletion Load

F
Input PDN

VSS

Fig. 2. 2: nMOS depletion mode transistor pull up When switching the output from 1 to 0, the pull up device is non-saturated initially and this presents lower resistance through which to charge capacitive loads.

2.2.3nMOSenhancementmodepullup

If the gate of the pull-up transistor is connected to VDD then it is called nMOS enhancement mode pull up. Power Dissipation is high since current flows when input voltage = logical 1. Output voltage can never reach VDD (logical 1).
VDD

F
Input PDN

VSS

Fig. 2. 3: nMOS enhancement mode pull up .

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2.2.4PseudonMOSlogic
If we replace the depletion mode pull-up transistor of the standard nMOS circuits with a p-transistor with gate connected to VSS, we have a structure similar to the NMOS equivalent. This approach of the logic design is illustrated in the Fig. 2.4
VSS Input PMOS Load VSS PDN F VDD

Fig. 2. 4: Pseudo-nMOS Logic The circuit arrangements look and behave much like nMOS circuits and appropriate ratio rules must be applied.

2.3COMPLEMENTARYTRANSISTORPULLUP(CMOS)

In CMOS we use both the pull-up network and also the pull down network. So, there is no static power dissipation, because no current flow either for logical 0 or for logical 1 inputs. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p-channel is slower than the n-channel device.
VDD Inputs VSS PDN Output PUN

Fig. 2. 5: Complementary transistor pull-up (CMOS)

2.3.1ComponentsofTotalPowerDissipationinCMOSCircuits
One of the major design challenges in high-performance digital integrated circuits is the minimization of the total power dissipation. Total power consumption in digital CMOS circuits can be divided into three major components: a) Switching power or dynamic power, b) Short-circuit power and c) Static or leakage power. Equation 1.1 defines total power and its three components in a simplified form [1.1]

PowerTOTAL = PowerDYNAMIC + PowerSHORT CIRCUIT + PowerLEAKAGE PowerDYNAMIC = AF F C Vdd 2 PowerSHORTCIRCUIT = ( PowerLEAKAGE Trise + T fall 2 = I LEAKAGE Vdd ) Vdd I PEAK [1.1]

Dynamic power is a result of the power consumed in charging and discharging various device and wire capacitances in the circuit. As seen from Equation 1.1, this component of power depends on the switching activity factor (probability that a power consuming transition occurs) AF, clock frequency F, the capacitances C being charged or discharged and square of supply voltage, Vdd. In long channel transistors the dynamic power is the dominant component of the total power. However, this is not the case in advanced technologies, as leakage power is becoming a significant component of total power.

Current (betweenrails)

Vin

Fig. 2. 6: CMOS inverter current versus Vin

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Short-circuit power is dissipated when there is a direct conducting path between power supply (Vdd) and ground (Vss). Since the input signals to the logic gates have a nonzero/finite slope or edge rate, there is a direct path current between Vdd and Vss for a period of time during which both the PMOS and NMOS devices conduct simultaneously. The magnitude of this current is given by the actual transistor widths and the on-state saturation current (IDSAT). The duration for which the current flows depends on the signal rise and fall times and increases as the signal slopes degrade. The overall short-circuit power can be obtained by integrating the total current over the duration of short circuit and then multiplying with Vdd. In a simplified form it can be calculated as shown in Equation 1.1, where Trise and Tfall are the rise and fall times respectively and IPEAK is the peak short circuit current. Static or leakage power dissipation is due to the leakage current, ILEAKAGE that flows between power rails in the absence of any switching activity. Three major sources of leakage current are: a) current flowing through reverse biased P-N diode junctions of the transistors located between the source or drain and substrate, b) subthreshold leakage current between source and drain when gate-source voltage, Vgs, is smaller than the threshold voltage, Vt of the transistors and c) gate leakage current via the gate tunneling mechanism. Because of the quadratic dependence of dynamic power on Vdd, reducing this voltage is the most effective approach to minimize dynamic power dissipation. However, reducing the supply voltage necessitates the reduction of threshold voltage to avoid serious degradation of performance. Unfortunately, reducing threshold voltage causes the sub-threshold leakage current to increase exponentially.

2.4DYNAMICCIRCUITS

Ratioed circuits reduce the input capacitance by replacing the pMOS transistors connected to the inputs with a single resistive pull-up. The drawbacks of ratioed circuits includes slow resistive transitions, contention on the falling transitions, static power dissipation and a non-zero VOL. Dynamic circuits circumvent these drawbacks by using a clocked pull-up transistor rather than a pMOS that is always ON.

Precharge CLK

Evaluate

Precharge

Fig. 2. 7: Precharge and evaluation of dynamic gates.

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Dynamic circuit operation is divided into two modes, shown in Fig. 2.7. During precharge, the clock (CLK) is 0, so the clocked pMOS is ON and initializes the output Y high. During evaluation, the clock is 1 and the clocked pMOS turns OFF. The output may remain high or may be discharged low through the pull-down network.

CLK

Precharge Transistor Y

FOOT

Fig. 2. 8: Footed dynamic inverter

Dynamic circuits are the fastest commonly used circuit family because they have lower input capacitance and no contention during switching. They also have static power dissipation. However, they require careful clocking, consume significant dynamic power, and are sensitive to noise during evaluation. In Fig. 2.9 if the input is 1 during precharge, contention will take place because both the pMOS and nMOS transistors will be ON.

CLK Y Inputs PDN

Fig. 2. 9: Unfooted dynamic gates.

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When the input cannot be guaranteed to be 0 during precharge,an extra clocked evaluation transistor can be added to the bottom of the nMOS stack to avoid contention as shown in Fig. 2.10. The extra transistor is sometimes called a foot. Fig. 2.10 shows generic footed gates.

CLK Y Inputs PDN

Fig. 2. 10: Generalized footed gates.

Fig. 2.11 estimates the falling logical effort of both footed and unfooted dynamic gates. As usual, the pull-down transistors widths are chosen to give unit resistance. Precharge occurs while the gate is idle and often may take place more slowly. Therefore, the precharge transistor width is chosen for twice unit resistance. This reduces the capacitive load on the clock and the parasitic capacitance at the expense of greater rising delays.
Inverter

CLK Y A

CLK

Y A

gd=1/3 Pd=2/3

gd=2/3 Pd=3/3

Fig. 2. 11: Logical effort of footed and unfooted dynamic gates

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Footed gates have higher logical effort than their unfooted counterparts but are still an improvement over static logic. In practice, the logical effort of footed gates is better than predicted because velocity saturation means series nMOS transistors have less resistance than we estimate. The size of the foot can be increased relative to the other nMOS transistors to reduce logical effort of the other inputs at the expense of greater clock loading. Like pseudo-nMOS gates, dynamic gates are particularly well suited to wide NOR functions or multiplexers because the logical effort is independent of the number of inputs.

A fundamental difficulty with the dynamic circuits is the monotonicity requirement. While a dynamic gate is in evaluation, the inputs must be monotonically rising. That is, the input can start LOW and remain LOW, start LOW and rise HIGH, start HIGH and remain HIGH, but not start HIGH and fall LOW. Fig. 2.12 shows waveforms for a footed dynamic inverter in which the input violates monotonically. During precharge, the output is pulled HIGH. When the clock rises, the input is HIGH so the output is discharged LOW through the pull-down network, as happen in an inverter.

Violatesmonotonicity duringevaluation A

Precharge CLK

Evaluate

Precharge

Y Outputshouldrisebutdoesnot

Fig. 2. 12: Monotonicity problem

The input later falls LOW, turning off the pull-down network. However, the precharge transistor is also OFF, so the output floats, staying LOW rather than rising as it would in a normal inverter. The output will remain low until the next precharge step. In summary, the inputs must be monotonically rising for the dynamic gate to compute the correct function.

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Unfortunately, the output of a dynamic gate begins HIGH and monotonically falls LOW during evaluation. This monotonically falling output X is not a suitable input to a secong dynamic gate expecting monotonically rising signals as shown in Fig. 2.13. Dynamic gates sharing the same clock cannot be directly connected. This problem is often overcome with domino logic.

CLK X A

A=1 Precharge CLK Precharge

Evaluate

X Xmonotonicallyfallsduringevaluation

Y Yshouldrisebutcannot

Fig. 2. 13: Incorrect connection of dynamic gates.

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2.5DOMINOLOGIC
Domino logic circuits find wider applications in high performance microprocessors due to their superior speed and area characteristics as compared to static CMOS circuits. But their noise margins are low making them more prone to noise. Various leakage reduction techniques are applied to domino logic circuits also to reduce the leakage. As the technology is scaled below 130nm, noise margin becomes a critical issue and hence techniques that provide high noise immunity become necessary in order to have reliable circuits. The monotonicity problem can be solved by placing a static CMOS inverter between dynamic gates as shown in the figure. This converts the monotonically falling output into a monotonically rising signal suitable for the next gate. The dynamic- static pair together is called a domino gate. A single clock can be used to precharge and evaluate all the logic gates within the chain. Therefore, the static inverter is usually a HI-skew gate to favor this rising output. We may observe that precharge occurs in parallel, but evaluation occurs sequentially. A standard domino logic circuit with a keeper is as shown in Fig. 2.14. A standard domino logic circuit consists of an n-type dynamic logic block followed by a static inverter. During precharge, the output of the dynamic gate is charged to Vdd and the output of the inverter is set to 0.

Fig. 2. 14: Standard Domino Logic circuit

16

During evaluation, the inverter makes conditional transition from 0 to 1. If the output of the domino gate is fed to other domino gates, then it must be ensured that all inputs are set to 0 at the end of the precharge phase and the transitions during evaluation are only 0 to 1. Hence the dynamic node discharges only when the previous stage evaluates to 1 and a high fan-out is achieved due to the static inverter present at the output. To counteract the leakage issues and to establish a low impedance path, a bleeder transistor (keeper) is connected in the feedback path.
Width:min Length:L
CLK

X A

Fig. 2. 15: Weak keeper implementation

The function of the keeper is to compensate the charge lost due to the pull-down leakage paths. But the keeper is fully turned on at the beginning of the evaluation phase. When the pull down network is ON, then there exists a contention between this and keeper transistor, which degrades the speed of domino circuits. Traditionally, a minimum sized keeper is used to minimize delay and power degradation caused by the contention current. A small keeper, however, cannot provide necessary noise immunity for reliable operation in an increasingly noisy and noise-sensitive on-chip environment. Therefore, there is a tradeoff between the high speed/energy efficient operation and reliability in domino logic. Hence, keeper sizing is important in deep sub micron circuits.

17

 CHAPTER3 CONTENTADDRESSABLEMEMORY (CAM)REVIEW

18

Chapter 3
CONTENT ADDRESSABLE MEMORY (CAM) REVIEW
3.1INTRODUCTION

Content addressable memories (CAMs) are memories that can search the entire memory in parallel and output the location of entries that hold a match to the key value. Today the increased need for faster searches, larger table sizes and wider data widths, makes CAMs a more attractive solution to the less expensive RAM software solution. CAMs are now much needed where quick searches of a database, a list, or a pattem is in order. In fact, CAMs can be a determining factor for a wide range of applications such as local-area networks, file storage management, artificial intelligence, database management and pattern recognition. A Content-Addressable Memory (CAM) searches for data by its content and returns the address of the matching data. This feature is used extensively in applications such as internet routers to channel incoming packets towards their destination addresses contained in the packet header. Energy per search and search speed are two important metrics used to evaluate CAM performance[12]Content addressable memory (CAM), a high-performance lookup engine in many systems, is so power-consuming that any saving becomes very significant in the whole system. CAM has three major power-sinking sources: evaluation power, input transition power and clocking power, all of them are discussed in this research. After that, a new low-power CAM design is proposed here. Its implementation under 0.35-p m process operates at 83.3 MHz with power performance metric as 45.5fJ/bit/search or equivalently 372 mJ/bit/search/m for random inputs. Two modified circuit structures for binary static CAM cells are also proposed. We have proved that under most conditions cell layout is smaller by this modification. A Content Addressable Memory (CAM) compares input search data against a table of stored data, and returns the address of the matching data [13][17]. CAMs have a single clock cycle throughput making them faster than other hardware and software-based search systems. CAMs can be used in a wide variety of applications requiring high search speeds. These applications include parametric curve extraction [18], Hough transformation [19], Huffman coding/decoding [20], [21], LempelZiv compression [22][25], and image coding [26]. The primary commercial application of CAMs today is to classify and forward Internet protocol (IP) packets in network routers [27][32]. In networks like the Internet, a message such an as e-mail or a Web page is transferred by rst breaking up the message into small data packets of a few hundred bytes, and, then, sending each data packet individually through
19

the network. These packets are routed from the source, through the intermediate nodes of the network (called routers), and reassembled at the destination to reproduce the original message. The function of a router is to compare the destination address of a packet to all possible routes, in order to choose the appropriate one. A CAM is a good choice for implementing this lookup operation due to its fast search capability. However, the speed of a CAM comes at the cost of increased silicon area and power consumption, two design parameters that designers strive to reduce. As CAM applications grow, demanding larger CAM sizes, the power problem is further exacerbated. Reducing power consumption, without sacricing speed or area, is the main thread of recent research in large capacity CAMs. In this research, we survey developments in the CAM area at two levels: circuits and architectures. Before providing an outline of this research at the end of this section, we rst briey introduce the operation of CAM and also describe the CAM application of packet forwarding.

SL0

SL0

SL1 SL1 SL2

SL2 ML0

C ML1 Encoder Hit

ML2

C ML3

Input Search Data Drivers/Registers

Fig. 3. 1: Simple schematic model of a 4x3 CAM array showing the core memory cells, differential search lines, match lines and encoder Fig. 3.1 shows a simplied block diagram of a CAM. The input to the system is the search word that is broadcast onto the searchlines to the table of stored data. The number of bits in a CAM word is usually large, with existing implementations ranging from 36 to 144 bits. A typical CAM employs a table size ranging between a few hundred entries to 32K entries, corresponding to an address space ranging from 7 bits to 15 bits. Each stored word has a matchline that indicates whether the search word and stored word are identical (the match case) or are different (a mismatch case, or miss). The matchlines are fed to an encoder that generates a binary match location corresponding to the matchline that is in the match state. An encoder is used in systems where only a single match is expected. In CAM applications where more than one word may match, a priority encoder is used instead of a simple encoder. A priority encoder selects the highest priority matching location to map to the match result, with words in lower address locations receiving higher priority. In addition, there is often a hit signal (not shown in the gure) that ags the case in which there is no matching location in the CAM. The overall function of a CAM is to take a search word and
20

return the matching memory location. One can think of this operation as a fully programmable arbitrary mapping of the large space of the input search word to the smaller space of the output match location.

8M Memory Size (bit)

10k 1986 Year Fig. 3. 2: Profile of CAM capacity (log scale) versus year of publication [33][40] The operation of a CAM is like that of the tag portion of a fully associative cache. The tag portion of a cache compares its input, which is an address, to all addresses stored in the tag memory. In the case of match, a single matchline goes high, indicating the location of a match. Unlike CAMs, caches do not use priority encoders since only a single match occurs; instead, the matchline directly activates a read of the data portion of the cache associated with the matching tag. Many circuits are common to both CAMs and caches; however, we focus on large- capacity CAMs rather than on fully associative caches, which target smaller capacity and higher speed. Todays largest commercially available single-chip CAMs are 18 Mbit implementations, although the largest CAMs reported in the literature are 9 Mbit in size [33], [40]. As a rule of thumb, the largest available CAM chip is usually about half the size of the largest available SRAM chip. This rule of thumb comes from the fact that a typical CAM cell consists of two SRAM cells, as we will see shortly. Fig. 3.2 plots (on a logarithmic scale) the capacity of published CAM [33][40] chips versus time from 1985 to 2004, revealing an exponential growth rate typical of semiconductor memory circuits and the factor-of-two relationship between SRAM and CAM. 2005

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3.2CORECELLSANDMATCHLINESTRUCTURE

A CAM cell serves two basic functions: bit storage (as in RAM) and bit comparison (unique to CAM). Fig. 3.4 shows a NOR-type CAM cell [Fig. 3.3(a)] and the NAND-type CAM cell [Fig. 3.3(b)]. The bit storage in both cases is an SRAM cell where cross-coupled inverters implement the bit-storage nodes D and DB . To simplify the schematic, we omit the nMOS access transistors and bitlines which are used to read and write the SRAM storage bit. Although some CAM cell implementations use lower area DRAM cells [3.27], [3.31], typically, CAM cells use SRAM storage. The bit comparison, which is logically equivalent to an XOR of the stored bit and the search bit is implemented in a somewhat different fashion in the NOR and the NAND cells.

3.2.1StructureofNORCell

A NOR Cell implements the comparison between the complementary stored bit, D (and DB), and the complementary search data on the complementary searchline, SL (and SLB), using four comparison transistors, M1 through M4, which are all typically minimumsize to maintain high cell density. These transistors implement the pull down path of a dynamic XNOR logic gate with inputs SL and D. Each pair of transistors, M1/M3 and M2/M4, forms a pull down path from the matchline, ML, such that a mismatch of SL and D

Fig. 3. 3: CAM core cells for (a) 10-T NOR-type CAM and (b) 9-T NAND-type CAM. The cells are shown using SRAM-based data-storage cells. activates least one of the pull down paths,connecting ML to ground. A match of SL and D disables both pull down paths, disconnecting ML from ground. The NOR nature of this cell becomes clear when multiple cells are connected in parallel to form a CAM word by shorting the ML of each cell to the ML of adjacent cells. The pull down paths connect in parallel resembling the pull down path of a CMOS NOR logic gate. There is a match condition on a given ML only if every individual cell in the word has a match.

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3.2.2StructureofNANDCell

The NAND cell implements the comparison between the stored bit, D, and corresponding search data on the corresponding searchlines, (SL, SLB), using the three comparison transistors M1, MD and MDB, which are all typically minimum-size to maintain high cell density. We illustrate the bit-comparison operation of a NAND cell through an example. Consider the case of a match when SL=1 and D=1. Pass transistor MD is ON and passes the logic 1 on the SL to node B. Node B is the bit-match node which is logic 1 if there is a match in the cell. The logic 1 on node B turns ON transistor M1. Note that is also turned ON in the other match case when SL=0 and D=0 . In this case, the transistor MDB passes a logic high to raise node B. The remaining cases, where SLD result in a miss condition, and accordingly node B is logic 0 and the transistor M1 is OFF. Node B is a pass-transistor implementation of the XNOR SLD function. The NAND nature of this cell becomes clear when multiple NAND cells are serially connected. In this case, the MLn and MLn+1 nodes are joined to form a word. A serial nMOS chain of all the Mi transistors resembles the pull down path of a CMOS NAND logic gate. A match condition for the entire word occurs only if every cell in a word is in the match condition. An important property of the NOR cell is that it provides a full rail voltage at the gates of all comparison transistors. On the other hand, a deciency of the NAND cell is that it provides only a reduced logic 1 voltage at node B, which can reach only VDD - Vtn sswhen the searchlines are driven to VDD (where VDD is the supply voltage and Vtn is the nMOS threshold voltage).

3.2.3TernaryCells

Usually two types of ternary cell are used. The NOR and NAND cells that have been presented are binary CAM cells. Such cells store either a logic 0 or a logic 1.Ternary cells, in addition, store an X value. The X value is a dont care, that represents both 0 and 1, allowing a wildcard operation. Wildcard operation means that an X value stored in a cell causes a match regardless of the input bit. As discussed earlier, this is a feature used in packet forwarding in Internet routers. A ternary symbol can be encoded into two bits according to Table 2.2. We represent these two bits as D and DB. Note that although the D and DB are not necessarily complementary, we maintain the complementary notation for consistency with the binary CAM cell. Since two bits can represent 4 possible states, but ternary storage requires only three states, we disallow the state where D and DB are both zero. To store a ternary value in a NOR cell, we add a second SRAM cell, as shown in Fig. 3.5. One bit, D, connects to the left pulldown path and the other bit, DB, connects to the right pull down path, making the pull down paths independently controlled.We store an X by setting both D and DB equal to logic 1, which disables both pull down paths and forces the cell to match regardless in the inputs. We store a logic 1 by setting D=1 and DB=0 and store a logic 0 by setting D=0 and DB=1. In addition to storing an X, the cell allows searching for an X by setting both SL and SLB to logic 0. This is an external dont care that forces a match of a bit regardless of the stored bit.

23

Table 3. 1: Truth Table for NOR Cell Stored Value Stored D 0 1 X 0 1 1 D 1 0 1 Search D 0 1 0 D 1 0 0

Table 3. 2: Truth Table for NAND Cell Stored Value Stored Bit D 0 1 x x 0 1 0 1 M 0 0 1 1 Search Bit SL 0 1 1 1 SL 1 0 1 1

Fig. 3. 4: Structure of Ternary core cells for (a) NOR-type (b) NAND-type CAM [41], [42].

24

Although storing an X is possible only in ternary CAMs, an external X symbol possible in both binary and ternary CAMs. In cases where ternary operation is needed but only binary CAMs are available, it is possible to emulate ternary operation using two binary cells per ternary symbol. As a modication to the ternary NOR cell of Fig.3.4(a), propose implementing the pull down transistors M1-M4 using pMOS devices and complementing the logic levels of the searchlines and matchlines accordingly. Using pMOS transistors (instead of nMOS transistors) for the comparison circuitry allows for a more compact layout, due to reducing the number of spacings of p-diffusions to n-diffusions in the cell. In addition to increased density, the smaller area of the cell reduces wiring capacitance and therefore reduces power consumption. The tradeoff that results from using minimum-size pMOS transistors, rather than minimum-size nMOS transistors, is that the pulldown path will have a higher equivalent resistance, slowing down the search operation. A NAND cell can be modied for ternary storage by adding storage for a mask bit at node M, as depicted in Fig. 3.4(b) [41], [42]. When storing an X, we set this mask bit to 1. This forces transistor Mmask ON, regardless of the value of D, ensuring that the cell always matches. In addition to storing an X, the cell allows searching for an X by setting both SL and SLB to logic 1. Table 2.2 lists the stored encoding and search-bit encoding for the ternary NAND cell. Further minor modications to CAM cells include mixing parts of the NAND and NOR cells, using dynamic-threshold techniques in silicon-on-insulator (SOI) processes, and alternating the logic level of the pull down path to ground in the NOR cell [44][46]. Currently, the NOR cell and the NAND cell are the prevalent core cells for providing storage and comparison circuitry in CMOS CAMs. For a comprehensive survey of the precursors of CMOS CAM cells refer to [47].

3.3MATCHLINESENSINGSCHEMES
This section reviews matchline sensing schemes that generate the match result. First, we review the conventional precharge high scheme, then introduce several variations that save power.

3.3.1Conventional(PrechargeHigh)MatchlineSensing
We review the basic operation of the conventional precharge-high scheme and look at sensing speed, charge sharing, timing control and power consumption.

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3.3.1.1BasicOperation
The basic scheme for sensing the stateof the NOR matchline is rst to precharge high the matchline and then evaluate by allowing the NOR cells to pull down the match-lines in the case of amiss, or leave the matchline high in the case of a match. Fig. 3.5(a) shows, in schematic form, an implementation of this matchline-sensing scheme. Fig. 3.5(b) shows the signal timing which is divided into three phases: SL precharge, ML precharge, and ML evaluation. The operation begins by asserting slpre to precharge the searchlines low, disconnecting all the pull down paths in the NOR cells.With the pull down paths disconnected, the operation continues by asserting mlpreb to precharge the matchline high. Once the matchline is high, both slpre and mlpreb are de-asserted. The ML evaluate phase begins by placing the search word on the searchlines. If there is at least one single-bit miss on the matchline, a path (or multiple paths) to ground will discharge the matchline, ML, indicating amiss for the entire word, which is output on the MLSA sense-output node, called

Fig. 3. 5: (a) the schematic with precharge circuitry for matchline sensing using the precharge-high scheme, and (b) the corresponding timing diagram showing relative signal transitions. [34]

26

MLso. If all bits on the matchline match, thematchline will remain high indicating a match for the entire word. Using this sketch of the precharge high scheme, we will investigate the performance of matchline in terms of speed, robustness, and power consumption. The matchline power dissipation is one of the major sources of power consumption in CAM.

3.3.1.2Matchlinepower

In a typical system, the number of misses is expected to be much greater than the number of matches; thus, using a dynamic NAND structure results in a signicant reduction in power. Fig. 3.6 demonstrates the power advantages of a NAND architecture versus a NOR. 1A NAND match-line architecture is considerably slower than it has NOR counterpart, especially for wide words.

Fig. 3. 6: Matchline power for NAND and NOR architecture [33]

3.3.1.3ChargeSharing
There is a potential charge-sharing problem depending on whether the CAM storage bits D and DB are connected to the top transistor or the bottom transistor in the pulldown path.

27

Fig. 3. 7: Two possible congurations for the NOR cell: (a) the stored bit is connected to the bottom transistors of the pulldown pair, and (b) the stored bit is connected to the top transistors of the pulldown pair.

Fig. 3.7 shows these two possible congurations of the NOR cell. In the conguration of Fig. 3.7(a), there is a charge-sharing problem between the matchline, ML, and nodes X1 and X2. Charge sharing occurs during matchline evaluation, which occurs immediately after the matchline precharge-high phase. During matchline precharge, SL and SLB are both at ground. Once the precharge completes, one of the searchlines is activated, depending on the search data, causing either M1 or M2 to turn ON. This shares the charge at node X1 or node X2 with that of ML, causing the ML voltage, VML, to drop, even in the case of match, which may lead to a sensing error. To avoid this problem, designers use the conguration shown in Fig.3.7 (b), where the stored bit is connected to the top transistors. Since the stored bit is constant during a search operation, charge sharing is eliminated.

3.3.1.4PowerConsumption
The dynamic power consumed by a single matchline that misses is due to the rising edge during precharge and the falling edge during evaluation, and is given by the equation Pmiss = fCMLVDD2 Where f is the frequency of search operations. In the case of a match, the power consumption associated with a single matchline depends on the previous state of the matchline; however, since typically there are only a small number of matches we can neglect this power consumption. Accordingly, the overall matchline power consumption of a CAM block with w matchlines is PML=wPmiss

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3.4LOWSWINGSCHEMES

The ML power consumption is an important issue and challenge to the researchers. Researchers proposed many techniques of reducing ML power consumption. One method of reducing the ML power consumption, and potentially increasing its speed, is to reduce the ML voltage swing [33], [50]. The reduction of power consumption is linearly proportional to the reduction of the voltage swing, resulting in the modied power equation PML=wfCMLVDDVMLswing Where VMLswing is the voltage swing of the ML. The main challenge addressed by various low-swing implementations is using a low-swing voltage without resorting to an externally generated reference voltage. Fig.3.8 is a simplied schematic of the matchline sensing scheme of [33], which saves power by reducing swing. The matchline swing is reduced from the full supply swing to mV. Precharge to VLow =300 mV is accomplished by associating a tank capacitor, Ctank, with every matchline. The precharge operation (assertion of pre signal) charges the tank capacitor to VDD and then uses charge sharing (enabled by eval signal) to dump the charge onto the matchline. and is set to be equal to 300 mV in the design [33]. In the case of a miss, the matchline discharges through the CAM cell(s) to ground, whereas in the case of match, the matchline remains at the precharge level.Matchline evaluation uses a sense amplier that employs transistor ratios to generate a reference level of about VLow /2 =150mV. This sense amplier is shown in generic form in the gure. A similar charge-sharing matchline scheme was also described in [50].

Fig. 3. 8: Low-swing matchline sensing scheme of [33].

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3.5CURRENTRACESCHEME
Current-Race saving is an important scheme for the CAM architecture. Fig. 3.9(a) shows a simplied schematic of the current-race scheme [51]. This scheme precharges the matchline low and evaluates the matchline state by charging the matchline with a current IML supplied by a current source. The signal timing is shown in Fig. 3.9(b). The precharge signal, mlpre, starts the search cycle by precharging thematchline low. Since the matchline is precharged low, the scheme concurrently charges the searchlines to their search data values, eliminating the need for a separate SL precharge phase required by the precharge-high scheme of Fig. 3.5(b). Instead, there is a single SL/ML precharge phase, as indicated in Fig. 3.9(b). After the SL/ML precharge phase completes, the enable signal, enb, connects the current source to the matchline. A matchline in the match state charges linearly to a high voltage, while a matchline in the miss state charges to a voltage of only IML*RML /m, where m denotes the number of misses in cells connected to the matchline. By setting the maximum voltage of a miss to be small, a simple matchline sense amplier easily differentiates between a match state and a miss state and generates the signal MLso. As shown in Fig. 3.9, the amplier is the nMOS transistor, Msense, whose output is stored by a half-latch. The nMOS sense transistor trips the latch with a threshold of Vtn. After some delay, matchlines in the match state will charge to slightly above tripping their latch, whereas matchlines in the miss state will remain at a much smaller voltage, leaving their latch in the initial state. A simple replica matchline (not shown) controls the shutoff of the current source and the latching of the match signal. We derive the power consumption of this scheme by rst noting that the same amount of current is discharged into every matchline, regardless of the state of the matchline. Looking at the match case for convenience, the power consumed to charge a matchline to slightly above Vtn is Pmatch=fCMLVDDVtn Since the power consumption of a match and a miss are identical, the overall power consumption for all w matchlines is PML=wPmatch This equation is identical to the low-swing scheme (previous equation) with VMLswing=Vtn. The benets of this scheme over the precharge-high schemes are the simplicity of the threshold circuitry and the extra savings in searchline power due to the elimination of the SL precharge phase which is discussed

30

Fig. 3. 9: (a) Circuit implementation including precharge circuitry and (b) a timing diagram for a single search cycle. For current-race matchline sensing [51]. Changing CAM cell configuration is an important feature of current racing scheme. The current-race scheme also allows changing the CAM cell conguration due to the fact that the matchline is precharged low. With precharge low, there is no charge-sharing problem for either CAM cell conguration of Fig.3.6, since the ML precharge level is the same as the level of the intermediate nodes X1 and X2. Rather than to avoid charge sharing, the criterion that determines which cell to use in this case is matching parasitic capacitances between MLs. In the conguration of Fig. 3.7(b), the parasitic load on a matchline depends on the ON/OFF state of M1 and of M2. Since different cells will have different stored data, there will be variations in the capacitance CML among the MLs. However, in the conguration of Fig.3.7(a), the variation of parasitic capacitance on the matchline depends only on the states of SL and SLB which are the same for all cells in the same column. Thus, the conguration of Fig. 3.7(a) maintains good matching between MLs and prevents possible sensing errors due to parasitic capacitance variations.

3.6SELECTIVEPRECHARGESCHEME

Selective precharge scheme came considering the non uniform ML power consumption. The matchline-sensing techniques we have seen so far, expend approximately the same amount of energy on every matchline, regardless of the specic data pattern, and whether there is a match or a miss. We now examine three schemes that allocate power to matchlines nonuniformly. The rst technique, called selective precharge, performs a match operation on the rst few bits of a word before activating the search of the remaining bits
31

[52]. For example, in a 144-bit word, selective precharge initially searches only the rst 3 bits and then searches the remaining 141 bits only for words that matched in the rst 3 bits. Assuming a uniform random data distribution, the initial 3-bit search should allow only 3 words to survive to the second stage saving about 88% of the matchline power. In practice, there are two sources of overhead that limit the power saving. First, to maintain speed, the initial match implementation may draw a higher power per bit than the search operation on the remaining bits. Second, an application may have a data distribution that is not uniform, and, in the worst-case scenario, the initial match bits are identical among all words in the CAM, eliminating any power saving. Fig. 3.10 is a simplied schematic of an example of selective precharge similar to that presented in the original paper [52]. The example uses the rst bit for the initial search and the remaining n-1 bits for the remaining search. To maintain speed, the implementation modies the precharge part of the precharge-high scheme [of Fig. 3.7(a) and (b)]. The ML is precharged through the transistor M1, which is controlled by the NAND CAM cell and turned on only if there is a match in the rst CAM bit. The remaining cells are NOR cells.

Fig. 3. 10: Sample implementation of the selective-precharge matchline technique [52]. Note that the ML of the NOR cells must be pre-discharged (circuitry not shown) to ground to maintain correct operation in the case that the previous search left thematchline high due to a match. Thus, one implementation of selective precharge is to use this mixed NAND/NOR matchline structure. Selective precharge is perhaps themost commonmethod used to save power on matchlines [34], [53][57] since it is both simple to implement and can reduce power by a large amount in many CAM applications.

3.7PIPELININGSCHEME

More generally, an implementation may divide the matchline into any number of segments, where a match in a given segment results in a search operation in the next segment but a miss terminates the match operation for that word. A design that uses multiple matchline segments in a pipelined fashion is the pipelined matchlines scheme [58], [59]. Fig. 3.11(a) shows a simplied schematic of a conventional NOR matchline structure where all cells are connected in parallel. Fig. 3.11(b) shows the same set of cells as in Fig. 3.11(a), but with the matchline broken into four matchline segments that are serially evaluated. If any stage misses, the subsequent stages are shut off, resulting in power saving. The drawbacks of this scheme are the increased latency and the area overhead due to the pipeline stages.
32

Fig. 3. 11: Pipelined matchlines reduce power by shutting down after a miss in a stage By itself, a pipelined matchline scheme is not as compelling as basic selective precharge; however, pipelining enables the use of hierarchical searchlines, thus saving power. Another approach is to segment the matchline so that each individual bit forms a segment. Thus, selective precharge operates on a bit-by-bit basis. In this design, the CAM cell is modied so that thematch evaluation ripples through each CAM cell. If at any cell there is a miss, the subsequent cells do not activate, as there is no need for a comparison operation. The drawback of this scheme is the extra circuitry required at each cell to gate the comparison with the result from the previous cell.

Fig. 3. 12: Simulated wave forms in the pipelined match-line architecture for (a) the fullmatch case consisting of a match in every stage, and (b) a miss case where the third stage results in a miss and turns off the subsequent stages.[58]
33

Fig 3.12 shows the simulated waveforms of the ML segments in the pipelined ML scheme. Fig 3.12 shows a full match as indicated by the rising ML in every segment along with the corresponding full-rail output of the MLSA. Fig 3.12(b) shows an example of a word that misses in the third stage as indicated by the lack of an MLSA output pulse. In this example, the ML sensing circuitry of the fourth and fifth segments is not activated, hence saving power.

3.8CURRENTSAVINGSCHEME
The current-saving scheme [60], [61] is another data-dependent matchline-sensing scheme which is a modied form of the current-race sensing scheme. Recall that the currentrace scheme uses the same current on each matchline, regardless of whether it has a match or a miss. The key improvement of the current-saving scheme is to allocate a different amount of current for a match than for a miss. In the current-saving scheme matches are allocated a larger current and misses are allocated a lower current. Since almost every matchline has a miss, overall the scheme saves power.

Fig. 3. 13: Current-saving matchline-sensing scheme Fig.3.13 shows a simplied schematic of the current-saving scheme. The main difference from the current-race scheme as depicted in Fig. 3.9 is the addition of the currentcontrol block. This block is the mechanism by which a different amount of current is allocated, based on a match or a miss. The input to this current-control block is the matchline voltage, VML, and the output is a control voltage that determines the current, IML, which charges the matchline. The current-control block provides positive feedback since higher VML results in higher IML, which, in turn, results in higher VML.

34

3.9CONCLUSION
From the above discussion of previous Content addressable Memory (CAM) it is clearly shown that the main concern was power and speed. The researchers gave a good importance to these two factors and improved the power and speed significantly. Scheme simplicity and noise immunity are other two factors. Researchers gave importance to these two factors too. The previous result from the simulation that the researchers performed is shown below in table format.

Table 3. 3: Comparison between the schemes[62] Scheme ML energy fj/bit/search Conventional Low swing Current race Selective precharge Pipelining Current saving 9.5 4.2 5.5 5.6 5.8 4.3 3.9 3.1 3.7 3.5 3.8 3.7 + + + Cycle time(ns) Noise Scheme simplicity ++ + + --

35

 CHAPTER4 PROPOSEDCHARGINGCONTROL SCHEME&SENSEAMPLIFIER

36

CHAPTER 4 PROPOSED CHARGING CONTROL SCHEME & SENSE AMPLIFIER

4.1INTRODUCTION

Content-addressable memory (CAM) is a storage device that searches for the matching data by content and returns the address of the matching data. Due to the rising demand of CAM for high speed search capability in various applications, the size as well as power consumption of CAM arrays continue to rise. A lot of researches have been done to reduce the power consumption and to increase the speed. Previous works present some schemes such as selective-precharge scheme [63], current-race scheme [64], current-saving scheme [65], [66], etc. It is reported in a survey [67] that the current-saving scheme consumes less power than other schemes [63], [64], [68]. In this work, we proposed a simplified match-line charging control scheme. Comparison with the current-race and current-saving schemes shows match-line energy reduction of over 50% and speed improvement of over 3 times.

4.2PROPOSEDCHARGECONTROLLINGSCHEME
Fig. 4.1(a) shows the basic architecture of the proposed charge controlling scheme. Here, the array of CAM cells stores the data entries; search data register stores the search word; each charge controller block controls the charging and discharging process of the respective match-line (ML); and the sense amplifier (SA) senses the ML voltage and gives the final match/miss decision. Fig. 4.1(b) shows the internal circuit of conventional NORtype Ternary CAM (TCAM) cell which is less susceptible to failure due to the process variation as compared to NAND-type cell [69]. At the beginning of each search cycle, all MLs are pre-discharged to ground by the charging controller. During the evaluation stage, the search data register broadcasts the search data to the search-lines (SLs). If SL resembles stored bit D or the stored bit is X (dont care), the ML has no discharging path to ground and the path remains in the high-impedance state. If SL does not resemble D, the ML has a discharging path (through either transistors T1-T2 path or T3-T4 path) to ground. So, in a ML, the number of discharging paths is equal to the number of mismatches. Fig. 4.2 shows the proposed charging controller. Here, at the beginning of search cycle, ML is pre-discharged to ground by a high MLP. The transistor M2 is turned ON by a low MLP and M5 is OFF by a low MLC; this causes M3 to be turned OFF. Therefore, charging of ML through M3 remains prohibited during the pre-discharging of ML. During the evaluation stage, MLP is switched to low so that both M1 and M2 turn OFF. At the same time, MLC is switched to high so that charging of ML through M3 begins.
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If the CAM cell data of this ML is fully matched with the search-line data, then, there is no discharging path through the CAM cell. So, charging to the fully matched match-line (denoted by ML0) is faster than the partially matched match-line. MLC is kept high until the voltage of ML0 is enough to turn M4 ON; this causes the gate of the transistor M3 to be low and charging to ML0 continues via M3. As the voltage of match-line, ML0 reaches about VDD/3 and MLC is low, M6 becomes fully ON and M7 becomes partially ON. The end result is no more charging of ML through M3. The achieved voltage (~VDD/3) of ML0 is high enough to be sensed as a high level for the proposed sense amplifier (SA). Now, the matchline which has one miss is denoted by ML1 and this ML is hardest to detect as a miss. As charging to ML1 is slower than ML0, the voltage of ML1 is not enough to be sensed as a high level by the SA.

Fig. 4. 1: Structure of the CAM of the proposed scheme: (a) basic architecture and (b) NORtype TCAM cell used in the scheme.

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Fig. 4. 2: Internal circuit of the charging controller.

Fig. 4.3 shows the proposed sense amplifier (SA). During precharge stage, the node SN is precharged to high through MS1. During the evaluation stage, when the voltage of ML is slightly above VDD/3, the transistor MS2 turns ON. So, the node SN begins to discharge and MLS begins to rise. As MLS reaches high level, the transistor MS3 turns ON resulting in faster discharge of node SN. Transistor MS4 is used to initialize the output MLS to ground at the beginning of each search cycle.

4.3SIMULATIONRESULTSANDANALYSIS
The proposed scheme along with current-race and current-saving schemes are simulated using HSpice in the same 64 72 TCAM for TSMC 0.18m CMOS process with the supply voltage of 1.8V. Fig. 4.4 shows the simulation result for our design. At the beginning of a search cycle, MLP is high for 0.39 ns so that previously charged MLs can discharge to ground. Then, MLP is switched to low and MLC is switched to high for 0.33ns. As the voltage of ML0 rises up to 0.65V and MLC is low, the charging is stopped and the voltage of ML0 remains unchanged. The proposed sense amplifier senses this voltage as a match and output MLS0 turns to a full high level. On the other hand, the voltage of the ML1 rises up to 0.46V and then, degrades through the discharging path. The SA senses this voltage as a miss and results a low MLS1. As the difference between the maximum ML0 and ML1 (worst-case match-line) is 190 mV, even for a large process variation, our scheme will produce the correct search results. Table 4.1 shows the comparative search energy and performance among the schemes. It shows that ML energy reduction is 57% and 54% compared to the current-race and currentsaving schemes respectively and the speed is 3.13 times that of the both schemes.
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The major difference between previous schemes [64]-[66] and our scheme is that we have used only one PMOS for charging the ML while previous schemes use two PMOS in series. So, the equivalent resistance is half of the previous schemes. Equivalent capacitance is also reduced. As a result, speed of the circuit increases. The basic difference between previous SA design [64]-[66] and the proposed SA is the switching threshold of SA. The proposed SA can sense a stable 0.6 V as a high level, whereas the previous SAs use ~1V as a switching voltage. So, the proposed scheme need not further charging after 0.6V (equals to VDD/3) at ML0 is achieved. So, this scheme reduces a large amount of dynamic and leakage power, while a larger voltage swing of about VDD/2 in [64]-[66] causes a higher power consumption.

MLP

MS1

MLS SN

ML MS2 MS3 MS4

MLP

Fig. 4. 3: Proposed sense amplifier (SA)

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Fig. 4. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched), ML1 (one-bit miss), ML2 (two-bit miss), MLC and MLP.

Table 4. 1: Comparison of Different Schemes

Schemes Current-race [64] Current-saving [65],[66] This work

ML Energy (fJ/bit/ search) 3.56 3.32 1.53

SL Energy (fJ/bit/ search) 0.65 0.65 0.62

Minimum Cycle Speed, 1/T time, T (MHz) (ns) 3.60 3.60 1.15 278 278 870

4.4CORNERSIMULATIONOFTHESCHEME

To test the reliability of the proposed scheme, we have simulated the proposed scheme in two extreme corners which we defined as follows: the fast corner with low threshold voltage, high VDD and low temperature (FHL) and the slow process corner with high threshold voltage, low VDD and high temperature (SLH). Simulation results reveal that the proposed scheme works satisfactorily in the fast process (FHL) corner with -10% threshold votlage, +5% VDD and at a temperature of 273 K as well as in the slow process (SLH) corner with +10% threshold votlage, -5% VDD and at a temperature of 343 K. The simulation results are shown in Fig. 4.5 and Fig. 4.6.

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Fig. 4. 5: Corner Simulation results for FHL (when threshold voltage= -10%,VDD=+5%, and temparature=273K)

Fig. 4. 6: Corner Simulation results for SLH (when threshold voltage= +10%,VDD=-5%, and temparature=343K)

4.5CONCLUSION
This work present a novel CAM scheme in which ML energy reduces by over 50% compared to previous current-race and current-saving schemes while the speed increases by over 3 times.

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 CHAPTER5 PROPOSEDSIMPLIFIEDDESIGNOF CHARGINGCONTROLLER

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CHAPTER 5 PROPOSED SIMPLIFIED DESIGN OF CHARGING CONTROLLER

5.1INTRODUCTION

Content-addressable memory (CAM) is a storage device that searches for the matching data by content and returns the address at which the matching data was found [70], [71]. CAM is used extensively in applications such as network address translation, pattern recognition, parametric curve extraction [72], Hough Transformation [73], image coding [74], etc. As the applications and usges of CAM continue to expand, especially in the field of network routing applications, the CAM array size as well as the total power consumption is becoming larger. Hence, the main focus in the design of CAM arrays has been given to the reduction of the power consumption while at the same time increasing the speed of search without sacrificing the robustness [75]. Fig. 5.1 shows the simplified block diagram of a conventional CAM architecture, consisting of an array of storage CAM cells, a search data register, and a column of sense amplifiers. The search data is sent to the search-lines (SLs) and compared bitwise with the stored word in the storage CAM cells. Conventionally, the match-lines (MLs) are precharged to high and the search-lines are precharged to ground [76], [77]. When the search data do not resemble the stored data, the precharged MLs are discharged. Since, only the matched MLs remain high and only one or a few rows of stored words match with the search data, a significant amount of power is consumed in discharging and charging the large number of MLs in CAM arrays. A number of techniques at the circuit level has been proposed in the past for reducing the power consumption in high-perfromance CAM arrays; these include low-swing schemes [78]-[79], selective precharge scheme [80], current-race scheme [81], and current-saving schemes [82], [83]. The low-swing scheme reduces the ML power by reducing the ML swing voltage. The selective precharge scheme reduces ML power consumption by breaking the search into two segments and observing that the second segment is rarely activated. The current-race scheme limits the ML voltage swing by VDD/2 and pre-discharge the MLs to ground instead of precharging to VDD. In the current-race scheme, as SL is not precharged, there is a 50% reduction in SL power consumption [75], compared to the precharge-high scheme [76], [77]. The current-saving scheme is the improved version of current-race scheme which allocates less power to match decision involving a large number
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of mismatched bits. It is reported in a survey [75] that the current-saving scheme consumes less power than other schemes [76], [80], [81]. So, to compare our proposed scheme with existing ones, we have selected the current-race and current-saving schemes as the baselines.

Fig. 5. 1: Simplified conventional CAM architecture In this work, we propose a new ML charging technique where the MLs are predischarged to ground at the beginning of each search cycle. During the evaluation stage, the MLs are charged towards VDD until the voltage of the fully matched ML approaches the sense threshold voltage of the sensing unit. This sensing unit is proposed by the same authors in [84]. This sensing unit can sense a stable voltage of about VDD/3 as a high and provide the match decision. As the voltage swing of ML is limited to about VDD/3, a large amount of dynamic as well as leakage power is saved. To speed up the charging and discharging process of MLs, we use only one PMOS and one NMOS device while previous schemes [81]-[83] use two PMOS devices for charging each match-line. The overall effect of the proposed scheme is a 55% ML power reduction compared to the current-race scheme, 51.8% reduction compared to the current-saving scheme, and 68% reduction in minimum cycle time. The remainder of this work is organized as follows: section II describes the operation of our proposed scheme in details. Section III presents the simulation results and analysis along with comparison among different schemes. Section IV provides the conclusion.

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5.2PROPOSEDMLCHARGINGTECHNIQUE

Fig. 5.2(a) shows the architecture of a CAM array using the proposed ML charging technique. The array of CAM cells stores the data words and the search data register stores the word to be searched. Each ML has its own charging and sensing block which has a charging and sensing unit. The charging unit controls the charging and discharging of MLs; the sensing unit senses the ML voltage and generates the final full-swing output in case of a match. We have used NOR-type Ternary CAM (TCAM) cell in our study; NOR-type is preferred over NAND-type because of the its less susceptibility to failure due to the variation of process, temperature and supply voltage [85]; also, NOR-type cell provides a full rail voltage at the gates of all comparison transistors [75]. Another disadvantage of NAND-type cell is that it needs unacceptably long search time that increases quadratically with the number of TCAM cells in series [83]. Fig. 5.2(b) shows the internal circuit of a NOR-type Ternary CAM (TCAM) cell. At the beginning of search cycle, all the MLs are reset to ground by the charging unit of charging and sensing block. This reset technique of ML eliminates the need for SL reset, since enabling pull-down path in the NOR cell does not interfere with ML precharge [71], [81]. During the evaluation stage, the search data register broadcasts the search data to the SLs. If SL resembles stored bit D or the stored bit is X (dont care), the ML has no discharging path to ground. If SL does not match D, the ML has a conducting path to ground. If there is at least one miss among all the CAM cells connected to each ML, there will be a discharging path to ground through that CAM cell. Number of discharging path is equal to the number of mismatches. The charging unit allows all the MLs to charge for a period determined by the time it takes the ML voltage of a matched ML to reach sensing threshold of the sensing unit. As the fully matched ML, where all the CAM cells connected to it have a match, has no path to ground, it is charged at a higher rate than the MLs that have at least one miss. The outputs MLS0, MLS1 etc. of sensing unit turn to high for matched MLs and remain low for missed MLs. Fig. 5.3 shows the ML charging unit proposed in this work and the sensing unit proposed by the same authors in [84]. At the beginning of each search cycle, each ML is reset to ground by a high MLP through transistor M1; at this stage, MLC is kept high. After the precharge stage is complete, MLC is switched to low to begin the charging of the MLs. If there is a match in one or more MLs, then the voltage of those matched MLs will be high enough to turn ON the transistor M3 in the sensing unit, before the MLC control signal is switched to high. As the charging of the miss-matched MLs is slower than the fully matched ML, other MLs which have at least one mismatch will not rise to the extent to turn the transistor M3 ON. Hence, only for the fully matched MLs, the transistor M3 will be ON; as there is no path to discharge for the fully matched MLs other than small leakage current, the voltage of those MLs will remain almost at the same voltage when MLC was switched to high. For the partially matched MLs, the voltage of the MLs will degrade due to the discharge through one or more discharging paths.

46

Fig. 5. 2: Structure of the CAM array with the proposed scheme: (a) the basic architecture and (b) internal circuit of the NOR-type TCAM cell used in this scheme. Here the usual SRAM access transistor and associated bitlines are omitted for simplicity.

Fig. 5. 3: The ML charging unit proposed in this work and the sensing unit proposed in [84].
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In the sensing unit shown in Fig. 5.3, the feedback circuit consisting of the inverter and transistor M5 is used to speed up the sensing faster. Transistor M6 is used for predischarging the output node MLS of the sensing unit to ground before the start of the evaluation stage.

5.3SIMULATIONRESULTSANDANALYSIS

The operation of the proposed CAM is verified by performing HSpice simulations based on TSMC 0.18m technology with a 1.8V supply voltage. The size of the CAM array is 64 72 bit. Fig. 5.4 shows the simulation result of the proposed design. At the beginning of a search cycle, both MLP and MLC are set to high so that previously charged MLs can reset to ground. The evaluation stage starts with the switching of both MLP and MLC to low. MLC is kept low for a period enough to charge the fully matched ML (ML0) to 0.67 V to enable the turning ON of the transistor M3. At this point, MLC is switched to high and the voltage of the fully matched ML (ML0) continues to maintain its value; the sensing unit senses this voltage as a match and generates a full swing output voltage at MLS0. The voltage of the matchline ML1 (only one bit mismatched ML, which is hardest to detect as a miss) is not high enough to turn the transistor M3 ON resulting in same low voltage at the output node MLS1.

Fig. 5. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched), ML1 (one-bit miss), ML2 (two-bit miss), MLC and MLP.

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Table 5. 1: Comparison of Different Schemes Scheme Current-race [81] Current-saving [82],[83] This work ML Energy (fJ/bit/search) 3.56 3.32 1.60 SL Energy (fJ/bit/search) 0.65 0.65 0.62 Minimum Cycle time (ns) 3.60 3.60 1.15

For the comparison of the proposed scheme with two other existing schemes (currentrace and current-saving), we simulated all three schemes with the same CMOS process using the same basic NOR type TCAM cell in the same 64 72 CAM block. Table 5.1 shows the comparative performance and energy per bit per search for these schemes. The match-line energy reduction is 51.8% compared to the current-saving scheme and 55% compared to the current-race scheme. While the SL energy remains almost same, the reduction in the minimum cycle time of operation of the proposed scheme is 68% compared to the both schemes. For the proposed technique, the speed of operation is 870 MHz which is 3.13 times the speed of the other two schemes (278MHz). The major difference between existing schemes [81]-[83] and our scheme is that we have used only one PMOS device for charging the MLs while existing schemes use two PMOS devices in series, resulting in half the equivalent resistance and increased speed of operation. The sensing unit [16] used in the simulation also contributed to the reduced power consumption. This sensing unit can sense about 0.67V as a high input whereas using the similar setup, sense amplifiers of the existing scheme requires a higher sense voltage of at about 1V. Due to the reduced sensing sense threshold voltage and lower voltage swing of MLs, this scheme results in reduced power consumption. Also, as the number of the transistors in charging unit of the proposed scheme is less than that in the existing schemes, less silicon area will be required to implement the unit CAM arrays. The difference between the maximum voltage to which ML0 and ML1 (hardest to detect as a miss) reach during evaluation, is about 180mV; this voltage is large enough to guard against any failure due to process variations. With respect to variation in supply voltage (VDD), the proposed scheme is found to be functional while VDD is varied from 1.67V to 2.07V. However, the MLs need to be protected against other sources of noise; an up-noise of over 180 mV on ML1 or a down-noise of over 180 mV will cause wrong values to be sensed by the sense amplifier. The cross-talk noise on MLs from neighboring signals needs to be minimized or eliminated using proper shielding and adequate spacing. So, the circuit will work properly even in presence of supply noise.

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5.4CONCLUSION
In this work, we have proposed a low-power and high- performance technique for charging match-lines for content-addressable memory arrays. To speed up the charging process, we have used only one PMOS device to charge up the match-lines and one NMOS device to reset them. The proposed scheme was simulated using HSpice in a 64 72 TCAM for TSMC 0.18m CMOS process. The results are compared with the existing current-race and current-saving schemes using the same technology. The results show that the match-line energy reduces by 51.8% and the minimum cycle time reduces by 68% compared to those schemes.

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 CHAPTER6 PROPOSEDCAMWITHIMPROVED NOISEMARGIN

51

CHAPTER 6 PROPOSED CAM WITH IMPROVED NOISE MARGIN

6.1INTRODUCTION

As Content Addressable Memory (CAM) is based on dynamic logic, it is more prone to be noise affected. The dynamic node Match-line (ML) of CAM is so long and may remain floating, so ML is the worst node regarding noise. Maintaining good immunity to noise, design of high speed and low-power CAM is the main purpose of this research. The principle of the new proposed charging controller is that Carry coal to Newcastle. The match-lines which has probability of being matched match-line (may be fully matched match-line in most of case or one miss-match-line if sufficient noise is added.) i.e. the match-line which has faster charging rate; the circuit will automatic charge those match-lines at the third state. The match-line which has lower probability to be matched match-line is no longer charged. This saves a large amount of power. As the matched matchline is charged to VDD, there is large difference of the voltages between fully matched matchline and 1-bit-missed matchline, so noise margin is high. In spite of the increase of noise immunity, speed and power consumption remains low as previous.

6.2OPERATIONOFTHESCHEME

The main structure of the CAM array is like the charging controller scheme. Here, an improved circuit of charging controller is used. The conventional sense amplifier is used to sense the match line voltage.

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Fig. 6. 1: Structure of the CAM array.

6.2.1Chargingcontroller

Fig. 6.2 shows the internal circuitry of the proposed charging controller. The total operation can be segmented into three phases or stages of time.

Fig. 6. 2: Internal circuitry of improved Charging

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Fig. 6. 3: Waveforms for CAM

At 1st stage, ML is precharged by high MLP. At this time, the transistor M1 and M7 is ON. So the gate of M2 is high and it is OFF so that the match-lines cannot be charged in this time. At 2nd stage, all the match-line is charged. A high MLC is applied to gate of M6; so it becomes ON and the gate of M2 is low. At 3rd stage, in most of match-line (miss-match line), charging is stopped. One or two match-lines are charged up to VDD (1.8V). For fully-matched matchline (as ML00 in Fig. 6.3), after the second stage, the voltage of the matchline is higher than any other matchline. This voltage is enough to make ON the transistor M3. The strength of the transistor M3 is make higher than M3 so that switching threshold of the inverter like part remain lower. So the gate of M2 will gradually get a low. So the charging to the respective matchline will continue. For partially matched matchline, the charging will be stopped just after the starting of 3 stage due to a high given by the output of transistor M4. This high will go through M5 transistor.
rd

6.2.2Thesenseamplifier

This scheme uses the conventional sense amplifier as shown in Fig. 6..4. To gain the high threshold switch, the strength of the keeper transistor is made higher than NMOS transistor.

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Fig. 6. 4: Conventional sense amplifier.

6.3SIMULATIONRESULT

Fig. 6..4 shows the simulation result which shows the two cycles of charging of different matchlines. Fig. 6.5 shows the input signals such as MLC and MLP and output MLS00 (output of the matchline which is fully matched) and MLS01 (output of the matchline which is partially matched.)

MLS00

ML00 ML01 ML02 MLS01

Fig. 6. 5: Charging in different match-lines.

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MLP

MLC

MLS00

MLS01

Fig. 6. 6: Controlled signals and output of each match-line. As we can see that the difference between the voltage of ML0 and ML1 is high. To result in error in the circuit, a large noise is should added in the matchline. So the noise immunity is quite better in this circuit. For process variation, we can assume that the match-line which has only one mismatch may be able to make ON the transistor M3. For that reason, if the charging continues, the voltage of the match-line will not be so large that can be sensed by the sense amplifier whose sensing threshold is higher.

Table 6. 1: Comparison of Different Schemes with improved noise margin scheme Scheme Current-race [81] Current-saving [82],[83] This work ML Energy (fJ/bit/search) 3.56 3.32 1.87 SL Energy (fJ/bit/search) 0.65 0.65 0.95 Minimum Cycle time (ns) 3.60 3.60 1.15

For the comparison of the proposed scheme with two other existing schemes (currentrace and current-saving), we simulated all three schemes with the same CMOS process using
56

the same basic NOR type TCAM cell in the same 64 72 CAM block. Table 6.1 shows the comparative performance and energy per bit per search for these schemes. The match-line energy reduction is 43.6% compared to the current-saving scheme and 47.5% compared to the current-race scheme. While the SL energy remains almost same, the reduction in the minimum cycle time of operation of the proposed scheme is 68% compared to the both schemes. For the proposed technique, the speed of operation is 870 MHz which is 3.13 times the speed of the other two schemes (278MHz). Table 6.2 shows the comparison of noise immunity and noise immunity which shows the scheme of this chapter provides good noise immunity.

Table 6. 2: Comparison of Noise Immunity of different schemes Scheme Noise Immunity Conventional Current race Current saving Charging control scheme Low noise scheme charging controller Good(+) + ++ + -Scheme simplicity

6.4CONCLUSION

The scheme shown in this Chapteris quite noise insensitive. The speed of the operation is also high as the previously proposed schemes. This scheme reduces the power consumption by a large extent. We think that this scheme would be practically implementable and usable.

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 CHAPTER7 CONCLUSION

58

Chapter 7
Conclusion
7.1Conclusion

CAMS are most often encountered as cache memories in computer systems but they are also starting to be used in applications such as database retrieval, parallel arithmetic algorithms and string processing. The width of the patterns stored in these CAMs usually varies between 32 and 64 bits, this parameter being governed by the word length used in todays computer systems. The match operation of high-performance CAM array is also performed with domino gates. The performance and area advantages of dynamic gates come at a cost of higher power and lower noise robustness. With the advancement of process technology, the leakage current in transistors continues to rise, worsening the total power and noise immunity in CAM circuits. Previous schemes follow different techniques to reduce the match line (ML) and search line (SL) power consumption. In this dissertation several methods and techniques are presented to design low-power and High Speed CAM circuits used in cache memory. To speed up the charging and discharging process, we use only one PMOS and one NMOS with full low and full high (when they are active) at the gate respectively where previous schemes [87], [88], [89] use two PMOSs to charge match-line. The overall effect of this scheme is a 57% ML power reduction compared to the current-race scheme, and 54% compared to the current-saving scheme

7.2FutureWork

We didnt analyze the noise immunity of our scheme. Noise is an important factor in CAM circuitry analysis. The immunity of a CMOS logic gate to noise signals is a function of many variables, such as individual chip differences, fan-in and fan-out, stray inductance and capacitance, supply voltage, location of the noise, shape of the noise signal, and temperature. Moreover, the immunity of a system of gates usually differs from that of any individual gate; thus a generalized analysis of the noise immunity of a logic circuit becomes a very complex process when one takes all the above parameters into consideration. There are several types
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of noise that can destroy the stored value. The major noises sources in electronic circuit are Crosstalk noise, Charge-sharing noise, charge leakage, propagated noise at the inputs, power supply noise, and process variations. There are so many techniques to reduce the effect of noise such as Covinos or inverter technique, DSouzas method: PMOS transistor pullup, Mirror technique, Twin-transistor technique, and Bobbas technique. For chip fabrication purpose layout design is necessary. We will design the layout of our scheme in next future and fabricate it. So, Chip fabrication is our next concern.

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J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits: A Design Perspective,PrenticeHall,UpperSaddleRiver,NJ,2002. N. Weste, D. Harris, A. Banerjee, CMOS VLSI DESIGN: A Circuits and Systems Perspective, 3rd Edition, Pearson Education, Inc.. 2005. D. A. Pucknell, K. Eshraghian, Basic VLSI Design, 3rd Edition, 1994.

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RESEARCH PAPERS FROM THIS THESIS

1. Md. Mehedi Hasan, Md. T. Rahman, Md. N. Hasan, A.B.M. H. Rashid, and Ataur R. Patwary, A Novel Match-line Charging Control Scheme with a New Sense Amplifier for High-Speed and Low-Power Content-Addressable Memory, 2008 International Conference on Solid State Devices and Materials (SSDM 2008), Tsukuba science city, Ibaraki, Japan.

2. Md. Mehedi Hasan, Md. Naimul Hasan, Md. Tauhidur Rahman, A.B.M. H. Rashid, and Ataur R. Patwary, A High-Speed and Low-Power Design of ContentAddressable Memory Using a Novel Match-line Charging Technique, accepted in TENCON 2008, Hyderabad.

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APPENDIX A SIMULATION CODE

A.1 HSpice code for Charging control scheme
File: mcam64_72ssdm.sp TCAM Circuit .TRAN 20P 2.30N UIC .IC V(MLV00)=0.65V *MEASURE THE SL AND ML POWER .INCLUDE 'MEAS_MCAM32.TXT' * VCC AND PRECHARGE VOLTAGES VDD 1 0 DC 1.8V VMLC MLC 0 PWL 0 0V,.39N 0V,.41N 1.8V,.72N 1.8V,.74N 0V,1.15N 0V,,1.54N 0V,1.56N 1.8V,1.87N 1.8V,1.89N 0V,2.30N 0V VMLP MLP 0 PWL 0 1.8V,.39N 1.8V,.41N 0V,1.08N 0V, 1.15N 1.8V,1.54N 1.8V,1.56N 0V,2.3N 0V VMLPB MLPB 0 PWL 0 0V,.39N 0V,.41N 1.80V,1.08N 1.80V, 1.15N 0V,1.54N 0V,1.56N 1.80V,2.3N 1.80V VSLDE SLDE 0 PWL 0 1.8V,0.02N 0V,.34N 0V,.36N 1.8V,1.15N 1.8V,1.17N 0V,1.49N 0V,1.51N 1.8V,2.3N 1.8V *Voltage sources to charge matchlines . E.g. MLV00 is to charge matchline ML00 .INCLUDE 'vmlv64.txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS .INCLUDE 'MYMLCS.TXT' $ML CHARGE CONTROLLER BLOCK .INCLUDE 'mcamxmlcs64.txt' *SENSE AMPLIFIER BLOCK .INCLUDE 'MYMLSA.TXT' .INCLUDE 'mcamxsa64.txt' *** MATCH LINE CAM CELL TOGETHER 4 LINE .INCLUDE 'ML_GOF4_1.txt' $FIRST 4 X 72 CAM CELL BLOCK . ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .INCLUDE 'ML_GOF4_2.txt' $2ND 4 X 72 CAM CELL BLOCK . ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .INCLUDE 'ML_GOF4_3.txt' .INCLUDE 'ML_GOF4_4.txt' .INCLUDE 'ML_GOF4_5.txt' .INCLUDE 'ML_GOF4_6.txt' .INCLUDE 'ML_GOF4_7.txt' .INCLUDE 'ML_GOF4_8.txt' .INCLUDE 'ML_GOF4_9.txt' .INCLUDE 'ML_GOF4_10.txt' .INCLUDE 'ML_GOF4_11.txt'

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.INCLUDE 'ML_GOF4_12.txt' .INCLUDE 'ML_GOF4_13.txt' .INCLUDE 'ML_GOF4_14.txt' .INCLUDE 'ML_GOF4_15.txt' .INCLUDE 'ML_GOF4_16.txt' .INCLUDE 'SLD10.txt' $SEARCH LINE DATA .INCLUDE 'SLDET.TXT' $DATA ENTER ENABLE NMOS *TCAMS .INCLUDE 'TCAM0.TXT' .INCLUDE 'TCAM1.TXT' .INCLUDE 'TCAMX.TXT' *WORD =X .INCLUDE 'WORDX.TXT' .INCLUDE 'BYTEX.TXT' $ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED $ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED

*WORD= 1010101010101010 & BYTE=10101010 .INCLUDE 'WORD10.TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .INCLUDE 'BYTE10.TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .INCLUDE 'WORD10M1.TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M2.TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M3.TXT' .INCLUDE 'WORD10M4.TXT' .INCLUDE 'WORD10M5.TXT' .INCLUDE 'WORD10M6.TXT' .INCLUDE 'WORD10M7.TXT' .INCLUDE 'WORD10M8.TXT' .INCLUDE 'WORD10M9.TXT' .INCLUDE 'WORD10M10.TXT' .INCLUDE 'WORD10M11.TXT' .INCLUDE 'WORD10M12.TXT' .INCLUDE 'WORD10M13.TXT' .INCLUDE 'WORD10M14.TXT' .INCLUDE 'WORD10M15.TXT' .INCLUDE 'WORD10M16.TXT' .INCLUDE 'BYTE10M8.txt' *MODEL .INCLUDE 'tsmc018.lib' .END File: vmlv64.txt VMLV00 MLV00 0 DC 1.8V VMLV01 MLV01 0 DC 1.8V VMLV02 MLV02 0 DC 1.8V VMLV03 MLV03 0 DC 1.8V VMLV04 MLV04 0 DC 1.8 VMLV05 MLV05 0 DC 1.8 VMLV06 MLV06 0 DC 1.8 VMLV07 MLV07 0 DC 1.8

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VMLV08 MLV08 0 DC 1.8 VMLV09 MLV09 0 DC 1.8 VMLV10 MLV10 0 DC 1.8 VMLV11 MLV11 0 DC 1.8 VMLV12 MLV12 0 DC 1.8 VMLV13 MLV13 0 DC 1.8 VMLV14 MLV14 0 DC 1.8 VMLV15 MLV15 0 DC 1.8 VMLV16 MLV16 0 DC 1.8 VMLV17 MLV17 0 DC 1.8 VMLV18 MLV18 0 DC 1.8 VMLV19 MLV19 0 DC 1.8 VMLV20 MLV20 0 DC 1.8V VMLV21 MLV21 0 DC 1.8V VMLV22 MLV22 0 DC 1.8V VMLV23 MLV23 0 DC 1.8V VMLV24 MLV24 0 DC 1.8 VMLV25 MLV25 0 DC 1.8 VMLV26 MLV26 0 DC 1.8 VMLV27 MLV27 0 DC 1.8 VMLV28 MLV28 0 DC 1.8 VMLV29 MLV29 0 DC 1.8 VMLV30 MLV30 0 DC 1.8 VMLV31 MLV31 0 DC 1.8 VMLV32 MLV32 0 DC 1.8 VMLV33 MLV33 0 DC 1.8 VMLV34 MLV34 0 DC 1.8 VMLV35 MLV35 0 DC 1.8 VMLV36 MLV36 0 DC 1.8 VMLV37 MLV37 0 DC 1.8 VMLV38 MLV38 0 DC 1.8 VMLV39 MLV39 0 DC 1.8 VMLV40 MLV40 0 DC 1.8V VMLV41 MLV41 0 DC 1.8V VMLV42 MLV42 0 DC 1.8V VMLV43 MLV43 0 DC 1.8V VMLV44 MLV44 0 DC 1.8 VMLV45 MLV45 0 DC 1.8 VMLV46 MLV46 0 DC 1.8 VMLV47 MLV47 0 DC 1.8 VMLV48 MLV48 0 DC 1.8 VMLV49 MLV49 0 DC 1.8 VMLV50 MLV50 0 DC 1.8 VMLV51 MLV51 0 DC 1.8 VMLV52 MLV52 0 DC 1.8 VMLV53 MLV53 0 DC 1.8 VMLV54 MLV54 0 DC 1.8 VMLV55 MLV55 0 DC 1.8 VMLV56 MLV56 0 DC 1.8 VMLV57 MLV57 0 DC 1.8 VMLV58 MLV58 0 DC 1.8 VMLV59 MLV59 0 DC 1.8 VMLV60 MLV60 0 DC 1.8V VMLV61 MLV61 0 DC 1.8V

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VMLV62 MLV62 0 DC 1.8V VMLV63 MLV63 0 DC 1.8V File: MYMLCS.txt .SUBCKT MYMLCS 1 MLC MLPB MLP MLV ML *MATCHLINE PRECHARGE TRANSISTOR MMLP ML MLP 0 0 cmosn L =0.18U W = 0.54U *MATCHLINE CURRENT SAVING MML1 ML MLCD MLV MLV cmosp L =0.18U W = 0.63U MML2 MLCD MLPB MLP 1 cmosp L =0.18U W = 0.63U MML3 MLCD ML 0 0 cmosn L =0.18U W = 0.27U MML4 MLCD MLC 0 0 cmosn L =0.18U W = 0.27U MML5 MLCD MLC ML5S 1 cmosp L =0.18U W = 0.63U MML6 ML5S ML 1 1 cmosp L =0.18U W = 0.63U .ENDS MYMLCS File: mcamxmlcs64.txt XMLCS00 1 MLC MLPB MLP MLV00 ML00 MYMLCS $FOR ML00 XMLCS01 1 MLC MLPB MLP MLV01 ML01 MYMLCS $FOR ML01 XMLCS02 1 MLC MLPB MLP MLV02 ML02 MYMLCS XMLCS03 1 MLC MLPB MLP MLV03 ML03 MYMLCS XMLCS04 1 MLC MLPB MLP MLV04 ML04 MYMLCS XMLCS05 1 MLC MLPB MLP MLV05 ML05 MYMLCS XMLCS06 1 MLC MLPB MLP MLV06 ML06 MYMLCS XMLCS07 1 MLC MLPB MLP MLV07 ML07 MYMLCS XMLCS08 1 MLC MLPB MLP MLV08 ML08 MYMLCS XMLCS09 1 MLC MLPB MLP MLV09 ML09 MYMLCS XMLCS10 1 MLC MLPB MLP MLV10 ML10 MYMLCS XMLCS11 1 MLC MLPB MLP MLV11 ML11 MYMLCS XMLCS12 1 MLC MLPB MLP MLV12 ML12 MYMLCS XMLCS13 1 MLC MLPB MLP MLV13 ML13 MYMLCS XMLCS14 1 MLC MLPB MLP MLV14 ML14 MYMLCS XMLCS15 1 MLC MLPB MLP MLV15 ML15 MYMLCS XMLCS16 1 MLC MLPB MLP MLV16 ML16 MYMLCS XMLCS17 1 MLC MLPB MLP MLV17 ML17 MYMLCS XMLCS18 1 MLC MLPB MLP MLV18 ML18 MYMLCS XMLCS19 1 MLC MLPB MLP MLV19 ML19 MYMLCS XMLCS20 1 MLC MLPB MLP MLV20 ML20 MYMLCS XMLCS21 1 MLC MLPB MLP MLV21 ML21 MYMLCS XMLCS22 1 MLC MLPB MLP MLV22 ML22 MYMLCS XMLCS23 1 MLC MLPB MLP MLV23 ML23 MYMLCS XMLCS24 1 MLC MLPB MLP MLV24 ML24 MYMLCS XMLCS25 1 MLC MLPB MLP MLV25 ML25 MYMLCS XMLCS26 1 MLC MLPB MLP MLV26 ML26 MYMLCS XMLCS27 1 MLC MLPB MLP MLV27 ML27 MYMLCS XMLCS28 1 MLC MLPB MLP MLV28 ML28 MYMLCS XMLCS29 1 MLC MLPB MLP MLV29 ML29 MYMLCS XMLCS30 1 MLC MLPB MLP MLV30 ML30 MYMLCS XMLCS31 1 MLC MLPB MLP MLV31 ML31 MYMLCS XMLCS32 1 MLC MLPB MLP MLV32 ML32 MYMLCS

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XMLCS33 1 MLC MLPB MLP MLV33 ML33 MYMLCS XMLCS34 1 MLC MLPB MLP MLV34 ML34 MYMLCS XMLCS35 1 MLC MLPB MLP MLV35 ML35 MYMLCS XMLCS36 1 MLC MLPB MLP MLV36 ML36 MYMLCS XMLCS37 1 MLC MLPB MLP MLV37 ML37 MYMLCS XMLCS38 1 MLC MLPB MLP MLV38 ML38 MYMLCS XMLCS39 1 MLC MLPB MLP MLV49 ML39 MYMLCS XMLCS40 1 MLC MLPB MLP MLV40 ML40 MYMLCS XMLCS41 1 MLC MLPB MLP MLV41 ML41 MYMLCS XMLCS42 1 MLC MLPB MLP MLV42 ML42 MYMLCS XMLCS43 1 MLC MLPB MLP MLV43 ML43 MYMLCS XMLCS44 1 MLC MLPB MLP MLV44 ML44 MYMLCS XMLCS45 1 MLC MLPB MLP MLV45 ML45 MYMLCS XMLCS46 1 MLC MLPB MLP MLV46 ML46 MYMLCS XMLCS47 1 MLC MLPB MLP MLV47 ML47 MYMLCS XMLCS48 1 MLC MLPB MLP MLV48 ML48 MYMLCS XMLCS49 1 MLC MLPB MLP MLV49 ML49 MYMLCS XMLCS50 1 MLC MLPB MLP MLV50 ML50 MYMLCS XMLCS51 1 MLC MLPB MLP MLV51 ML51 MYMLCS XMLCS52 1 MLC MLPB MLP MLV52 ML52 MYMLCS XMLCS53 1 MLC MLPB MLP MLV53 ML53 MYMLCS XMLCS54 1 MLC MLPB MLP MLV54 ML54 MYMLCS XMLCS55 1 MLC MLPB MLP MLV55 ML55 MYMLCS XMLCS56 1 MLC MLPB MLP MLV56 ML56 MYMLCS XMLCS57 1 MLC MLPB MLP MLV57 ML57 MYMLCS XMLCS58 1 MLC MLPB MLP MLV58 ML58 MYMLCS XMLCS59 1 MLC MLPB MLP MLV59 ML59 MYMLCS XMLCS60 1 MLC MLPB MLP MLV60 ML60 MYMLCS XMLCS61 1 MLC MLPB MLP MLV61 ML61 MYMLCS XMLCS62 1 MLC MLPB MLP MLV62 ML62 MYMLCS XMLCS63 1 MLC MLPB MLP MLV63 ML63 MYMLCS MYMLSA.TXT .SUBCKT MLSA 1 ML MLP MLPB MLSO MSA1 MSA1D ML 0 0 CMOSN L =0.18U W = 0.36U MSA2 MSA1D MLPB 1 1 CMOSP L =0.18U W = 0.63U XSA 1 MSA1D MLSO INVTR MSA3 MSA1D MLSO 0 0 CMOSN L =0.18U W = 0.27U MSA4 MLSO MLP 0 0 CMOSN L =0.18U W = 0.27U .SUBCKT INVTR VCC IN OUT MI1 OUT IN VCC VCC CMOSP L = 0.18U W = .63U MI2 OUT IN 0 0 CMOSN L =0.18U W = 0.27U .ENDS INVTR .ENDS MLSA
MCAMXSA64.TXT

XSA00 1 ML00 MLP MLPB MLSO00 MLSA XSA01 1 ML01 MLP MLPB MLSO01 MLSA

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XSA02 1 ML02 MLP MLPB MLSO02 MLSA XSA03 1 ML03 MLP MLPB MLSO03 MLSA XSA04 1 ML04 MLP MLPB MLSO04 MLSA XSA05 1 ML05 MLP MLPB MLSO05 MLSA XSA06 1 ML06 MLP MLPB MLSO06 MLSA XSA07 1 ML07 MLP MLPB MLSO07 MLSA XSA08 1 ML08 MLP MLPB MLSO08 MLSA XSA09 1 ML09 MLP MLPB MLSO09 MLSA XSA10 1 ML10 MLP MLPB MLSO10 MLSA XSA11 1 ML11 MLP MLPB MLSO11 MLSA XSA12 1 ML12 MLP MLPB MLSO12 MLSA XSA13 1 ML13 MLP MLPB MLSO13 MLSA XSA14 1 ML14 MLP MLPB MLSO14 MLSA XSA15 1 ML15 MLP MLPB MLSO15 MLSA XSA16 1 ML16 MLP MLPB MLSO16 MLSA XSA17 1 ML17 MLP MLPB MLSO17 MLSA XSA18 1 ML18 MLP MLPB MLSO18 MLSA XSA19 1 ML19 MLP MLPB MLSO19 MLSA XSA20 1 ML20 MLP MLPB MLSO20 MLSA XSA21 1 ML21 MLP MLPB MLSO21 MLSA XSA22 1 ML22 MLP MLPB MLSO22 MLSA XSA23 1 ML23 MLP MLPB MLSO23 MLSA XSA24 1 ML24 MLP MLPB MLSO24 MLSA XSA25 1 ML25 MLP MLPB MLSO25 MLSA XSA26 1 ML26 MLP MLPB MLSO26 MLSA XSA27 1 ML27 MLP MLPB MLSO27 MLSA XSA28 1 ML28 MLP MLPB MLSO28 MLSA XSA29 1 ML29 MLP MLPB MLSO29 MLSA XSA30 1 ML30 MLP MLPB MLSO30 MLSA XSA31 1 ML31 MLP MLPB MLSO31 MLSA XSA32 1 ML32 MLP MLPB MLSO32 MLSA XSA33 1 ML33 MLP MLPB MLSO33 MLSA XSA34 1 ML34 MLP MLPB MLSO34 MLSA XSA35 1 ML35 MLP MLPB MLSO35 MLSA XSA36 1 ML36 MLP MLPB MLSO36 MLSA XSA37 1 ML37 MLP MLPB MLSO37 MLSA XSA38 1 ML38 MLP MLPB MLSO38 MLSA XSA39 1 ML39 MLP MLPB MLSO39 MLSA XSA40 1 ML40 MLP MLPB MLSO40 MLSA XSA41 1 ML41 MLP MLPB MLSO41 MLSA XSA42 1 ML42 MLP MLPB MLSO42 MLSA XSA43 1 ML43 MLP MLPB MLSO43 MLSA XSA44 1 ML44 MLP MLPB MLSO44 MLSA XSA45 1 ML45 MLP MLPB MLSO45 MLSA XSA46 1 ML46 MLP MLPB MLSO46 MLSA XSA47 1 ML47 MLP MLPB MLSO47 MLSA XSA48 1 ML48 MLP MLPB MLSO48 MLSA XSA49 1 ML49 MLP MLPB MLSO49 MLSA XSA50 1 ML50 MLP MLPB MLSO50 MLSA XSA51 1 ML51 MLP MLPB MLSO51 MLSA XSA52 1 ML52 MLP MLPB MLSO52 MLSA XSA53 1 ML53 MLP MLPB MLSO53 MLSA XSA54 1 ML54 MLP MLPB MLSO54 MLSA XSA55 1 ML55 MLP MLPB MLSO55 MLSA

76

XSA56 1 ML56 MLP MLPB MLSO56 MLSA XSA57 1 ML57 MLP MLPB MLSO57 MLSA XSA58 1 ML58 MLP MLPB MLSO58 MLSA XSA59 1 ML59 MLP MLPB MLSO59 MLSA XSA60 1 ML60 MLP MLPB MLSO60 MLSA XSA61 1 ML61 MLP MLPB MLSO61 MLSA XSA62 1 ML62 MLP MLPB MLSO62 MLSA XSA63 1 ML63 MLP MLPB MLSO63 MLSA ML_GOF4_1.TXT XW001 1 ML00 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10 XW002 1 ML00 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW003 1 ML00 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW004 1 ML00 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW005 1 ML00 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW011 1 ML01 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10 XW012 1 ML01 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW013 1 ML01 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW014 1 ML01 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW015 1 ML01 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW021 1 ML02 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M1

77

XW022 1 ML02 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW023 1 ML02 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW024 1 ML02 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW025 1 ML02 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW031 1 ML03 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M2 XW032 1 ML03 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW033 1 ML03 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW034 1 ML03 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW035 1 ML03 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_2.TXT XW041 1 ML04 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M3 XW042 1 ML04 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW043 1 ML04 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW044 1 ML04 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW045 1 ML04 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

78

XW051 1 ML05 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M4 XW052 1 ML05 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW053 1 ML05 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW054 1 ML05 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW055 1 ML05 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW061 1 ML06 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M5 XW062 1 ML06 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW063 1 ML06 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW064 1 ML06 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW065 1 ML06 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW071 1 ML07 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M6 XW072 1 ML07 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW073 1 ML07 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW074 1 ML07 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10

79

XW075 1 ML07 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_3.TXT XW081 1 ML08 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M7 XW082 1 ML08 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW083 1 ML08 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW084 1 ML08 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW085 1 ML08 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW091 1 ML09 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M8 XW092 1 ML09 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW093 1 ML09 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW094 1 ML09 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW095 1 ML09 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW101 1 ML10 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M9 XW102 1 ML10 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW103 1 ML10 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW104 1 ML10 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B

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+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW105 1 ML10 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW111 1 ML11 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M10 XW112 1 ML11 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW113 1 ML11 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW114 1 ML11 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW115 1 ML11 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_4.TXT XW121 1 ML12 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M11 XW122 1 ML12 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW123 1 ML12 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW124 1 ML12 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW125 1 ML12 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW131 1 ML13 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M12 XW132 1 ML13 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW133 1 ML13 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B

81

+SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW134 1 ML13 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW135 1 ML13 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW141 1 ML14 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M13 XW142 1 ML14 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW143 1 ML14 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW144 1 ML14 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW145 1 ML14 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW151 1 ML15 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M14 XW152 1 ML15 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW153 1 ML15 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW154 1 ML15 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW155 1 ML15 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_5.txt XW161 1 ML16 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M15 XW162 1 ML16 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10

82

XW163 1 ML16 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW164 1 ML16 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW165 1 ML16 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW171 1 ML17 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW172 1 ML17 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW173 1 ML17 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW174 1 ML17 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW175 1 ML17 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW181 1 ML18 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW182 1 ML18 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M1 XW183 1 ML18 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW184 1 ML18 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW185 1 ML18 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW191 1 ML19 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW192 1 ML19 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M2

83

XW193 1 ML19 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW194 1 ML19 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW195 1 ML19 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_6.txt XW201 1 ML20 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW202 1 ML20 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M3 XW203 1 ML20 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW204 1 ML20 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW205 1 ML20 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW211 1 ML21 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW212 1 ML21 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M4 XW213 1 ML21 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW214 1 ML21 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW215 1 ML21 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW221 1 ML22 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16

84

XW222 1 ML22 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M5 XW223 1 ML22 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW224 1 ML22 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW225 1 ML22 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW231 1 ML23 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW232 1 ML23 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M6 XW233 1 ML23 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW234 1 ML23 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW235 1 ML23 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_7.txt XW241 1 ML24 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW242 1 ML24 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M7 XW243 1 ML24 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW244 1 ML24 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW245 1 ML24 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW251 1 ML25 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B

85

+SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW252 1 ML25 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M8 XW253 1 ML25 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW254 1 ML25 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW255 1 ML25 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW261 1 ML26 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW262 1 ML26 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M9 XW263 1 ML26 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW264 1 ML26 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW265 1 ML26 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW271 1 ML27 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW272 1 ML27 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M10 XW273 1 ML27 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW274 1 ML27 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW275 1 ML27 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

86

ML_GOF4_8.txt XW281 1 ML28 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW282 1 ML28 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M11 XW283 1 ML28 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW284 1 ML28 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW285 1 ML28 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW291 1 ML29 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW292 1 ML29 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M11 XW293 1 ML29 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW294 1 ML29 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW295 1 ML29 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW301 1 ML30 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW302 1 ML30 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M12 XW303 1 ML30 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW304 1 ML30 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10

87

XW305 1 ML30 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW311 1 ML31 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW312 1 ML31 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M13 XW313 1 ML31 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW314 1 ML31 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW315 1 ML31 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_9.txt XW321 1 ML32 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW322 1 ML32 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW323 1 ML32 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW324 1 ML32 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW325 1 ML32 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW331 1 ML33 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW332 1 ML33 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW333 1 ML33 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW334 1 ML33 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B

88

+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW335 1 ML33 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW341 1 ML34 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW342 1 ML34 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW343 1 ML34 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW344 1 ML34 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW345 1 ML34 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW351 1 ML35 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW352 1 ML35 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW353 1 ML35 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW354 1 ML35 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW355 1 ML35 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_10.txt XW361 1 ML36 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW362 1 ML36 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW363 1 ML36 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10

89

XW364 1 ML36 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW365 1 ML36 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW371 1 ML37 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW372 1 ML37 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW373 1 ML37 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW374 1 ML37 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW375 1 ML37 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW381 1 ML38 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW382 1 ML38 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW383 1 ML38 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW384 1 ML38 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW385 1 ML38 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW391 1 ML39 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW392 1 ML39 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10

90

XW393 1 ML39 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW394 1 ML39 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW395 1 ML39 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_11.txt XW401 1 ML40 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW402 1 ML40 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW403 1 ML40 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW404 1 ML40 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW405 1 ML40 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW411 1 ML41 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW412 1 ML41 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW413 1 ML41 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW414 1 ML41 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW415 1 ML41 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW421 1 ML42 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16

91

XW422 1 ML42 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW423 1 ML42 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW424 1 ML42 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW425 1 ML42 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW431 1 ML43 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW432 1 ML43 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW433 1 ML43 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW434 1 ML43 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW435 1 ML43 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_12.txt XW441 1 ML44 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW442 1 ML44 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW443 1 ML44 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW444 1 ML44 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW445 1 ML44 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW451 1 ML45 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B

92

+SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW452 1 ML45 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW453 1 ML45 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW454 1 ML45 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW455 1 ML45 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW461 1 ML47 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW462 1 ML47 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW463 1 ML47 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW464 1 ML47 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW465 1 ML47 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW471 1 ML47 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW472 1 ML47 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW473 1 ML47 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW474 1 ML47 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW475 1 ML47 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_13.txt

93

XW481 1 ML48 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW482 1 ML48 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW483 1 ML48 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW484 1 ML48 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW485 1 ML48 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW491 1 ML49 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW492 1 ML49 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW493 1 ML49 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW494 1 ML49 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW495 1 ML49 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW501 1 ML50 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW502 1 ML50 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW503 1 ML50 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW504 1 ML50 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW505 1 ML50 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

94

XW511 1 ML51 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW512 1 ML51 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW513 1 ML51 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW514 1 ML51 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW515 1 ML51 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_14.txt XW521 1 ML52 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW522 1 ML52 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW523 1 ML52 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW524 1 ML52 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW525 1 ML52 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW531 1 ML53 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW532 1 ML53 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW533 1 ML53 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW534 1 ML53 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW535 1 ML53 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B

95

+SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW541 1 ML54 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW542 1 ML54 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW543 1 ML54 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW544 1 ML54 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW545 1 ML54 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW551 1 ML55 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW552 1 ML55 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW553 1 ML55 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW554 1 ML55 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW555 1 ML55 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_15.txt XW561 1 ML56 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW562 1 ML56 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW563 1 ML56 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW564 1 ML56 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B

96

+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW565 1 ML56 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW571 1 ML57 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW572 1 ML57 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW573 1 ML57 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW574 1 ML57 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW575 1 ML57 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW581 1 ML58 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW582 1 ML58 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW583 1 ML58 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW584 1 ML58 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW585 1 ML58 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW591 1 ML59 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW592 1 ML59 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW593 1 ML59 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10

97

XW594 1 ML59 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW595 1 ML59 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_16.txt XW601 1 ML60 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW602 1 ML60 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW603 1 ML60 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW604 1 ML60 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW605 1 ML60 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW611 1 ML61 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW612 1 ML61 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW613 1 ML61 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW614 1 ML61 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW615 1 ML61 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW621 1 ML62 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW622 1 ML62 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10

98

XW623 1 ML62 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW624 1 ML62 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW625 1 ML62 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10

XW631 1 ML63 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW632 1 ML63 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW633 1 ML63 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW634 1 ML63 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW635 1 ML63 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 SLD10.txt VSLD00 SLD00 0 1.80V VSLD00B SLD00B 0 0V VSLD01 SLD01 0 0V VSLD01B SLD01B 0 1.80V VSLD02 SLD02 0 1.80V VSLD02B SLD02B 0 0V VSLD03 SLD03 0 0V VSLD03B SLD03B 0 1.80V VSLD04 SLD04 0 1.80V VSLD04B SLD04B 0 0V VSLD05 SLD05 0 0V VSLD05B SLD05B 0 1.80V VSLD06 SLD06 0 1.80V VSLD06B SLD06B 0 0V VSLD07 SLD07 0 0V VSLD07B SLD07B 0 1.80V VSLD08 SLD08 0 1.80V VSLD08B SLD08B 0 0V

99

VSLD09 SLD09 0 0V VSLD09B SLD09B 0 1.80V VSLD10 SLD10 0 1.80V VSLD10B SLD10B 0 0V VSLD11 SLD11 0 0V VSLD11B SLD11B 0 1.80V VSLD12 SLD12 0 1.80V VSLD12B SLD12B 0 0V VSLD13 SLD13 0 0V VSLD13B SLD13B 0 1.80V VSLD14 SLD14 0 1.80V VSLD14B SLD14B 0 0V VSLD15 SLD15 0 0V VSLD15B SLD15B 0 1.80V VSLD16 SLD16 0 1.80V VSLD16B SLD16B 0 0V VSLD17 SLD17 0 0V VSLD17B SLD17B 0 1.80V VSLD18 SLD18 0 1.80V VSLD18B SLD18B 0 0V VSLD19 SLD19 0 0V VSLD19B SLD19B 0 1.80V VSLD20 SLD20 0 1.80V VSLD20B SLD20B 0 0V VSLD21 SLD21 0 0V VSLD21B SLD21B 0 1.80V VSLD22 SLD22 0 1.80V VSLD22B SLD22B 0 0V VSLD23 SLD23 0 0V VSLD23B SLD23B 0 1.80V VSLD24 SLD24 0 1.80V VSLD24B SLD24B 0 0V VSLD25 SLD25 0 0V VSLD25B SLD25B 0 1.80V VSLD26 SLD26 0 1.80V VSLD26B SLD26B 0 0V VSLD27 SLD27 0 0V VSLD27B SLD27B 0 1.80V VSLD28 SLD28 0 1.80V VSLD28B SLD28B 0 0V

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VSLD29 SLD29 0 0V VSLD29B SLD29B 0 1.80V VSLD30 SLD30 0 1.80V VSLD30B SLD30B 0 0V VSLD31 SLD31 0 0V VSLD31B SLD31B 0 1.80V VSLD32 SLD32 0 1.80V VSLD32B SLD32B 0 0V VSLD33 SLD33 0 0V VSLD33B SLD33B 0 1.80V VSLD34 SLD34 0 1.80V VSLD34B SLD34B 0 0V

VSLD35 SLD35 0 0V VSLD35B SLD35B 0 1.80V VSLD36 SLD36 0 1.80V VSLD36B SLD36B 0 0V VSLD37 SLD37 0 0V VSLD37B SLD37B 0 1.80V VSLD38 SLD38 0 1.80V VSLD38B SLD38B 0 0V VSLD39 SLD39 0 0V VSLD39B SLD39B 0 1.80V VSLD40 SLD40 0 1.80V VSLD40B SLD40B 0 0V VSLD41 SLD41 0 0V VSLD41B SLD41B 0 1.80V VSLD42 SLD42 0 1.80V VSLD42B SLD42B 0 0V VSLD43 SLD43 0 0V VSLD43B SLD43B 0 1.80V VSLD44 SLD44 0 1.80V VSLD44B SLD44B 0 0V VSLD45 SLD45 0 0V VSLD45B SLD45B 0 1.80V VSLD46 SLD46 0 1.80V VSLD46B SLD46B 0 0V VSLD47 SLD47 0 0V

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VSLD47B SLD47B 0 1.80V VSLD48 SLD48 0 1.80V VSLD48B SLD48B 0 0V VSLD49 SLD49 0 0V VSLD49B SLD49B 0 1.80V VSLD50 SLD50 0 1.80V VSLD50B SLD50B 0 0V VSLD51 SLD51 0 0V VSLD51B SLD51B 0 1.80V VSLD52 SLD52 0 1.80V VSLD52B SLD52B 0 0V VSLD53 SLD53 0 0V VSLD53B SLD53B 0 1.80V VSLD54 SLD54 0 1.80V VSLD54B SLD54B 0 0V VSLD55 SLD55 0 0V VSLD55B SLD55B 0 1.80V VSLD56 SLD56 0 1.80V VSLD56B SLD56B 0 0V VSLD57 SLD57 0 0V VSLD57B SLD57B 0 1.80V VSLD58 SLD58 0 1.80V VSLD58B SLD58B 0 0V VSLD59 SLD59 0 0V VSLD59B SLD59B 0 1.80V VSLD60 SLD60 0 1.80V VSLD60B SLD60B 0 0V VSLD61 SLD61 0 0V VSLD61B SLD61B 0 1.80V VSLD62 SLD62 0 1.80V VSLD62B SLD62B 0 0V VSLD63 SLD63 0 0V VSLD63B SLD63B 0 1.80V VSLD64 SLD64 0 1.80V VSLD64B SLD64B 0 0V VSLD65 SLD65 0 0V VSLD65B SLD65B 0 1.80V VSLD66 SLD66 0 1.80V VSLD66B SLD66B 0 0V

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VSLD67 SLD67 0 0V VSLD67B SLD67B 0 1.80V VSLD68 SLD68 0 1.80V VSLD68B SLD68B 0 0V VSLD69 SLD69 0 0V VSLD69B SLD69B 0 1.80V VSLD70 SLD70 0 1.80V VSLD70B SLD70B 0 0V VSLD71 SLD71 0 0V VSLD71B SLD71B 0 1.80V SLDET.TXT MSLD00 SL00 SLDE SLD00 0 cmosn L =0.18U W = 0.27U MSLD00B SL00B SLDE SLD00B 0 cmosn L =0.18U W = 0.27U MSLD01 SL01 SLDE SLD01 0 cmosn L =0.18U W = 0.27U MSLD01B SL01B SLDE SLD01B 0 cmosn L =0.18U W = 0.27U MSLD02 SL02 SLDE SLD02 0 cmosn L =0.18U W = 0.27U MSLD02B SL02B SLDE SLD02B 0 cmosn L =0.18U W = 0.27U MSLD03 SL03 SLDE SLD03 0 cmosn L =0.18U W = 0.27U MSLD03B SL03B SLDE SLD03B 0 cmosn L =0.18U W = 0.27U MSLD04 SL04 SLDE SLD04 0 cmosn L =0.18U W = 0.27U MSLD04B SL04B SLDE SLD04B 0 cmosn L =0.18U W = 0.27U MSLD05 SL05 SLDE SLD05 0 cmosn L =0.18U W = 0.27U MSLD05B SL05B SLDE SLD05B 0 cmosn L =0.18U W = 0.27U MSLD06 SL06 SLDE SLD06 0 cmosn L =0.18U W = 0.27U MSLD06B SL06B SLDE SLD06B 0 cmosn L =0.18U W = 0.27U MSLD07 SL07 SLDE SLD07 0 cmosn L =0.18U W = 0.27U MSLD07B SL07B SLDE SLD07B 0 cmosn L =0.18U W = 0.27U MSLD08 SL08 SLDE SLD08 0 cmosn L =0.18U W = 0.27U MSLD08B SL08B SLDE SLD08B 0 cmosn L =0.18U W = 0.27U MSLD09 SL09 SLDE SLD09 0 cmosn L =0.18U W = 0.27U MSLD09B SL09B SLDE SLD09B 0 cmosn L =0.18U W = 0.27U MSLD10 SL10 SLDE SLD10 0 cmosn L =0.18U W = 0.27U MSLD10B SL10B SLDE SLD10B 0 cmosn L =0.18U W = 0.27U MSLD11 SL11 SLDE SLD11 0 cmosn L =0.18U W = 0.27U MSLD11B SL11B SLDE SLD11B 0 cmosn L =0.18U W = 0.27U MSLD12 SL12 SLDE SLD12 0 cmosn L =0.18U W = 0.27U MSLD12B SL12B SLDE SLD12B 0 cmosn L =0.18U W = 0.27U MSLD13 SL13 SLDE SLD13 0 cmosn L =0.18U W = 0.27U MSLD13B SL13B SLDE SLD13B 0 cmosn L =0.18U W = 0.27U

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MSLD14 SL14 SLDE SLD14 0 cmosn L =0.18U W = 0.27U MSLD14B SL14B SLDE SLD14B 0 cmosn L =0.18U W = 0.27U MSLD15 SL15 SLDE SLD15 0 cmosn L =0.18U W = 0.27U MSLD15B SL15B SLDE SLD15B 0 cmosn L =0.18U W = 0.27U MSLD16 SL16 SLDE SLD16 0 cmosn L =0.18U W = 0.27U MSLD16B SL16B SLDE SLD16B 0 cmosn L =0.18U W = 0.27U MSLD17 SL17 SLDE SLD17 0 cmosn L =0.18U W = 0.27U MSLD17B SL17B SLDE SLD17B 0 cmosn L =0.18U W = 0.27U MSLD18 SL18 SLDE SLD18 0 cmosn L =0.18U W = 0.27U MSLD18B SL18B SLDE SLD18B 0 cmosn L =0.18U W = 0.27U MSLD19 SL19 SLDE SLD19 0 cmosn L =0.18U W = 0.27U MSLD19B SL19B SLDE SLD19B 0 cmosn L =0.18U W = 0.27U MSLD20 SL20 SLDE SLD20 0 cmosn L =0.18U W = 0.27U MSLD20B SL20B SLDE SLD20B 0 cmosn L =0.18U W = 0.27U MSLD21 SL21 SLDE SLD21 0 cmosn L =0.18U W = 0.27U MSLD21B SL21B SLDE SLD21B 0 cmosn L =0.18U W = 0.27U MSLD22 SL22 SLDE SLD22 0 cmosn L =0.18U W = 0.27U MSLD22B SL22B SLDE SLD22B 0 cmosn L =0.18U W = 0.27U MSLD23 SL23 SLDE SLD23 0 cmosn L =0.18U W = 0.27U MSLD23B SL23B SLDE SLD23B 0 cmosn L =0.18U W = 0.27U MSLD24 SL24 SLDE SLD24 0 cmosn L =0.18U W = 0.27U MSLD24B SL24B SLDE SLD24B 0 cmosn L =0.18U W = 0.27U MSLD25 SL25 SLDE SLD25 0 cmosn L =0.18U W = 0.27U MSLD25B SL25B SLDE SLD25B 0 cmosn L =0.18U W = 0.27U MSLD26 SL26 SLDE SLD26 0 cmosn L =0.18U W = 0.27U MSLD26B SL26B SLDE SLD26B 0 cmosn L =0.18U W = 0.27U MSLD27 SL27 SLDE SLD27 0 cmosn L =0.18U W = 0.27U MSLD27B SL27B SLDE SLD27B 0 cmosn L =0.18U W = 0.27U MSLD28 SL28 SLDE SLD28 0 cmosn L =0.18U W = 0.27U MSLD28B SL28B SLDE SLD28B 0 cmosn L =0.18U W = 0.27U MSLD29 SL29 SLDE SLD29 0 cmosn L =0.18U W = 0.27U MSLD29B SL29B SLDE SLD29B 0 cmosn L =0.18U W = 0.27U MSLD30 SL30 SLDE SLD30 0 cmosn L =0.18U W = 0.27U MSLD30B SL30B SLDE SLD30B 0 cmosn L =0.18U W = 0.27U MSLD31 SL31 SLDE SLD31 0 cmosn L =0.18U W = 0.27U MSLD31B SL31B SLDE SLD31B 0 cmosn L =0.18U W = 0.27U MSLD32 SL32 SLDE SLD32 0 cmosn L =0.18U W = 0.27U MSLD32B SL32B SLDE SLD32B 0 cmosn L =0.18U W = 0.27U MSLD33 SL33 SLDE SLD33 0 cmosn L =0.18U W = 0.27U MSLD33B SL33B SLDE SLD33B 0 cmosn L =0.18U W = 0.27U

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MSLD34 SL34 SLDE SLD34 0 cmosn L =0.18U W = 0.27U MSLD34B SL34B SLDE SLD34B 0 cmosn L =0.18U W = 0.27U MSLD35 SL35 SLDE SLD35 0 cmosn L =0.18U W = 0.27U MSLD35B SL35B SLDE SLD35B 0 cmosn L =0.18U W = 0.27U MSLD36 SL36 SLDE SLD36 0 cmosn L =0.18U W = 0.27U MSLD36B SL36B SLDE SLD36B 0 cmosn L =0.18U W = 0.27U MSLD37 SL37 SLDE SLD37 0 cmosn L =0.18U W = 0.27U MSLD37B SL37B SLDE SLD37B 0 cmosn L =0.18U W = 0.27U MSLD38 SL38 SLDE SLD38 0 cmosn L =0.18U W = 0.27U MSLD38B SL38B SLDE SLD38B 0 cmosn L =0.18U W = 0.27U MSLD39 SL39 SLDE SLD39 0 cmosn L =0.18U W = 0.27U MSLD39B SL39B SLDE SLD39B 0 cmosn L =0.18U W = 0.27U MSLD40 SL40 SLDE SLD40 0 cmosn L =0.18U W = 0.27U MSLD40B SL40B SLDE SLD40B 0 cmosn L =0.18U W = 0.27U MSLD41 SL41 SLDE SLD41 0 cmosn L =0.18U W = 0.27U MSLD41B SL41B SLDE SLD41B 0 cmosn L =0.18U W = 0.27U MSLD42 SL42 SLDE SLD42 0 cmosn L =0.18U W = 0.27U MSLD42B SL42B SLDE SLD42B 0 cmosn L =0.18U W = 0.27U MSLD43 SL43 SLDE SLD43 0 cmosn L =0.18U W = 0.27U MSLD43B SL43B SLDE SLD43B 0 cmosn L =0.18U W = 0.27U MSLD44 SL44 SLDE SLD44 0 cmosn L =0.18U W = 0.27U MSLD44B SL44B SLDE SLD44B 0 cmosn L =0.18U W = 0.27U MSLD45 SL45 SLDE SLD45 0 cmosn L =0.18U W = 0.27U MSLD45B SL45B SLDE SLD45B 0 cmosn L =0.18U W = 0.27U MSLD46 SL46 SLDE SLD46 0 cmosn L =0.18U W = 0.27U MSLD46B SL46B SLDE SLD46B 0 cmosn L =0.18U W = 0.27U MSLD47 SL47 SLDE SLD47 0 cmosn L =0.18U W = 0.27U MSLD47B SL47B SLDE SLD47B 0 cmosn L =0.18U W = 0.27U MSLD48 SL48 SLDE SLD48 0 cmosn L =0.18U W = 0.27U MSLD48B SL48B SLDE SLD48B 0 cmosn L =0.18U W = 0.27U MSLD49 SL49 SLDE SLD49 0 cmosn L =0.18U W = 0.27U MSLD49B SL49B SLDE SLD49B 0 cmosn L =0.18U W = 0.27U MSLD50 SL50 SLDE SLD50 0 cmosn L =0.18U W = 0.27U MSLD50B SL50B SLDE SLD50B 0 cmosn L =0.18U W = 0.27U MSLD51 SL51 SLDE SLD51 0 cmosn L =0.18U W = 0.27U MSLD51B SL51B SLDE SLD51B 0 cmosn L =0.18U W = 0.27U MSLD52 SL52 SLDE SLD52 0 cmosn L =0.18U W = 0.27U MSLD52B SL52B SLDE SLD52B 0 cmosn L =0.18U W = 0.27U MSLD53 SL53 SLDE SLD53 0 cmosn L =0.18U W = 0.27U

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MSLD53B SL53B SLDE SLD53B 0 cmosn L =0.18U W = 0.27U MSLD54 SL54 SLDE SLD54 0 cmosn L =0.18U W = 0.27U MSLD54B SL54B SLDE SLD54B 0 cmosn L =0.18U W = 0.27U MSLD55 SL55 SLDE SLD55 0 cmosn L =0.18U W = 0.27U MSLD55B SL55B SLDE SLD55B 0 cmosn L =0.18U W = 0.27U MSLD56 SL56 SLDE SLD56 0 cmosn L =0.18U W = 0.27U MSLD56B SL56B SLDE SLD56B 0 cmosn L =0.18U W = 0.27U MSLD57 SL57 SLDE SLD57 0 cmosn L =0.18U W = 0.27U MSLD57B SL57B SLDE SLD57B 0 cmosn L =0.18U W = 0.27U MSLD58 SL58 SLDE SLD58 0 cmosn L =0.18U W = 0.27U MSLD58B SL58B SLDE SLD58B 0 cmosn L =0.18U W = 0.27U MSLD59 SL59 SLDE SLD59 0 cmosn L =0.18U W = 0.27U MSLD59B SL59B SLDE SLD59B 0 cmosn L =0.18U W = 0.27U MSLD60 SL60 SLDE SLD60 0 cmosn L =0.18U W = 0.27U MSLD60B SL60B SLDE SLD60B 0 cmosn L =0.18U W = 0.27U MSLD61 SL61 SLDE SLD61 0 cmosn L =0.18U W = 0.27U MSLD61B SL61B SLDE SLD61B 0 cmosn L =0.18U W = 0.27U MSLD62 SL62 SLDE SLD62 0 cmosn L =0.18U W = 0.27U MSLD62B SL62B SLDE SLD62B 0 cmosn L =0.18U W = 0.27U MSLD63 SL63 SLDE SLD63 0 cmosn L =0.18U W = 0.27U MSLD63B SL63B SLDE SLD63B 0 cmosn L =0.18U W = 0.27U MSLD64 SL64 SLDE SLD64 0 cmosn L =0.18U W = 0.27U MSLD64B SL64B SLDE SLD64B 0 cmosn L =0.18U W = 0.27U MSLD65 SL65 SLDE SLD65 0 cmosn L =0.18U W = 0.27U MSLD65B SL65B SLDE SLD65B 0 cmosn L =0.18U W = 0.27U MSLD66 SL66 SLDE SLD66 0 cmosn L =0.18U W = 0.27U MSLD66B SL66B SLDE SLD66B 0 cmosn L =0.18U W = 0.27U MSLD67 SL67 SLDE SLD67 0 cmosn L =0.18U W = 0.27U MSLD67B SL67B SLDE SLD67B 0 cmosn L =0.18U W = 0.27U MSLD68 SL68 SLDE SLD68 0 cmosn L =0.18U W = 0.27U MSLD68B SL68B SLDE SLD68B 0 cmosn L =0.18U W = 0.27U MSLD69 SL69 SLDE SLD69 0 cmosn L =0.18U W = 0.27U MSLD69B SL69B SLDE SLD69B 0 cmosn L =0.18U W = 0.27U MSLD70 SL70 SLDE SLD70 0 cmosn L =0.18U W = 0.27U MSLD70B SL70B SLDE SLD70B 0 cmosn L =0.18U W = 0.27U MSLD71 SL71 SLDE SLD71 0 cmosn L =0.18U W = 0.27U MSLD71B SL71B SLDE SLD71B 0 cmosn L =0.18U W = 0.27U TCAM0.TXT .SUBCKT TCAM0 1 2 7 8

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VMD0 9 0 DC 0V VMD0B 10 0 DC 1.8v X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.18U W = 0.27U MN2 2 4 6 0 cmosn L =0.18U W = 0.27U MN3 5 7 0 0 cmosn L =0.18U W = 0.27U MN4 6 8 0 0 cmosn L =0.18U W = 0.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.18U W = 0.27U MR2 9 WL BLL 0 cmosn L =0.18U W = 0.27U MR3 10 WL BLRB 0 cmosn L =0.18U W = 0.27U MR4 4 WL BLR 0 cmosn L =0.18U W = 0.27U *INVERTER SUBCKT .SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.18U W = .63U M2 OUT IN 0 0 cmosn L =0.18U W = 0.27U .ENDS INVTR .ENDS TCAM0 TCAM1.TXT .SUBCKT TCAM1 1 2 7 8 VMD1 9 0 DC 1.8V VMD1B 10 0 DC 0V X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.18U W = 0.27U MN2 2 4 6 0 cmosn L =0.18U W = 0.27U MN3 5 7 0 0 cmosn L =0.18U W = 0.27U MN4 6 8 0 0 cmosn L =0.18U W = 0.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V

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VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.18U W = 0.27U MR2 9 WL BLL 0 cmosn L =0.18U W = 0.27U MR3 10 WL BLRB 0 cmosn L =0.18U W = 0.27U MR4 4 WL BLR 0 cmosn L =0.18U W = 0.27U .SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.18U W = .63U M2 OUT IN 0 0 cmosn L =0.18U W = 0.27U .ENDS INVTR .ENDS TCAM1 TCAMX.TXT .SUBCKT TCAMX 1 2 7 8 VMDX 9 0 DC 1.8V VMDXB 10 0 DC 1.8V X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.18U W = 0.27U MN2 2 4 6 0 cmosn L =0.18U W = 0.27U MN3 5 7 0 0 cmosn L =0.18U W = 0.27U MN4 6 8 0 0 cmosn L =0.18U W = 0.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.18U W = 0.27U MR2 9 WL BLL 0 cmosn L =0.18U W = 0.27U MR3 10 WL BLRB 0 cmosn L =0.18U W = 0.27U MR4 4 WL BLR 0 cmosn L =0.18U W = 0.27U

.SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.18U W = .63U M2 OUT IN 0 0 cmosn L =0.18U W = 0.27U .ENDS INVTR .ENDS TCAMX WORDX.TXT

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.SUBCKT WORDX 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAMX X01 1 ML SL01 SL01B TCAMX X02 1 ML SL02 SL02B TCAMX X03 1 ML SL03 SL03B TCAMX X04 1 ML SL04 SL04B TCAMX X05 1 ML SL05 SL05B TCAMX X06 1 ML SL06 SL06B TCAMX X07 1 ML SL07 SL07B TCAMX X08 1 ML SL08 SL08B TCAMX X09 1 ML SL09 SL09B TCAMX X10 1 ML SL10 SL10B TCAMX X11 1 ML SL11 SL11B TCAMX X12 1 ML SL12 SL12B TCAMX X13 1 ML SL13 SL13B TCAMX X14 1 ML SL14 SL14B TCAMX X15 1 ML SL15 SL15B TCAMX .ENDS WORDX BYTEX.TXT .SUBCKT BYTEX 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B X00 1 ML SL00 SL00B TCAMX X01 1 ML SL01 SL01B TCAMX X02 1 ML SL02 SL02B TCAMX X03 1 ML SL03 SL03B TCAMX X04 1 ML SL04 SL04B TCAMX X05 1 ML SL05 SL05B TCAMX X06 1 ML SL06 SL06B TCAMX X07 1 ML SL07 SL07B TCAMX .ENDS BYTEX WORD10M1.TXT .SUBCKT WORD10M1 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM1 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0

109

X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M1 WORD10M2.TXT .SUBCKT WORD10M2 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M2 WORD10M3.TXT .SUBCKT WORD10M2 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M2 WORD10M4.TXT

110

.SUBCKT WORD10M4 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M4 WORD10M5.TXT .SUBCKT WORD10M5 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M5 WORD10M6.TXT .SUBCKT WORD10M6 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0

111

X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M6 WORD10M7.TXT .SUBCKT WORD10M7 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M7 WORD10M8.TXT .SUBCKT WORD10M8 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0

112

X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M8 WORD10M9.TXT .SUBCKT WORD10M9 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M9 WORD10M10.TXT .SUBCKT WORD10M10 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M10 WORD10M11.TXT .SUBCKT WORD10M11 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B

113

+SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M11 WORD10M12.TXT .SUBCKT WORD10M12 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M12 WORD10M13.TXT .SUBCKT WORD10M13 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1

114

X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M13 WORD10M14.TXT .SUBCKT WORD10M14 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M14 WORD10M15.TXT .SUBCKT WORD10M15 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM1 X14 1 ML SL14 SL14B TCAM0

115

X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M15 WORD10M16.TXT .SUBCKT WORD10M16 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM1 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM1 .ENDS WORD10M16 BYTE10M8.txt .SUBCKT BYTE10M8 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 .ENDS BYTE10M8 MEAS_MCAM32.TXT .MEAS TRAN AVGML0POW AVG P(VMLV00) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML1POW AVG P(VMLV01) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML2POW AVG P(VMLV02) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML3POW AVG P(VMLV03) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML4POW AVG P(VMLV04) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML5POW AVG P(VMLV05) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML6POW AVG P(VMLV06) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML7POW AVG P(VMLV07) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML8POW AVG P(VMLV08) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML9POW AVG P(VMLV09) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML10POW AVG P(VMLV10) FROM = 1.15NS TO = 2.3NS

116

.MEAS TRAN AVGML11POW AVG P(VMLV11) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML12POW AVG P(VMLV12) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML13POW AVG P(VMLV13) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML14POW AVG P(VMLV14) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML15POW AVG P(VMLV15) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML16POW AVG P(VMLV16) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML17POW AVG P(VMLV17) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML18POW AVG P(VMLV18) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML19POW AVG P(VMLV19) FROM = 1.15NS TO = 2.3NS

.MEAS TRAN AVGML20POW AVG P(VMLV20) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML21POW AVG P(VMLV21) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML22POW AVG P(VMLV22) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML23POW AVG P(VMLV23) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML24POW AVG P(VMLV24) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML25POW AVG P(VMLV25) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML26POW AVG P(VMLV26) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML27POW AVG P(VMLV27) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML28POW AVG P(VMLV28) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML29POW AVG P(VMLV29) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML30POW AVG P(VMLV30) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML31POW AVG P(VMLV31) FROM = 1.15NS TO = 2.3NS

.MEAS TRAN AVGSL0POW AVG P(VSLD00) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB0POW AVG P(VSLD00B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL1POW AVG P(VSLD01) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB1POW AVG P(VSLD01B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL2POW AVG P(VSLD02) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB2POW AVG P(VSLD02B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL3POW AVG P(VSLD03) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB3POW AVG P(VSLD03B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL4POW AVG P(VSLD04) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB4POW AVG P(VSLD04B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL5POW AVG P(VSLD05) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB5POW AVG P(VSLD05B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL6POW AVG P(VSLD06) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB6POW AVG P(VSLD06B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL7POW AVG P(VSLD07) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB7POW AVG P(VSLD07B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL8POW AVG P(VSLD08) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB8POW AVG P(VSLD08B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSL9POW AVG P(VSLD09) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB9POW AVG P(VSLD09B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLC20POW AVG P(VSLD00) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B0POW AVG P(VSLD00B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC21POW AVG P(VSLD01) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B1POW AVG P(VSLD01B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC22POW AVG P(VSLD02) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B2POW AVG P(VSLD02B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC23POW AVG P(VSLD03) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B3POW AVG P(VSLD03B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC24POW AVG P(VSLD04) FROM = 1.15NS TO = 2.3NS

117

.MEAS TRAN AVGSLC2B4POW AVG P(VSLD04B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC25POW AVG P(VSLD05) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B5POW AVG P(VSLD05B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC26POW AVG P(VSLD06) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B6POW AVG P(VSLD06B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC27POW AVG P(VSLD07) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B7POW AVG P(VSLD07B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC28POW AVG P(VSLD08) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B8POW AVG P(VSLD08B) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC29POW AVG P(VSLD09) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGSLC2B9POW AVG P(VSLD09B) FROM = 1.15NS TO = 2.3NS tsmc018.lib * T58F SPICE BSIM3 VERSION 3.1 PARAMETERS * * SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * * DATE: Oct 31/05 * LOT: T58F WAF: 9005 * Temperature_parameters=Default

.MODEL CMOSN NMOS ( +VERSION = 3.1 +XJ +K1 +K3B = 1E-7 = 0.5864999 = 0.0294061 TNOM NCH K2 W0 = 27

LEVEL = 49 TOX VTH0 K3 NLX = 4.1E-9 = 0.3662473 = 1E-3 = 1.630684E-7

= 2.3549E17 = 1.127266E-3 = 1E-7

+DVT0W = 0 +DVT0 = 1.2064649 +U0 +UC +AGS +KETA +RDSW +WR +XL +DWB +CIT = 273.8094484

DVT1W = 0 DVT1 UA

DVT2W = 0 DVT2 = 0.0197749 UB A0 B1 A2 PRWB = 2.408323E-18 =2 = 4.99995E-6 = 0.4640272 = -0.197728

= 0.4215486 = -1.40499E-9 = 1.355009E5

= 6.504826E-11 VSAT = 0.4449958 = -0.0164863 = 123.3376355 =1 =0 WINT XW B0 A1

= 1.901075E-7 = 3.868769E-4 = 0.5 LINT DWG

PRWG =0 = -1E-8

= 1.690044E-8 = -4.728719E-9 NFACTOR = 2.1860065

= -2.452411E-9 VOFF =0 CDSC ETA0

= -0.0948017

= 2.4E-4

CDSCD = 0 = 6.028975E-5

+CDSCB = 0

= 2.230928E-3 ETAB

118

+DSUB = 0.0145467 +PDIBLC2 = 1.66653E-3 +PSCBE1 = 8.91287E9 +DELTA = 0.01 +PRT +KT1L +UB1 +WL +WWN +LLN +LWL =0 =0 = -7.61E-18 =0 =1 =1 =0

PCLM

= 1.3822069

PDIBLC1 = 0.1762787 DROUT = 0.7694691

PDIBLCB = -0.1

PSCBE2 = 7.349607E-9 PVAG = 1.685917E-3 RSH = 6.7 MOBMOD = 1 KT1 UA1 AT =0 =0 =1 = -0.11 = 4.31E-9 = 3.3E4

UTE KT2

= -1.5 = 0.022

UC1

= -5.6E-11 =1 =0 WW LL LWN

WLN WWL LW

=0

CAPMOD = 2 CGSO PB

XPART = 0.5 CGBO = 1E-12

+CGDO = 8.23E-10 +CJ +CJSW = 9.466429E-4

= 8.23E-10 MJ = 0.8

= 0.8

= 0.3820266 MJSW = 0.102322

= 2.608154E-10 PBSW

+CJSWG = 3.3E-10 +CF +PK2 +PU0 =0

PBSWG = 0.8

MJSWG = 0.102322

PVTH0 = -2.199373E-3 PRDSW = -0.9368961 WKETA = -2.880976E-3 LKETA = 7.165078E-3 PUA = 5.505418E-12 PUB = 8.84133E-25

= 1.593254E-3 = 6.777519

+PVSAT = 2.006286E3 +NOIMOD=2.0E+00

PETA0 = 1.003159E-4

PKETA = -6.759277E-3

NOIA=1.3182567385564E+19

+NOIB=144543.977074592 NOIC=-1.24515784572817E-12 EF=0.92 EM=41000000 ) * * * flicker noise parameters above added manually from some other process * .MODEL CMOSP PMOS ( +VERSION = 3.1 +XJ +K1 +K3B = 1E-7 = 0.5341312 = 7.4916211 TNOM NCH K2 W0 = 27 LEVEL = 49 TOX VTH0 K3 NLX = 4.1E-9 = -0.3906012 =0 = 1.194072E-7

= 4.1589E17 = 0.0395326 = 1E-6

119

+DVT0W = 0 +DVT0 = 0.5060555 +U0 +UC +AGS = 115.6894042 = -1E-10 = 0.4186945

DVT1W = 0 DVT1 UA

DVT2W = 0 DVT2 = 0.1 UB A0 B1 A2 = 1.874308E-21 = 1.9976555 = 6.422908E-7 = 0.300003 = -0.4986647

= 0.2423835 = 1.573746E-9

VSAT B0 A1

= 1.130982E5 = 1.949178E-7 = 0.4749146 = 0.5 LINT DWG = -0.095236

+KETA = 0.0166345 +RDSW +WR +XL +DWB +CIT = 198.321294 =1 =0

PRWG =0 = -1E-8

PRWB

WINT XW

= 2.94454E-8 = -2.798724E-8 NFACTOR = 2

= -4.83797E-10 VOFF =0 CDSC ETA0

= 2.4E-4

CDSCD = 0 ETAB = -4.358398E-4

+CDSCB = 0 +DSUB

= 1.035504E-3

= 1.816555E-3

PCLM

= 1.3299898

PDIBLC1 = 1.766563E-3 DROUT = 1.011891E-3 PVAG = 0.0209921

+PDIBLC2 = 7.728395E-7

PDIBLCB = -1E-3

+PSCBE1 = 4.872184E10 PSCBE2 = 5E-10 +DELTA = 0.01 +PRT +KT1L +UB1 +WL +WWN +LLN +LWL =0 =0 = -7.61E-18 =0 =1 =1 =0 RSH UTE KT2 = 7.7

MOBMOD = 1 KT1 UA1 AT =0 =0 =1 = -0.11 = 4.31E-9 = 3.3E4

= -1.5 = 0.022

UC1

= -5.6E-11 =1 =0 WW LL LWN

WLN WWL LW

=0

CAPMOD = 2 CGSO PB

XPART = 0.5 CGBO MJ = 1E-12

+CGDO = 6.35E-10 +CJ +CJSW = 1.144521E-3

= 6.35E-10

= 0.8468686

= 0.4099522 MJSW = 0.3478565 MJSWG = 0.3478565

= 2.490749E-10 PBSW

= 0.8769118

+CJSWG = 4.22E-10 +CF +PK2 +PU0 =0

PBSWG = 0.8769118

PVTH0 = 2.302018E-3

PRDSW = 9.0575312 LKETA = -1.495872E-3 = 1E-21

= 1.821914E-3 = -1.5580645

WKETA = 0.0222457 PUA

= -6.36889E-11 PUB

120

+PVSAT = 49.8420442 + NOIMOD=2.0E+00

PETA0 = 2.827793E-5

PKETA = -2.536564E-3 NOIB=2500 EM=41000000 )

NOIA=3.57456993317604E+18

+ NOIC=2.61260020285845E-11 EF=1.1388 * * * flicker noise parameters above added manually from some other process *

121

A.2HSpicecodeforsimplifieddesignofchargingcontroller
mcam64_72_tencon.sp TCAM Circuit .TRAN 20P 2.30N 1.15N uic .IC V(MLV00)=.10V *MEASURE THE SL AND ML POWER .INCLUDE 'MEAS_MCAM32.TXT' * VCC AND PRECHARGE VOLTAGES .PARAM x=1.80 VDD 1 0 DC x VMLC MLC 0 PWL 0 1.8V,.39N 1.8V,.41N 0V,0.75N 0V,0.77N 1.8V, 1.15N 1.8V,1.54N 1.8V,1.56N 0V,1.90N 0V,1.92N 1.8V, 2.30N 1.8V VMLP MLP 0 PWL 0 1.8V,.39N 1.8V,.41N 0V,1.08N 0V, 1.15N 1.8V,1.54N 1.8V,1.56N 0V,2.3N 0V VMLPB MLPB 0 PWL 0 0V,.39N 0V,.41N 1.80V,1.08N 1.80V, 1.15N 0V,1.54N 0V,1.56N 1.80V,2.3N 1.80V VSLDE SLDE 0 PWL 0 1.8V,0.02N 0V,.34N 0V,.36N 1.8V,1.15N 1.8V,1.17N 0V,1.49N 0V,1.51N 1.8V,2.3N 1.8V *Voltage sources to charge matchlines . E.g. MLV00 is to charge matchline ML00 .INCLUDE 'vmlv64.txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS .INCLUDE 'MYMLCSNEW.TXT' $ML CHARGE CONTROLLER BLOCK .INCLUDE 'mcamxmlcs64.txt' *SENSE AMPLIFIER BLOCK .INCLUDE 'MYMLSA.TXT' .INCLUDE 'mcamxsa64.txt' *** MATCH LINE CAM CELL TOGETHER 4 LINE .INCLUDE 'ML_GOF4_1.txt' $FIRST 4 X 72 CAM CELL BLOCK . ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .INCLUDE 'ML_GOF4_2.txt' $2ND 4 X 72 CAM CELL BLOCK . ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .INCLUDE 'ML_GOF4_3.txt' .INCLUDE 'ML_GOF4_4.txt' .INCLUDE 'ML_GOF4_5.txt' .INCLUDE 'ML_GOF4_6.txt' .INCLUDE 'ML_GOF4_7.txt' .INCLUDE 'ML_GOF4_8.txt' .INCLUDE 'ML_GOF4_9.txt' .INCLUDE 'ML_GOF4_10.txt' .INCLUDE 'ML_GOF4_11.txt'

122

.INCLUDE 'ML_GOF4_12.txt' .INCLUDE 'ML_GOF4_13.txt' .INCLUDE 'ML_GOF4_14.txt' .INCLUDE 'ML_GOF4_15.txt' .INCLUDE 'ML_GOF4_16.txt' .INCLUDE 'SLD10.txt' $SEARCH LINE DATA .INCLUDE 'SLDET.TXT' $DATA ENTER ENABLE NMOS *TCAMS .INCLUDE 'TCAM0.TXT' .INCLUDE 'TCAM1.TXT' .INCLUDE 'TCAMX.TXT' *WORD =X .INCLUDE 'WORDX.TXT' .INCLUDE 'BYTEX.TXT'

$ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED

$ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED

*WORD= 1010101010101010 & BYTE=10101010 .INCLUDE 'WORD10.TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .INCLUDE 'BYTE10.TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .INCLUDE 'WORD10M1.TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M2.TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M3.TXT' .INCLUDE 'WORD10M4.TXT' .INCLUDE 'WORD10M5.TXT' .INCLUDE 'WORD10M6.TXT' .INCLUDE 'WORD10M7.TXT' .INCLUDE 'WORD10M8.TXT' .INCLUDE 'WORD10M9.TXT' .INCLUDE 'WORD10M10.TXT' .INCLUDE 'WORD10M11.TXT' .INCLUDE 'WORD10M12.TXT' .INCLUDE 'WORD10M13.TXT' .INCLUDE 'WORD10M14.TXT' .INCLUDE 'WORD10M15.TXT' .INCLUDE 'WORD10M16.TXT' .INCLUDE 'BYTE10M8.txt' *MODEL .INCLUDE 'tsmc018.lib' .END MYMLCSNEW.TXT * MY MLCS WITH TWO TRANSISTORS .SUBCKT MYMLCS 1 MLC MLPB MLP MLV ML

123

*MATCHLINE PRECHARGE TRANSISTOR MMLP ML MLP 0 0 cmosn L =0.18U W = 0.54U *MATCHLINE CURRENT SAVING M2 ML MLC MLV MLV cmosp L =0.18U W = 0.63U .ENDS MYMLCS

A.3HSpicecodeforimprovednoisescheme[chapter6]
mcam64_72_lna2.sp TCAM Circuit .TRAN 20P 2.30N UIC .IC V(MLV01)=1.7V *MEASURE THE SL AND ML POWER .INCLUDE 'MEAS_MCAM32.TXT' * VCC AND PRECHARGE VOLTAGES .PARAM x=1.8 VDD 1 0 DC x VMLC MLC 0 PWL 0 0,.48N 0,0.50N x,0.75N x,0.77N 0,1.15N 0,1.63N 0,1.65N x,1.90N x,1.92N 0,2.29N 0,2.30N x VMLCB MLCB 0 PWL 0 x,.48N x,0.50N 0,0.75N 0,0.77N x,1.15N x,1.63N x,1.65N 0V,1.90N 0V,1.92N x,2.29N x,2.30N 0V VMLP MLP 0 PWL 0 x,.48N x,.50N 0,1.14N 0,1.15N x,1.63N x,1.65N 0,2.29N 0,2.30N x VMLPB MLPB 0 PWL 0 0,.48N 0,.50N x,1.14N x,1.15N 0,1.63N 0,1.65N x,2.29N x,2.30N 0 VSLDE SLDE 0 PWL 0 0,.48N 0,0.50N x,1.14N x,1.15N 0,1.63N 0,1.65N x,2.29N x,2.30N 0 *Voltage sources to charge matchlines . E.g. MLV00 is to charge matchline ML00 .INCLUDE 'vmlv64.txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS .INCLUDE 'MYMLCS_lna2.TXT' $ML CHARGE CONTROLLER BLOCK .INCLUDE 'mcamxmlcs64_lna2.txt'

*SENSE AMPLIFIER BLOCK .INCLUDE 'MLSA_lna2.TXT' .INCLUDE 'mcamxsa64.txt'

124

*** MATCH LINE CAM CELL TOGETHER 4 LINE .INCLUDE 'ML_GOF4_1.txt' $FIRST 4 X 72 CAM CELL BLOCK . ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .INCLUDE 'ML_GOF4_2.txt' $2ND 4 X 72 CAM CELL BLOCK . ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .INCLUDE 'ML_GOF4_3.txt' .INCLUDE 'ML_GOF4_4.txt' .INCLUDE 'ML_GOF4_5.txt' .INCLUDE 'ML_GOF4_6.txt' .INCLUDE 'ML_GOF4_7.txt' .INCLUDE 'ML_GOF4_8.txt' .INCLUDE 'ML_GOF4_9.txt' .INCLUDE 'ML_GOF4_10.txt' .INCLUDE 'ML_GOF4_11.txt' .INCLUDE 'ML_GOF4_12.txt' .INCLUDE 'ML_GOF4_13.txt' .INCLUDE 'ML_GOF4_14.txt' .INCLUDE 'ML_GOF4_15.txt' .INCLUDE 'ML_GOF4_16.txt' .INCLUDE 'SLD10.txt' $SEARCH LINE DATA .INCLUDE 'SLDET.TXT' $DATA ENTER ENABLE NMOS *TCAMS .INCLUDE 'TCAM0.TXT' .INCLUDE 'TCAM1.TXT' .INCLUDE 'TCAMX.TXT' *WORD =X .INCLUDE 'WORDX.TXT' .INCLUDE 'BYTEX.TXT'

$ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED

$ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED

*WORD= 1010101010101010 & BYTE=10101010 .INCLUDE 'WORD10.TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .INCLUDE 'BYTE10.TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .INCLUDE 'WORD10M1.TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M2.TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .INCLUDE 'WORD10M3.TXT' .INCLUDE 'WORD10M4.TXT' .INCLUDE 'WORD10M5.TXT' .INCLUDE 'WORD10M6.TXT' .INCLUDE 'WORD10M7.TXT' .INCLUDE 'WORD10M8.TXT' .INCLUDE 'WORD10M9.TXT' .INCLUDE 'WORD10M10.TXT' .INCLUDE 'WORD10M11.TXT' .INCLUDE 'WORD10M12.TXT' .INCLUDE 'WORD10M13.TXT' .INCLUDE 'WORD10M14.TXT' .INCLUDE 'WORD10M15.TXT'

125

.INCLUDE 'WORD10M16.TXT' .INCLUDE 'BYTE10M8.txt' *MODEL .INCLUDE 'tsmc018.lib' .END MYMLCS_lna2.TXT .SUBCKT MYMLCS 1 MLV MLC MLCB MLP MLPB ML *MATCHLINE PRECHARGE TRANSISTOR M1 ML MLP 0 0 CMOSN L =0.18u W = 0.63u *MATCHLINE CURRENT SAVING M2 ML MID2 MLV MLV CMOSP L =0.18u W = 1.26u M3 MID1 ML 0 0 CMOSN L =0.18u W = 0.54u M4 MID1 ML 1 1 CMOSP L =0.18u W = 0.63u M5 MID1 MLCB MID2 0 CMOSN L =0.18u W = 0.27u M6 MID2 MLC 0 0 CMOSN L =0.18u W = 0.27u M7 MID2 MLPB 1 1 CMOSP L =0.18u W = 0.63u .ENDS MYMLCS mcamxmlcs64_lna2.txt XMLCS00 1 MLC MLPB MLP MLV00 ML00 MYMLCS $FOR ML00 XMLCS01 1 MLC MLPB MLP MLV01 ML01 MYMLCS $FOR ML01 XMLCS02 1 MLC MLPB MLP MLV02 ML02 MYMLCS XMLCS03 1 MLC MLPB MLP MLV03 ML03 MYMLCS XMLCS04 1 MLC MLPB MLP MLV04 ML04 MYMLCS XMLCS05 1 MLC MLPB MLP MLV05 ML05 MYMLCS XMLCS06 1 MLC MLPB MLP MLV06 ML06 MYMLCS XMLCS07 1 MLC MLPB MLP MLV07 ML07 MYMLCS XMLCS08 1 MLC MLPB MLP MLV08 ML08 MYMLCS XMLCS09 1 MLC MLPB MLP MLV09 ML09 MYMLCS XMLCS10 1 MLC MLPB MLP MLV10 ML10 MYMLCS XMLCS11 1 MLC MLPB MLP MLV11 ML11 MYMLCS XMLCS12 1 MLC MLPB MLP MLV12 ML12 MYMLCS XMLCS13 1 MLC MLPB MLP MLV13 ML13 MYMLCS XMLCS14 1 MLC MLPB MLP MLV14 ML14 MYMLCS XMLCS15 1 MLC MLPB MLP MLV15 ML15 MYMLCS XMLCS16 1 MLC MLPB MLP MLV16 ML16 MYMLCS XMLCS17 1 MLC MLPB MLP MLV17 ML17 MYMLCS XMLCS18 1 MLC MLPB MLP MLV18 ML18 MYMLCS XMLCS19 1 MLC MLPB MLP MLV19 ML19 MYMLCS XMLCS20 1 MLC MLPB MLP MLV20 ML20 MYMLCS XMLCS21 1 MLC MLPB MLP MLV21 ML21 MYMLCS XMLCS22 1 MLC MLPB MLP MLV22 ML22 MYMLCS XMLCS23 1 MLC MLPB MLP MLV23 ML23 MYMLCS XMLCS24 1 MLC MLPB MLP MLV24 ML24 MYMLCS XMLCS25 1 MLC MLPB MLP MLV25 ML25 MYMLCS

126

XMLCS26 1 MLC MLPB MLP MLV26 ML26 MYMLCS XMLCS27 1 MLC MLPB MLP MLV27 ML27 MYMLCS XMLCS28 1 MLC MLPB MLP MLV28 ML28 MYMLCS XMLCS29 1 MLC MLPB MLP MLV29 ML29 MYMLCS XMLCS30 1 MLC MLPB MLP MLV30 ML30 MYMLCS XMLCS31 1 MLC MLPB MLP MLV31 ML31 MYMLCS XMLCS32 1 MLC MLPB MLP MLV32 ML32 MYMLCS XMLCS33 1 MLC MLPB MLP MLV33 ML33 MYMLCS XMLCS34 1 MLC MLPB MLP MLV34 ML34 MYMLCS XMLCS35 1 MLC MLPB MLP MLV35 ML35 MYMLCS XMLCS36 1 MLC MLPB MLP MLV36 ML36 MYMLCS XMLCS37 1 MLC MLPB MLP MLV37 ML37 MYMLCS XMLCS38 1 MLC MLPB MLP MLV38 ML38 MYMLCS XMLCS39 1 MLC MLPB MLP MLV49 ML39 MYMLCS XMLCS40 1 MLC MLPB MLP MLV40 ML40 MYMLCS XMLCS41 1 MLC MLPB MLP MLV41 ML41 MYMLCS XMLCS42 1 MLC MLPB MLP MLV42 ML42 MYMLCS XMLCS43 1 MLC MLPB MLP MLV43 ML43 MYMLCS XMLCS44 1 MLC MLPB MLP MLV44 ML44 MYMLCS XMLCS45 1 MLC MLPB MLP MLV45 ML45 MYMLCS XMLCS46 1 MLC MLPB MLP MLV46 ML46 MYMLCS XMLCS47 1 MLC MLPB MLP MLV47 ML47 MYMLCS XMLCS48 1 MLC MLPB MLP MLV48 ML48 MYMLCS XMLCS49 1 MLC MLPB MLP MLV49 ML49 MYMLCS XMLCS50 1 MLC MLPB MLP MLV50 ML50 MYMLCS XMLCS51 1 MLC MLPB MLP MLV51 ML51 MYMLCS XMLCS52 1 MLC MLPB MLP MLV52 ML52 MYMLCS XMLCS53 1 MLC MLPB MLP MLV53 ML53 MYMLCS XMLCS54 1 MLC MLPB MLP MLV54 ML54 MYMLCS XMLCS55 1 MLC MLPB MLP MLV55 ML55 MYMLCS XMLCS56 1 MLC MLPB MLP MLV56 ML56 MYMLCS XMLCS57 1 MLC MLPB MLP MLV57 ML57 MYMLCS XMLCS58 1 MLC MLPB MLP MLV58 ML58 MYMLCS XMLCS59 1 MLC MLPB MLP MLV59 ML59 MYMLCS XMLCS60 1 MLC MLPB MLP MLV60 ML60 MYMLCS XMLCS61 1 MLC MLPB MLP MLV61 ML61 MYMLCS XMLCS62 1 MLC MLPB MLP MLV62 ML62 MYMLCS XMLCS63 1 MLC MLPB MLP MLV63 ML63 MYMLCS MLSA_lna2.TXT .SUBCKT MLSA 1 ML MLP MLPB MLSO MSA1 MSA1D ML 0 0 cmosn L =0.18U W = 0.27U MSA2 MSA1D MLPB 1 1 cmosp L =0.18U W = 0.63U XSA 1 MSA1D MLSO INVTR MSA3 MSA1D MLSO 1 1 cmosp L =0.18U W = 0.54U .SUBCKT INVTR VCC IN OUT MI1 OUT IN VCC VCC cmosp L = 0.18U W = .63U MI2 OUT IN 0 0 cmosn L =0.18U W = 0.27U .ENDS INVTR .ENDS MLSA

127

APPENDIX B HSPICE BASICS

B.1 INTRODUCTION
SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose analog electronic circuit simulator. It is a powerful program that is used in IC and board-level design to check the integrity of circuit designs and to predict circuit behavior. [1] HSpice is one of the most prominent commercial versions of SPICE which is now owned by Synopsys.

B.2 INSTALLATION AND USAGE OF HSPICE 2007

1. Double click the file Setup.exe. A window will appear like Fig. B.1

Fig. B.1

2. Click on Next. 3. By browsing the destination folder, click again on Next or simply click on Next for default destination folder.
128

4. As in Fig. B.2, selecting Typical Setup, click on the Next button.

Fig. B.2

5. Click on Next-> again on Next -> and again on Next. Now installation will be started. 6. When the window like Fig. B.3 appear, click on Ok.

Fig. B.3

6. When the window like Fig. B.4 appears, click on Ok.

129

Fig.B.4 7. Click on Finish and computer will be restarted. 8. Write a simple Hspice code and save as .sp file in a directory.

Fig. B.5 9. Click Start -> All programs -> HSPICE Z-2007.03 -> HSPUI z-2007.03. A window like Fig. B.5 will appear. 10. Click on Open and browse for the directory of the .sp file. 11. Click on Simulate. 12. If it wants any license file, browse your directory\hspice_vZ2007.03_Win_setup_w_license\Disk1\crack\license.dat and click on Ok. 13. Now simulation will be completed. 14. By clicking Avanwaves, you will get a window like Fig. B.6.

130

Fig. B.6

15. Click on the line like Transient: Tcam circuit. There may be DC:***** according to analysis type. 16. Then a list will appear on Box of Types and Curves. Click on the curve you want to watch. 17. The resultant graph will appear on Black window.

B.3 BASIC RULES OR QUICK MANUAL [2] B.3.1.InputFile

HSPICEinputiscomposedof(mainly)fourpart.

B.3.1.1.Titleline
Title line is always the first line of the input file. HSPICE simply neglects it. Since this line is echoed back in the outputfile for the page header, it is a very good place to describe what this simulation is for.

B.3.1.2.Elementdescription
Willbediscussedinmoredetaillater.

B.3.1.3.Controllines
CommandlinesthatyouusetocontrolthebehaviorofHSPICE.

B.3.1.4..END
131

Anythingafterthe.ENDlineisignored.

*Comment
Anylinestartingwith*isconsideredasacomment.

*Linecontinuation
Anylinethatstartswith+signisconsideredasthecontinuationofthepreviousline.

B.3.2.ElementDescription
B.3.2.1.Activedevice
B.3.2.1.1.MOS
AnylinethatstartswithMisconsideredasthedescriptionlineforaMOStransistor. MXXNode_DNode_GNode_SNode_BMODEL_NAME +W=W_VALUEL=L_VALUE[AD=AD_VALUE][AS=AS_VALUE] +[PD=PD_VALUE][PS=PS_VALUE] W,L:WidthandLengthofMOS AS,AD:theareaofthesource,drainregion(optional) PS,PD:theperipherallengthofsource,drainregion YouwillneedtospecifyAD,AS,PD,andPSifyouareconcernedabouttheparasiticcapacitancesof thedrainandsourcearea. (Example) M1004133NCHW=10uL=1uAD=30pAS=30PPD=16uPS=16U definesaMOStransistornamedM100withitsdrainconnectedtonode4,gateto1,sourceandbulk tonode3.Itswidthis10,length1micron.Areaforthesourceanddrainare30*10E12,andtheir peripherals.NowsincethemodelisNCH,youneedtodefineitsmodel.ThesimplestforofMOS modeldefinitionwouldbe: .MODELNCHNMOS TheabovelinetellsyouthatthemostypeNCHisaNMOSdevice.Itdoesn'tsayanythingmorethan that,soyoumaywantto,atleast,additsthresholdvoltage. MODELNCHNMOS +VT0=0.7... 132

B.3.2.1.2.Bipolartransistor
QXXN_CollectorN_BaseN_EmitterMODEL

B.3.2.1.3Diode
DXXN_anodeN_cathodeMODEL

B.3.2.2.PassiveDevice
RXXN1N2RvalueResistor CXXN1N2CvalueCapacitor LXXN1N2LvalueInductor

B.3.2.3.Independentsource
There are two types of independent source, voltage source and current source. B.3.2.3.1.Pulse Mostfrequentlyusedtimevaryingwaveformisapulse.Forexample,alinelikethefollowing: V11011pulse0510n1n2n4n10n saysthatthere'savoltagesourceconnectedbetweennode10andnode11,whichtogglesbetween 0Vand5V,withleadingtime(delay)of10n,1nsrisingtime,2nsfallingtimeand4nshightime,and period10ns. Becareful,however,ifyouwrite V11011pulse5010n1n2n4n10n nowthe1nsisfallingtime,notrisingtimesinceV1isoriginally5vinsteadof0V.

B.3.2.3.2.PWL
PWLisusedforpiecewiselinearwaveform.Mostflexible,butneedmanyparameterstouse. VNAMEn1n2pwlt0v0t1v1t2v2t3v3... ThevalueofVNAMEisv0att=t0,v1att=t1,andsoon.

B.3.2.3.3.Sine
Sinisforsinusoidalwaveform. V1100sinv_offv_ampfreq[phase] v_offisoffsetvalue,v_ampistheamplitude,freqisthefrequency

B.3.2.4.Dependentsource

133

Dependent sources are very useful elements in HSPICE. The four kinds of inear dependent sources are: VCCS:voltagecontrolledcurrentsource(Gelement) VCVS:voltagecontrolledvoltagesource(Eelement) CCCS:currentcontrolledcurrentsource(Felement) CCVS:currentcontrolledcurrentsource(Helement) Theyaredescribedinthefollowingform. GXXN+NNC+NCGain EXXN+NNC+NCGain FXXN+NNC+NCGain HXXN+NNC+NCGain

B.3.3. Analysis
B.3.3.1.DCanalysis
WhenyouwanttoperformaDCanalysis,youusethe.DCcontrolline.Itsformatis .DCVARIABLEstart_valuestop_valueincrement_value HSPICEwillstepthroughttheVARIABLEvaluestartfromthestart_valueinincrementof increment_valueuntiltheVARIABLEreachesthestop_value. Associatedwithany.DCcontrolshouldbea.PRINTor.PLOTcontrollinewhichwillcauseanoutput tobewrittentotheHSPICEoutput.

B.3.3.2.ACanalysis
.ACLINn_pointfstartfstop .ACDECn_pointfstartfstop .ACOCTn_pointfstartfstop HSPICEcalculatestheoperatingcondition,andformasmallsignalequivalentcircuitforthegiven netlist.Thenitperformsacanalysis.YouneedtohaveatleastoneACindependentsource.The frequencyofanyACsourceinthecircuitissettofstart.Thefrequencyincrementvalueisdefinedby theincrementoption.IfLINisused,frequencyissweepedfromfstart,andendswhenfrequency= fstop.Totalnumberoffrequencypointsusedinthissimationisn_point.IfDECisused,thereare goingtoben_pointpointswithinonedecade,andtherearen_pointpointswithinoneoctaveifOCT isused. Associatedwithany.ACstatementshouldbea.PRINTor.PLOTor.PROBE. Supposeyouhaveasimulationsetuplikethefollowing:

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Vin10DC=1AC .ACDEC1010100MEG .printacvdb(10)vp(10) ThenHSPICEwillprintoutthevoltageatnode10withvariousfrequencyfrom10Hzto100MegHzin decibelscale.Itwillprintoutthephaseofnode10,too. Ifnode1wastheinputforthecircuit,thentheprintedoutputVdb(10)willbethegainofyourcircuit fromnode1to10.Since'DEC10'isused,therewillbe10points(inlogscale)withineachdecade.

B.3.3.3.Transientanalysis.
.TRANt_incrementt_stop HSPICE will start simulating the circuit from time 0 to t_stop. The internal timing step is adjusted automatically to get the required accuracy. Parameter t_increment is used for output printout. It is also used in the internal timestep control algorithm, so when a accurate simulation is required, use asmallernumber.

B.3.3.4TFanalysis
.... VIN103v .TFv(10)vin .... will print out the transfer gain from the source specified as vin to the voltage of node 10. Thevaluespecifiedwhenvinisdefined(3voltinthisexample)isusedforbiascalculation.

B.3.4 References
[1]Online:http://en.wikipedia.org/wiki/HSPICE [2]Online:http://www.engr.uiuc.edu/OCEE/webcourses/ece497am/quick_hspice.html#misc

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