KM62256C Family

Document Title
32Kx8 bit Low Power CMOS Static RAM

CMOS SRAM

Revision History
Revision No
0.0 0.1 1.0 2.0

History
Advance information Initial draft Finalize Revise - Add 45ns part with 30pF test load Revise - Change specification format and merge : Commercial, Extended, Industrial product in same datasheets. Revise - Change Speed bin Erase 45ns part from commercial product and 100ns from extended and industrial product. - Production change Erase Low power product from TSOP package

Draft Data
February 12, 1993 November 2, 1993 September 24, 1994 August 12, 1995

Remark
Design target Preliminary Final Final

3.0

April 15, 1996

Final

4.0

December 19, 1997

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and product. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 4.0 December 1997

KM62256C Family
32Kx8 bit Low Power CMOS Static RAM
FEATURES
Process Technology : Poly Load Organization : 32Kx8 Power Supply Voltage : 4.5~5.5V Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 28-DIP-600B, 28-SOP-450, 28-TSOP1 -0813.4F/R

CMOS SRAM
GENERAL DESCRIPTION
The KM62256C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.

PRODUCT FAMILY
Power Dissipation Product Family KM62256CL KM62256CL-L KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L Operating Temperature VCC Range Speed Standby (ISB1, Max) 100A 20 A 100A 50 A 100A 50 A 70mA Operating (Icc2) PKG Type

Commercial (0~70C) Extended (-25~85C) Industrial (-40~85C)

55/70ns

28-DIP, 28-SOP 28-TSOP1 R/F 28-SOP 28-TSOP1 R/F 28-SOP 28-TSOP1 R/F

4.5 to 5.5V

70ns

70ns

PIN DESCRIPTION
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10

FUNCTIONAL BLOCK DIAGRAM

Clk gen. Precharge circuit.

A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24

VCC WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4

28-TSOP Type1 - Forward

A3 A4 A5 A6 A7 A8 A12 A13 A14

28-DIP 28-SOP

23 22 21 20 19 18 17 16 15

Row select

Memory array 512 rows 648 columns

28-TSOP Type1 - Reverse

I/O 1 I/O 8

Data cont

I/O Circuit Column select

Data cont

NameName
WE CS OE A0~A14 I/O1~I/O8 Vcc Vss

Function
Write Enable Input Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs Power Ground
CS WE OE A0 A1 A2 A9 A10 A11

Control Logic

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 4.0 December 1997

KM62256C Family
PRODUCT LIST
Commercial Temperature Product (0~70C) Part Name
KM62256CLP-5 KM62256CLP-5L KM62256CLP-7 KM62256CLP-7L KM62256CLG-5 KM62256CLG-5L KM62256CLG-7 KM62256CLG-7L KM62256CLTG-5L KM62256CLTG-7L KM62256CLRG-5L KM62256CLRG-7L

CMOS SRAM

Extended Temperature Products (-25~85 C) Part Name

KM62256CLGE-7 KM62256CLGE-7L KM62256CLTGE-7L KM62256CLRGE-7L

Industrial Temperature Products (-40~85C) Part Name

KM62256CLGI-7 KM62256CLGI-7L KM62256CLTGI-7L KM62256CLRGI-7L

Function
28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 55ns, L-pwr 28-SOP, 55ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 55ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 55ns, LL-pwr 28-TSOP R, 70ns, LL-pwr

Function
28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 70ns, LL-pwr

Function
28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP R, 70ns, LL-pwr

Note : LL means Low Low standby current.

FUNCTIONAL DESCRIPTION
CS H L L L
1. X means dont care

OE X
1)

WE X
1)

I/O Pin High-Z High-Z Dout Din

Mode Deselected Output Disabled Read Write

Power Standby Active Active Active

H L X
1)

H H L

ABSOLUTE MAXIMUM RATINGS1)

Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN,VOUT VCC PD TSTG Ratings -0.5 to VCC+0.5 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Operating Temperature TA -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260C, 10sec(Lead Only) Unit V V W C C C C Remark KM62256CL KM62256CLE KM62256CLI -

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Revision 4.0 December 1997

KM62256C Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 -

CMOS SRAM
Max 5.5 0 Vcc+0.5V2) 0.8 Unit V V V V

Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified Extended Product : TA=-25 to 85C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested

CAPACITANCE 1) (f=1MHz, TA=25C)

Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested

Symbol CIN CIO

Test Condition VIN=0V VIO=0V

Min -

Max 6 8

Unit pF pF

DC AND OPERATING CHARACTERISTICS

Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) KM62256CL KM62256CL-L Standby Current (CMOS) KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L
1. 20mA for Extended and Industrial Products 2. 10mA for Extended and Industrial Products 3. 2mA for Extended and Industrial Products

Test Conditions VIN=Vss to Vcc CS=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIH or V IL Cycle time=1s, 100% duty, IIO=0mA CS 0.2V, VIN0.2V, V INVcc -0.2V
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

Min -1 -1 2.4 Low Power Low Low Power -

Typ 7 2 1 -

Max 1 1 15
1)

Unit A A mA mA mA V V mA A A A

72) 70 0.4 1
3)

VOL VOH ISB

IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIH or VIL

100 20 100 50 100 50

ISB1

CS Vcc-0.2V, Other inputs=0~Vcc

Low Power Low Low Power Low Power Low Low Power

Revision 4.0 December 1997

KM62256C Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL

CMOS SRAM

CL1)

1. Including scope and jig capacitance

AC CHARACTERISTICS (Vcc=4.5~5.5V, KM62256C Family:TA=0 to 70C, KM62256CE Family:TA=-25 to 85C,

KM62256CI Family:TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 5 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 5 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 30 30 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units

DATA RETENTION CHARACTERISTICS

Item Vcc for data retention VDR KM62256CL KM62256CL-L Data retention current IDR KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L Data retention set-up time Recovery time tSDR tRDR Vcc=3.0V CSVcc-0.2V Symbol Test Condition CSVcc-0.2V L-Ver LL-Ver L-Ver LL-Ver L-Ver LL-Ver See data retention waveform Min 2.0 0 5 Typ 1 0.5 Max 5.5 50 10 50 25 50 25 ms A Unit V

Revision 4.0 December 1997

KM62256C Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA

CMOS SRAM

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC Address tAA tCO CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH

Data out
NOTES (READ CYCLE)

High-Z

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection.

Revision 4.0 December 1997

KM62256C Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(2) (CS

Controlled)

tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)

Data out
NOTES (WRITE CYCLE)

High-Z

High-Z

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, t WP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled
VCC 4.5V tSDR Data Retention Mode tRDR

2.2V VDR CSVCC - 0.2V CS GND

Revision 4.0 December 1997

KM62256C Family
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)

CMOS SRAM
Units: millimeter(inch)
0.25 +0.10 -0.05 +0.004 0.010-0.002 #15

#28

#1 36.72 1.446 MAX 36.320.20 1.4300.008

#14 3.810.20 0.1500.008 5.08 0.200 MAX

15.24 0.600

13.600.20 0.5350.008

0~15

( 1.65 ) 0.065

0.460.10 0.018 0.004 1.520.10 0.0600.004

2.54 0.100

3.300.30 0.1300.012 0.38 MIN 0.015

28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)

0~8 #28 #15

11.810.30 0.465 0.012

8.380.20 0.3300.008

#1 18.69 MAX 0.736 18.290.20 0.7200.008

#14 2.590.20 0.1020.008 3.00 0.118MAX 0.15

11.43 0.450

+0.10 -0.05

0.006+0.004 -0.002

1.020.20 0.0400.008

0.10 MAX 0.004 MAX

0.89 ) 0.035

0.410.10 0.0160.004

1.27 0.050

0.05 MIN 0.002

Revision 4.0 December 1997

KM62256C Family
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

CMOS SRAM
Units: millimeter(inch)

+0.10 -0.05 0.008+0.004 -0.002

0.20

13.400.20 0.5280.008 #28 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017

#1

0.55 0.0217

#14

#15 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN

28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)

0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.008-0.002

0.20

13.400.20 0.528 0.008 #15 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017

#14

0.55 0.0217

#1 0.25 0.010 TYP 11.800.10 0.4650.004

#28
+0.10 -0.05

0.15

0.006+0.004 -0.002 0~8

1.000.10 0.0390.004 1.20 0.047 MAX

0.45 ~0.75 0.018 ~0.030

0.50 ) 0.020

0.10 MAX 0.004 MAX 0.05 0.002 MIN

Revision 4.0 December 1997