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EXPERIMENT 1: INTRODUCTION TO LOGIC DESIGN

PURPOSE The purpose of this lab is to introduce you to several aspects of digital logic design. Among the topics discussed are documenting, building, and debugging digital logic circuits.

INTRODUCTION TO DIGITAL LOGIC Digital logic has found widespread acceptance throughout industry in the design of many diverse products. For instance, it is used in such devices as digital voltmeters, pocket calculators, digital watches, communication systems, and digital computers to name a few. In fact, digital circuits are used extensively in nearly all fields involving electronic design. Digital logic's widespread acceptance may be attributed to many factors, among which include its high reliability, its low cost, and its amenability to modularization in the form of integrated circuits (IC's), resulting in design simplification and a reduction in the number of components required to implement devices. Digital logic is based on the concept of discrete quantities, such as digits and alphabetic characters, as opposed to continuous quantities, such as voltages. The most prevalent digital logic system in use today is the binary system. In this system there exist only two discrete quantities or states. These states are referred to as on and off, true and false, high and low, or most commonly as 0 (zero) and 1 (one). The main reason for this system's dominance is the advantages it affords over other systems. Many components available for use in digital logic systems naturally have only two states--lights, diodes, and switches, for example. Furthermore, it is much easier to distinguish between two states rather than among several. This leads to more reliable systems. Finally, systems based on binary logic are easier to implement. The binary states could be represented in practical logic systems by a number of physical quantities (or signals), such as an open or short circuit; an open or closed valve; the presence or absence of fluid flow (as in fluid logic); high or low voltages; high or low pressure (as in pneumatic logic); and clockwise or counterclockwise magnetic fields (as in magnetic core memories). Many of these quantities are actually continuous in nature; hence, a range of values over which the quantity varies is used to represent each binary state. The most commonly used physical binary logic system implementation, and the one that will be used in this manual, unless otherwise mentioned, is called transistor-transistor logic (TTL). In this system, the quantity of interest is HIGH or LOW voltage. TTL logic devices are powered by a single +5 volt power supply. Thus, all signal voltages can only range from 0 to 5 volts. Logic 0 is represented by voltages between 0 and 0.8 volts, and logic 1 by voltages between 2.4 and 5 1.1

volts. The region between 0.8 and 2.4 volts is called the threshold region. A pictorial representation of this is given in Figure 1.1a. As an example, the interpretation of an arbitrary signal in this system is illustrated in Figure 1.1b. Usually the signal in Figure 1.1b is idealized to that shown in Figure 1.1c.

Figure 1.1 Representation of Binary Logic by Voltage Levels. In this type of physical logic system, the higher voltages are usually chosen to correspond to logic 1 and the lower voltages to logic 0. This is called the positive logic convention. If higher voltages are chosen to correspond to logic 0 and lower voltages to logic 1, we have the less common negative logic convention. Note that the choice of logic notation (positive or negative) is merely an assignment of the two voltage levels (HIGH or LOW) to the logic states (0 or 1). Thus, either logic notation can be chosen to describe the same digital circuit. Positive logic will be assumed throughout the rest of this manual unless otherwise mentioned.

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Two basic types of elements are used to manipulate logic signals and are also used as building blocks for larger more complex circuits: logic gates and flip-flops. Gates combine one or more logic inputs and produce a specified logic output. Flip-flops are storage devices created from gates using feedback, they can "store" logic values, i.e., they are memory devices. Circuit networks comprised only of logic gates (no flip-flops and usually no feedback) are called combinational logic. (There are a few unusual cases of circuits containing feedback which are still just combinational logic.) Circuits containing flip-flops, in addition to gates, are called sequential circuits (networks).

Figure 1.2 Standard Gate Symbols and Truth Tables for Basic Two Input Logic Functions.

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The symbols representing the most common logic gates, which perform the logical operations AND, OR, NOT, NAND, and NOR, are shown in Figure 1.2. In addition, a table of combinations or truth table corresponding to each gate is given. The truth table indicates the logic value generated at the output corresponding to all possible combinations of values arriving at the inputs, an input combination. (Note that a single line entering a circuit is called an input while a pattern of 0s and 1s on the inputs is called an input combination.) For example, consider the two input AND gate of Figure 1.2a. From its truth table in Figure 1.2b, we see that the output C of the AND gate generates logic 1 if and only if logic 1 is present at both of its inputs, A and B. All of these gates, except the inverter, may contain more than two inputs (e.g., 3-input gates, 4-input gates and 8-input gates are common). It is important to understand the basic operation of all the logic gates. Take time to learn the operation of gates in Figure 1.2. The symbols representing the most common types of flip-flops, JK and D flip-flops, are shown in Figure 1.3. The logic value stored in the flip-flops, or state of the flip-flops, are reflected at their outputs Q and Q', where Q is the true output and Q' is the complement output. A clock signal at the clock input, indicated by the '>', determines at what points in time the state of the flip-flop changes according to its inputs, D or J and K, and its previous state. The PR and CLR inputs are used to initialize the state of the flip-flops to either 1 or 0, respectively, and they function independent of the clock and override the effect of the clock and other inputs. They are called asynchronous inputs.

PR D Q J Q

Q CLR

K CLR

Figure 1.3 D and JK Flip-flops.

INTEGRATED CIRCUITS Logic gates, flip-flops, and other digital devices are invariably constructed from integrated circuits (IC's). IC's contain diodes, transistors, and resistors, required to implement the device, on a semiconductor base called a chip. Thousands of chips, performing a great variety of logical operations, are available. The chip itself is enclosed in a protective metal or plastic case called a package. Connecting pins on the exterior of the package allow input/output signals and power to be transmitted between the chip and the outside world. A common package is the dual in-line package (DIP); in such at package, the connecting pins are arranged in two (dual) lines. The packages 1.4

commonly have a total of 14, 16, 18, 20, 24, 36, or 40 pins. The pin numbering scheme for 14-, 16-, and 24-pin DIP IC's is shown in Figure 1.4. A notch in the package usually identifies pin 1. (Figure 1.4 shows a top view of the chips. Note that, when viewed from the top, pin 1 is to the left of the notch and when viewed from the bottom, pin 1 is the right of the notch.)

Figure 1.4 IC Pin Numberings. (Top View) IC's are classified not only by their logical functions, but also by their logic family. An IC's logic family is determined by the "basic circuit" upon which more complex circuits are based. Some of the older logic families include TTL--Transistor-transistor logic, ECL--Emitter-coupled logic, MOS--Metal-oxide semiconductor logic, CMOS--Complementary metal-oxide semiconductor logic, and I2L--Integrated-injection logic. In the lab we use a version of TTL logic called lowlevel Schottky, LS for short. Each logic family has its own particular characteristics and physical binary logic system, i.e., chips from two different logic families may not have compatible physical representations of binary 0 and 1; meaning some families of chips will use different voltages to represent logic 0 and 1. Therefore, it may not be compatible to build a logic circuit out of two or more families of chips. Specification sheets for ICs list pertinent information regarding device use. These sheets are available in printed data manuals, but most manufacturers of ICs now have these specifications available on the web. For example, the Texas Instrument web site for logic families is http://focus.ti.com/logic/docs/logichome.tsp?sectionId=450&familyId=1&DCMP=TIHom eTracking&HQS=Other+OT+home_p_logicl This site has specification sheets for TIs logic families. For example, if you follow the path Data Sheets, LS(under select a logic family), SN74LS00 and Download(under the Datasheet section), you will download a data sheet in pdf format for the 74LS00 IC. It is called 1.5

a quad two-input NAND gate package. This IC contains four, two-input NAND gates, as the name implies. The 54 series number (military grade), 5400, or the 74 series number (commercial grade), 7400 indicate that the chip belongs to the TTL logic family. The pin assignments for the gate inputs, gate outputs, supply voltage, and ground pins are shown at the top left for the 14-pin dual-in-line (DIP) package, the J package. (All the chips used in the 2301 lab are in DIP packages, either 14-pin or 16-pin.) This chip is also available in other packages, e.g., a flatpack package, the fk package. (Another web site containing information on TTL chips is www.datasheet.in. The LS parts are in pages 7 and 8 of those parts with part number starting with 7.) In addition to pin assignments, the specification sheet gives recommended operating parameters and characteristics for the chip. For example, we see in the Guaranteed Operating Ranges table that, for proper operation, the commercial grade 7400 chip's supply voltage, VCC, should range between 4.75 and 5.25 V, and its temperature between 0 to 70 C. This table also gives the maximum output current, IOH, that can be sourced by a gate output when it is HIGH, and the maximum output current, IOL, that can be sinked by a gate output when it is LOW. Note the signs on these current values. By convention, current is positive if it is flowing into a terminal so IOH is a negative 0.4 mA and IOL is a positive 8.0 mA. Also from the DC Characteristics over Operating Temperature Range table, we see that an input signal exceeding 2.0 volts, VIH, is guaranteed to be interpreted as HIGH, and one not exceeding 0.8 volts, VIL, as LOW. Similarly, an output is guaranteed to be at least 2.7 volts, VOH, for a HIGH output and less than 0.5 volts, VOL, for a LOW output, when sinking 8.0 mA of current. This table also specifies the current flow into an input when it is HIGH, IIH, and when it is LOW, IIL. The output short circuit current IOS is the output current that flows from a HIGH output that is connected directly to ground. The HIGH supply current ICCH is the total power supply current per IC that flows when the outputs of the chip are HIGH. Similarly, ICCL is the supply current per IC which flows when the outputs are LOW. Another parameter of interest for gates in a logic family is the maximum fan-out. The maximum fan-out is the maximum number of gate inputs, within the same logic family, that can be driven from (connected to) a gate output can drive before the output becomes overloaded, i.e., it produces a voltage level outside a range for a valid logic level. For TTL logic, the maximum fan-out is equal to the ratio of IOL to the absolute value of IIL, so it is 20 for the LS family. The minimum and maximum values given in a data sheet are guaranteed over the entire temperature and supply voltage range indicated for the device. This implies that the device can operate reliably under variable temperatures and supply voltages that occur in practical systems. Finally, the data sheets specify the AC characteristics of the gates. When the input voltage to a logic gate changes, it takes time for this change to propagate to the output. The propagation delay time is the time required for the output of a device to change after receiving an input signal. The turn-off delay tPLH is the time required for the gate output to switch from LOW to 1.6

HIGH, measured relative to the time the gate input changes. The turn-on delay tPHL is the time required for the gate output to switch from HIGH to LOW, measured relative to the time the gate input changes.

CIRCUIT CONSTRUCTION In order to protect the IC's pins and facilitate wiring, the IC's you use will be mounted in a breadboard. An extraction tool, available in the lab, should always be used to remove an IC from its socket; trying to remove them by hand often results in bent and broken IC pins. All IC's should be mounted with the same orientation to facilitate wiring and debugging. It is not advisable to reverse the orientation of some IC's to minimize wire lengths. Wiring is done on the top side of the breadboard, i.e., on the same side that the ICs are inserted; hence, the numbering scheme shown in Figure 1.4 gives the correct view. Appendix A describes the functionality of the logic box available in the lab and how to connect the logic box to the breadboard. The breadboard and ICs used in the experiments are available in lab kit available through the bookstore. You should begin connecting your circuits by wiring power, ground, and all unused inputs of gates (for gates having more inputs than needed) to an appropriate constant source. This makes the first connections those that are least likely to change during debugging. Try to keep the wires as close to the surface of the board and as short as possible. Try not to cross too many wires, so that tracing and removal of the wires will be easier. Furthermore, a color code scheme will greatly simplify debugging the circuit later. For example, all power supply wires could be red, all ground wires black, etc. When you have finished wiring, examine each pin of each IC to verify its connection. Check all pins without any wires attached to see if they really should have no connection. Be sure to double-check all power connections before applying power to the circuit. The 5 volt power supply provided is short-circuit protected, so that shorting the power supply will merely shut it down until the short circuit is removed. Thus, there is no need to worry about getting a shock from 5 volts. However, you should be concerned about damaging IC's by improper connections! The one sure way to irreparably damage an IC is to reverse power and ground. Most IC's have their ground pin in the lower-left hand corner and power in the upper right-hand corner, when viewed from the bottom. Thus mounting an IC backwards will blow it out. But be alert, some IC's have power and ground in nonstandard locations. Sometimes you will not damage an IC by shorting one of its outputs to ground. However, when a TTL output trying to maintain a LOW level is shorted to the 5 volt power supply, damage will result. Shorting the outputs of CMOS gates to each other, power, or ground for a short period of time is not damaging, but permanent damage may result after a few minutes. Also, if a signal is

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applied to a CMOS gate input that does not have its power and ground connected, damage may result. Although TTL inputs may be tied directly to ground, they should never be connected directly to the +5 volt power supply. If by some misfortune the voltage level at some input terminal exceeds that at the power supply terminal, the chip will be destroyed. Use either a logicbox TTL output to provide a HIGH level to a TTL input, or wire up a gate on your circuit to provide a fixed HIGH level signal at its output to supply the TTL input. (The logic box TTL outputs contain a current limiting resistor in the connection to +5 volts.) Above all, keep your wiring neat. A neatly wired circuit is much easier to debug and tends to be more reliable. With messy wiring, removing or inserting one wire, besides being a difficult chore, can have unpredictable and untraceable effects--it can loosen other wires tangled with it in the mess. In a neatly wired circuit, you (and the laboratory instructor) at least have a chance of successfully debugging the circuit.

DOCUMENTATION The most important prerequisite for good design is good documentation. You should design and document your system completely before you build it, not while you build it. The documentation should include complete circuit diagrams of your system, indicating the part numbers, pin numbers, and physical locations of all the components. Your documentation should generally consist of five parts: a block diagram, logic diagram, chip layout, state diagram, and word description. The block diagram gives an overview of the functional modules comprising a complex system, while logic diagrams, in conjunction with the chip layout diagram, completely detail the system's construction. State diagrams aid in understanding any complex sequential control circuitry. Finally, the word description should concisely explain the operation of the system and any assumptions made. Not all five parts of the documentation are essential for every circuit. For example, simple circuits containing less than 10 IC's may not need block diagrams. The circuit's operation could readily be assimilated from its logic diagram. Also, state diagrams are definitely not applicable to combinational circuits. Block Diagrams In complex systems involving many IC's, a block diagram is essential to attain a fundamental understanding of the system's operation. It must indicate the major subsystems of the system, and the data and control paths between them. In very large systems, additional block diagrams of the individual subsystems may also be required, but there should always be one block diagram illustrating the entire system.

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The blocks in the diagram indicate functional modules of the system, not the individual components that comprise it. For example, a 16-bit register implemented using four 4-bit registers should be considered as one block rather than four individual blocks. It is looked upon as a 16-bit register by all the other modules in the system. The individual components comprising it are not individually accessible by the other modules. The separation of the system into major subsystems is not a well-defined process. There are many ways to partition a system into subsystems. But essentially the partitioning reduces to a compromise between too much and too little detail. Too much detail, and the overall operation of the system is lost in a mass of details. Too little detail, and the fundamental operation of the system is inadequately depicted. Figure 1.5 illustrates a block diagram. The double arrows indicate buses, i.e., multiple lines used to carry signals, data or control, between modules. It is essential that the flow of control and data between modules in block diagrams be indicated clearly. With control and status lines, the flow is usually in one direction, but lines carrying data, especially buses, are often bidirectional, i.e., the flow can be in both directions.

Figure 1.5 Example Block Diagram.

Logic Diagrams and Chip Layout The logic diagrams and chip layout should give all the information needed to construct the system. The logic diagram should indicate every connection between the components. The chip layout diagram should indicate the position, a reference number (such as U1, U2, etc.), and the part number of each component used in the circuit. Figure 1.6 illustrates a logic diagram of a 1.9

circuit. A corresponding chip layout diagram is shown in Figure 1.7. Note that NC stands for no connection on the logic diagram. On the logic diagram, the gates and flip-flops used in the circuit should be shown using the standard symbols presented in the introduction to this lab. Each gate and flip-flop should be labeled with the reference number and part number of the IC containing it. In addition, the input and output lines of the gates and flip-flops should be labeled with the corresponding pin numbers on the IC. The gate number on the IC should also be labeled.

Figure 1.6 Logic Diagram for a Serial Adder.

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Figure 1.7 Chip Layout Diagram for a Serial Adder. Other IC chips should be drawn as rectangles with labels inside denoting their reference and part numbers. Also the names of the input and output pins should be labeled within the rectangle. As with gates and flip-flops, the input/output lines should be labeled with their corresponding pin numbers on the IC to facilitate wiring the circuit. Note that normally power and ground pins for chips are not included in logic diagrams. It is assumed that you can look up their locations from the specification sheets of the IC's. All input and output lines to the circuit must be labeled. It may be helpful to label other lines.

DEBUGGING A circuit may sometimes work properly the first time it is turned on, but more likely it will not and, hence, will require debugging. Before power is applied to the circuit, the circuit should be checked to see that it is wired correctly. Improper connections may irreparably damage the chips. (An ohmmeter can be used to check connections if available.) If a connection is missing, check to make sure that it is not simply the result of a misconnected wire by checking the routing of all the other wires leaving the two connection points involved. If, after you apply power, sparks fly, you smell something burning, or one of the chips becomes hot, immediately shut the power off and recheck your circuit. Be aware that typically you will have prepared several circuits for the next week's lab and all are activated whenever power is applied. Two types of errors will be detected in debugging: wiring errors and design errors. Both types of errors may be detected by working backwards in the circuit from some point where the erroneous behavior was discovered. If a signal at any point does not have the expected behavior,

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then work back another level. Do not try to guess the trouble source; such a procedure usually just leads to confusion since the problem is never where you expect it to be. In the case of sequential circuits, the first thing you should do upon powering up is to get the circuit into a known state and then examine all signals for their proper logic values. The next check is to single-step the system clock and check that the proper state changes are made. Be particularly alert to glitches in the combinational logic of your circuit that are clocked into the flip-flops. Finally you can debug the system at full speed. The most common wiring errors are omitted and misplaced wires. An omitted wire results in a floating input to a device. A floating TTL input will show a voltage between 1.6 to 1.8 volts, in the threshold region. Misplaced wires sometimes result in short circuits between outputs. Two shorted TTL outputs trying to maintain opposite logic levels will produce an output voltage of about 0.6 volts and may cause damage to one of the driving gates. The most common design errors involve floating unused inputs. Quite often when an input is not used, the designer forgets to make any connection to it. The result is usually an effective logic 1 in TTL circuits however, you cannot depend on this and it is very poor design practice to leave an input unconnected. In CMOS circuits, the effective logic value of the input is indeterminate. Hence all unused inputs should be tied to an appropriate logic source.

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PRELAB 1. Read all of Lab 1 and Appendices A, B and C regarding the logicbox, breadboard, interfacing the breadboard to the logicbox, oscilloscope, WaveStar software, and function generator. 2. To acquire proficiency in the documentation of logic circuits, draw a complete logic and chip layout diagram for the logic circuit below (Figure 1.8). It is not essential that you understand the operation of this circuit, only the procedures for documenting it. First, construct a complete logic diagram, labeling each gate with its reference and part number. Also be sure to indicate the pin numbers and double check to make sure they are labeled correctly. Next, construct a chip layout diagram. You need to consult the pin assignment diagrams in the data sheets to determine the chip sizes. Try to arrange the chips in an orderly fashion so that those having connections between chips are as near as possible. (Since the breadboards you will use in lab require that the chips be arranged in a single vertical column, use this arrangement for this exercise.) Be sure to label each chip with its reference and part number. If you have any questions regarding the procedures involved in drawing a logic diagram or drawing a chip layout diagram, they can be answered in lab. Make sure to at least attempt to complete these drawings before lab, if no effort is evident, then no credit will be given. Note when constructing the chip layout, you must adhere to the following restrictions: 1) AND gates are available in one 74LS08 chip, 2) XOR gates are available in one 74LS86 chip, 3) Inverters are available in one 74LS04 chip, but 4) The OR gate must be constructed using one AND gate and inverters as needed.

X Y

OUT1

OUT2 Z

Figure 1.8 Schematic Diagram of Logic Circuit for Prelab. 1.13

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PROCEDURE Before performing the procedures listed below, read the report section of the experiment to assure you make all required measurements and record all required data. A. Documentation Check 1. Have your TA check your diagrams to ensure that they were done correctly. If you have any questions regarding any aspect of the diagrams, ask your TA now. B. Start-up 1. Familiarize yourself with the front panel controls on the oscilloscope available to you. Refer to Appendix B on the Tektronix TDS360 oscilloscope for their functions. Before taking any measurements on the oscilloscope, reset it to its factory defaults, as outlined in Appendix B, Initial Turn-on Procedure. 2. Connect the oscilloscope probe to the signal generator. You do not need to connect the generator to the logic box. Connect the probe directly to the red banana plug on the cable from the function generator and the probe's alligator clip to the black banana plug. 3. Set the function generator to produce a 5 volt amplitude, 1 kHz sinusoidal wave with no offset. The generator is activated by depressing the LINE pushbutton switch. The generator should be in the "normal" operating mode, indicated by the LED at the upper left hand corner. If not, depress the pushbutton switch immediately below until normal mode is selected. Engage the sine function pushbutton. Depress the FREQUENCY button and press the RANGE rocker switch until the LED next to kHz is lit and the decimal point is one digit from the left in the display. Adjust the FREQUENCY vernier until the display reads 1.00 kHz. Make sure the DUTY CYCLE vernier control is pressed in. Press the AMPLITUDE button and adjust the AMPLITUDE control until the display reads 5.00 volts. Make sure the offset switch is in its 12 o'clock position. None of the attenuation or output mode pushbuttons should be engaged. The HORIZONTAL SCALE and VERTICAL SCALE on the scope should be adjusted to produce an appropriate trace. Since the frequency of the sine wave is 1 kHz, 500 s might be a good setting for the HORIZONTAL SCALE. (Recall 1 kHz corresponds to a period of 1/1000 sec. = 1 ms) The five-volt amplitude of the waveform suggests that a 2 VOLTS/DIV for the VERTICAL SCALE might be a good setting for VOLTS/DIV. Also, it is a good idea to establish a ground potential reference level. To do this, press the VERTICAL MENU button and then press the softkey labeled COUPLING, on the bottom-left of the screen. A menu will then appear along the right side of the screen with three different options, DC, AC, and GND, select GND. Adjust the trace by turning the VERTICAL POSITION knob so that the trace is at the desired ground reference level--usually the center of the screen. Each time the VOLTS/DIV dial is changed, a new ground reference level should be 1.15

established. Observe how the trace moves vertically as the VOLTS/DIV dial is changed. The HORIZONTAL POSITION knob may be used to center the trace horizontally on the display. Be sure to return the coupling to DC to allow the DC input signals into the vertical amplifier. Use the WaveStar software to acquire a picture of the oscilloscope display. This procedure is outlined in Appendix B. After obtaining a satisfactory screen image, cut and paste it into your final report. Be sure to indicate the ground potential on the display. What is the peak to peak voltage of the waveform? What is its period? Show how you arrived at these figures from the scope display and dial settings. 4. Add a 5 volt offset to the sine wave signal by depressing the OFFSET pushbutton on the function generator and adjusting the OFFSET control until the display reads 5 volts. Record the display and appropriate vernier settings on the scope for both DC and AC couplings. These settings can be found under the VERTICAL MENU. Reconcile the differences between the traces under DC and AC coupling. Be sure to record your ground (0 volts) reference position. 5. Observe a 5 Hz triangle waveform with a 5 volt amplitude, 50% duty cycle, and no offset under both AC and DC coupling. To view this, restore the OFFSET control to its 12 o'clock position. Depress the triangle waveform pushbutton. Engage the FREQUENCY pushbutton and adjust the FREQUENCY vernier until the LED displays 5.00 Hz. You will need to adjust the HORIZONTAL SCALE knob until a clear triangle waveform appears. Note that the frequency of this waveform is much smaller than the previous 5 kHz wave. Again reconcile the differences between the DC and AC coupled displays of the signal. 6. Set the function generator to produce a 10 kHz sine wave with a 5 volt amplitude, 50% duty cycle, and no offset. Set the HORIZONTAL SCALE to 50s. Adjust the TRIGGER LEVEL knob and observe the effects on the display. Also try pressing the TRIGGER MENU pushbutton and then the SLOPE softkey at the bottom of the screen. Next change the EDGE SLOPE control along the right side of the screen. How do these controls determine on which part of the cycle of a periodic input signal to trigger, i.e., where in the cycle the trace begins? C. Logic Box Evaluation 1. Connect the logic box to the power supply, then connect the cable from the logic box to the breadboard. If you have any questions about how this is done, consult your TA. 2. Insert a single 74LS00 chip on the breadboard. Connect power and ground to the chip and connect three of the four 2-input NAND gates as shown in the circuit below. Finally connect the clock output from the logic box to the circuit input. Attach one probe from the oscilloscope to the circuit input and the other probe to the circuit output. (Make sure that the ground connector of the probe is connected to the logic ground i.e., the 74LS00 ground pin, not the power supply ground.) Using the oscilloscope capture the circuit input and output waveforms for two different clock signals by selecting two different switch positions. Be sure to indicate the switch position for each waveform.

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3. Attach an oscilloscope probe to Counter Output #3 from the logic box. Place the counter in the free-running mode and capture the output waveform for both AC and DC coupling. Place the counter in single-step mode and again capture the output waveform for both AC and DC coupling.

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EXPERIMENT 1-- INTRODUCTION TO LOGIC DESIGN AND LAB EQUIPMENT FINAL REPORT
I. Turn in your Logic and Chip Layout Diagrams. II. Measurements a) Sketch the sine waveform observed in part B.3.

VOLTS/DIV_________________

TIME/DIV_________________

b) What is the peak to peak voltage of the waveform? What is its period? What is its frequency? Indicate how you determined these values from the above sketch.

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c) Record the waveforms observed in part B.4.

DC Coupling

AC Coupling

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d) The waveforms observed using AC and DC coupling are different. Explain why.

e) Sketch the waveforms observed on the oscilloscope in part B.5.

DC Coupling

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AC Coupling f) Why is the AC coupled trace distorted?

g) From your observations in part B.6, explain how the TRIGGER LEVEL knob and the EDGE SLOPE softkeys determine where in the cycle of a periodic input signal the scope begins the trace.

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III. Analysis of Logic Box and Beardboard a) Sketch the input and output waveforms obtained in part C.2 for the two different input frequencies.

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b) Sketch the circuit you constructed showing the pin numbers on each gate.

c) What are the frequencies of the input and output waveforms for the two input frequencies you selected? How do the input and output waveforms differ? Is this what was expected?

d) Sketch the waveforms obtained in part C.3. Identify the waveforms, i.e., counter was free-running or single stepping and the vertical channel of the scope was in DC or AC mode.

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e) Does the counter output behave as expected and what is its frequency? What voltages were obtained at the counter output for a logic 0 and logic 1? (Remember that we are using a positive logic convention.)

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f) Explain how the counter output might be used to obtain the table of combinations for a combinational logic circuit.

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