SVPWM Based 3-Level Statcom For Reactive Power Management Under Line-Line

International Journal of JOURNAL Electrical Engineering and Technology (IJEET), ISSN 0976 INTERNATIONAL OF ELECTRICAL ENGINEERING 6545(Print), ISSN
N 0976 6553(Online) Volume 4, Issue 3, May - June (2013), IAEME & TECHNOLOGY (IJEET)
ISSN 0976 6545(Print) ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), pp. 167-187 IAEME: www.iaeme.com/ijeet.asp Journal Impact Factor (2013): 5.5028 (Calculated by GISI) www.jifactor.com
IJEET
IAEME
SVPWM BASED 3-LEVEL STATCOM FOR REACTIVE POWER MANAGEMENT UNDER LINE-LINE FAULT IN A TRANSMISSION LINE
S.M.Padmaja1, Dr. G. Tulasi RamDas 2
1
(Associate Professor, EEE Dept., Shri Vishnu Engg. College for Women, Bhimavaram, AP, INDIA) 2 (Vice Chancellor, JNTUK, Kakinada, AP, INDIA)
ABSTRACT A fault in the power transmission system results in the failure of electrical equipment either due to insulation failure or end of current flow due to open circuit. Although manufacturers carefully design the short circuit rating of the power system equipment, in order to safely withstand the sudden passage of high current for a specified duration, it has been continuous challenging issue to pre estimate the severity of fault. At the same time, fast retrieving of the steady state and transient stability is also an important issue. The immediate effect of a fault is severe voltage sag, which remains a negative impact on the transmission system voltage stability leading to mismanagement of reactive power. So, there is every need to pre analyze the severity of the fault with respect to its precise location and its consequence under different loading considerations. A special requirement for the fast recovery of normal voltage is obtained from Flexible Alternating Current Transmission Systems (FACTS) technology. The full compensating current for the reactive power management under low voltages are met through Static Synchronous Compensator (STATCOM) from FACTS family. In this paper the authors concentrated on the complete analysis of Line-Line fault occurred in the standard IEEE 14 bus system. This fault analysis and evaluation module reduces down time of the transmission or distribution lines and supports the quick restoration of power. To achieve the satisfactory performance during steady state and transient operation of power system, advanced controllers like space vector pulse width modulation (SVPWM) techniques are implemented. Also the dynamic response of the 2-level SVPWM controlled STATCOM and 3-level SVPWM controlled multilevel STATCOM and their impact on the
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), IAEME
nearby buses is analyzed and validated using MATLAB/ SIMULINK environment. The results shown in this paper indicates the effectiveness of the SVPWM control strategy on the dynamics of 2-level and 3-level STATCOM. Keywords: Fault, Reactive power management, Space vector pulse width modulation, Static synchronous compensator, 3-level Multilevel converter. 1. INTRODUCTION
Majority of faults in power systems typically occur on overhead transmission lines and bus bars combined with substation equipment. A fault is an abnormal condition occurred due to either short circuit or open circuit at the transmission lines and supporting equipment. Short circuit faults are mainly due to insulation failure that occurs because of degradation of insulation over time, over voltage and over stress and weather conditions [1], [2]. This can proceed to secondary failure as open circuit fault with the end of flow of current. The fault will ultimately result in equipment failure depending upon its severity and can lead to severe economic losses. Faults are of different types depending on the path of their occurrence. Short circuit faults can occur between the lines, between line and the ground or both as a simultaneous fault. The three phase fault affects the three lines symmetrically and noted as a balanced fault and all other faults are said to be unbalanced. The negative impact of penetration of the fault on the nearby areas results in voltage sags or voltage swells, voltage flicker, loss of generation for frequency support and thus affect the overall stable operation of the power system [3]. The critical issue is the risk of voltage collapse for the lack of reactive power support [4], [5]. Therefore, the fault severity needs to be pre assessed to design the standard short circuit rating of the infrastructural electrical equipment before their procurement and installation. This helps in the safe operation of power system equipment and thus the general public under diverse environmental and overstress conditions. The fast emerging power electronic controllers of FACTS plays a critical role with the ever increasing complexities in power systems. The latest FACTS family includes Static Synchronous Compensator - STATCOM, Static Synchronous Series Compensator- SSSC and Unified Power Flow Controller UPFC [6]. The solid state switching devices of these three FACTS controllers are based on Gate Turn-Off Thyritors-GTOs, Insulated Gate Bipolar Transistor (IGBTs). Specifically, STATCOM is a shunt compensating device that is capable of injecting or absorbing reactive power instantaneously at the output terminals. A STATCOM behaves as an adjustable voltage source connected to a utility bus through magnetic coupling [7], [8]. The DC side voltage of the STATCOM is adjusted by the charging and discharging of the DC capacitor to balance the instantaneous power equality constraint at the input and output terminals of the STATCOM [9]. The capacity of independent control of real and reactive power of STATCOM improves the power system performance through dynamic voltage control, power oscillation damping and transient stability. STATCOM with multilevel concept is an extended topology with enhanced power quality employed with high power-rating converters to overcome the limitations of the current and voltage range of the semiconductor switches [10]. The multilevel converters (MLC) give increased number of voltage levels through parallel or series connection of the fundamental topologies such as Diode Clamped type, flying capacitor type and cascaded H168
Bridge Multilevel converters for further smoothening of the sinusoidal AC output. Diode clamped topology based multilevel converter offers superior performance in realizing the STATCOM at both fundamental and high switching frequencies [11]. Multilevel concept offers new horizons in terms of power system control, with the potential to independently control the power system parameters like bus voltage and line active and reactive powers. Further the advantages of multilevel converters include high voltage capability, good electromagnetic compatibility, decreasing switching frequency and thus switching losses and decreasing total harmonic distortion (THD). However, as the number of voltage levels increase, the need of power electronic devices increases and which in turn need an advanced control technique to meet its complex operation. Space Vector Pulse Width Modulation (SVPWM) technique is an advanced modulation technique with optimized switching strategy to mitigate the lower order harmonics [12], [13], [14]. This paper tests and analyses the performance evaluation of a standard IEEE-14 bus system shown in Fig. 1 incorporated with non linear loads at all buses and a line-line fault at bus number 3. Considering the constraints of cost effectiveness and loss sensitivity, the optimum location of 2-level and 3-level based STATCOM in IEEE-14 bus system is chosen as bus number 14 and its impact on the nearby buses is investigated [15], [16], [17]. The performance of SVPWM switching strategy is tested on the simulated fault data with 2-level VSC and 3-level diode clamped multilevel converter (DCMC) adapted as STATCOM. Moreover, a comparison is made between the dynamic performance of 2-level VSC and 3level DCMC based STATCOM in the management of reactive power and voltage stability, under non linear loads with line-line fault.
Fig. 1. IEEE 14 Bus System

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2.
STATCOM MODEL
For the systematic operation of STATCOM, a mathematical model is developed [18]. The two terminal sides of the STATCOM are connected, one to the utility AC system and the other to a DC capacitor. It is desirable to transfer the dynamic model of STATCOM towards AC and DC sides, from abc to dqo frame as the d and q current components of STATCOM proportionately control the exchange of real and reactive components respectively between the STATCOM and the utility system. The utility side three phase voltage equations of the STATCOM are expressed as, v i v = R i L v i R Where, R = 0 0 0 R 0 v i i + v v i
(1) 0 L 0 0 0 Ls
The STATCOM terminal voltage is expressed as a function of its DC bus voltage. sin t v v = M v sint v sint
0 L 0 and L 0 R 0
(2)
Where, t t The DC side voltage Vdc of STATCOM is represented as,
The dynamic model of STATCOM AC and DC sides represented in equations (2) and (3) are transferred from abc to dqo frame by using the transformation matrix K shown in equation 5. cos K sin 1 2 cos sin 1 2

The DC current idc is expressed in terms of line currents [ iabcs ] at the STATCOM terminal. sin i i= M i sin (4) i sin

)= i
cos sin 1 2
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The d and q axis voltage equations of the STATCOM connected at the AC side load terminals are shown in equations (6) and (7) [18] in which the d and q current components are also coupled. d 6 v v R i L i L dt v R i L d i L dt
Based on above equations 6 and 7, the amplitude and angle modulation index M.I are calculated from equations (8) and(9), M= v v = V
tan
v v
8 9
Fig .2. 2-Level SVPWM Controlled STATCOM Fig. 2 shows the model of 2 level Voltage Source Converter (VSC) applied as a STATCOM at bus-14 of Fig.1. A coupling transformer is used to link the STATCOM to the AC system. The loads on the IEEE14 bus network are diode bridge rectifiers as non linear loads. The STATCOM should regulate the voltage at the load terminals and its DC bus voltage through reactive and real power exchange with the AC system. This model is used to verify the dynamic response of SVPWM controller of the STATCOM following a line line fault at bus 3.
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3.
2 LEVEL SVPWM STRATEGY
The conventional PWM methods with necessary extensions in their corresponding techniques, still find some redundancy in the application of zero vectors and in the utilization of DC bus voltage of the 2 level VSC. There is an increasing trend of using SVPWM technique because of its easier digital realization and better DC bus utilization. The methodology of SVPWM is clearly explained in [19]. 3.1 SWITCHING STATES The distinct possible switching states of the 2-level VSC are represented as eight voltage vectors, out of which six are active states (V1 V6) and two are null states (V0 , V7). The active states contribute output line voltage as +Vdc or Vdc , where as null states does not contribute any output voltage for VSC. The eight voltage vectors are tabulated in Table 1. 1 denotes ON state of the switch and 0 denotes OFF state of the switch. TABLE 1. 2-Level Inverter Voltage Vectors Voltage Switching States Line-Neutral Vectors Voltages S1 S3 S5 V0 0 0 0 0 0 0 V1 1 0 0 Vdc 0 -Vdc V2 1 1 0 0 Vdc -Vdc V3 0 1 0 -Vdc Vdc 0 V4 0 1 1 -Vdc 0 Vdc V5 0 0 1 0 -Vdc Vdc V6 1 0 1 Vdc -Vdc 0 V7 1 1 1 0 0 0 3.2 SPACE VECTOR DIAGRAM The eight switching vectors constitutes a space vector diagram which resembles a hexagon with its center coincide with the origin of d-q plane. The six active vectors project to the vertices of the hexagon and the remaining two zero vectors lie at the origin as shown in Fig. 3. The region between two consecutive vectors is identified as a sector covering an angle of 60. In total there are six sectors covering the entire 360. The SVPWM scheme proposes the suitable selection and execution of the switching states of the triangle with respective on times.
Fig.3. Hexagon representation of switching state vectors of 2 level VSI

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3.3 VOLTAGE VECTOR SYNTHESIS According to SVPWM switching strategy, the average AC output voltage is synthesized by the three nearest consecutive switching voltage vectors distributed over a sampling period (Ts) should match the reference voltage vector Vref. The Vref is the resultant of d-q axis voltages. The ideal trajectory of the Vref describes a circle which is inscribed in a hexagon as shown in Fig.4. For the case of line side convertor operation in AC-DC-AC conversion, it should be followed that, SVPWM scheme is restricted to under modulation region only [20]. The upper limit in under modulation range is M = V.
Fig.4. Inscribed circular path of Hexagon 3.4 SECTOR IDENTIFICATION The ideal trajectory of the Vref is from 0 to 360 in a circular path which benefits into a sinusoidal output voltage of VSC. The incircle of the hexagon almost include the six sectors (1, 2, 3, 4, 5 and 6). The position of the reference vector can be identified with the help of calculated from equation 9. The MATLAB / Simulink Fig. 5 shows the possible conditions of the placement of Vref .
Fig. 5. Sector Identification

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The Fig.5 describes that, suppose the angle lies among (0 60), (60 120), (120 180), (180 240), (240 300) and (300 360), then Vref lies in the sectors 1, 2, 3, 4, 5 and 6 respectively. 3.5 ON- TIME CALCULATION The on duration of each switching vector is determined from the following volt-time balance relationship [19]. For example, sector 1 is considered. V T V T V T V T T T T T 10
Where,
The line-neutral voltages are calculated from Table 1 and represented in equations (11), (12) and (13) V 11 V V V 0 V e

V cos jsin

12
Equating real and imaginary parts on both sides, 2 1 V T T cos T 3 3 V 1 T V sin T V
V V . e V cos sin
13
14
Solving for T and T T
15
The ON times of the respective space vectors in the other sectors are determined in the similar fashion. The generalized equations for calculating time duration of the respective space vectors in any of the sectors is given by equations (19) and (20).
T T T T
3T V sin V
3TV sin V 3
16
18
17
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n1 3T||V | sin V 3 3 n1 3T ||V | sin V 3
n refers to sector 1 6 and 0 60 The ON time durations T0, T1, T2 of the 3 nearest voltage vectors with respect to the position of reference vector in each sector are utilized in the calculation of total switching time of each switch. Also, for minimum switching transition losses, a particular switching sequence is demanded to generate the reference space vector. 3.6 SWITCHING PATTERNS The selection of switching sequence highly influences on the total harmonic distortion, DC capacitor voltage and switching losses of the 2-level VSC. The ultimate main consideration leads to cost function which necessitates the proper selection criteria of the switching pattern [18]. Fig. 6 shows the selected directions of the switching transition in a sector from one vector to the other. Both forward and reverse switching sequences pertaining to all six sectors are tabulated in Table 2.
T T T T
20
19
21
Fig. 6. Switching Transition with Directions TABLE 2. Switching Sequences of Voltage Vectors Sector 1 2 3 4 5 6 Forward direction V0 V1V2V7 V0V3V2V7 V0V3V4V7 V0V5V4V7 V0V5V6V7 V0V1V6V7 Reverse direction V7V2V1V0 V7V2V3V0 V7V4V3V0 V7V4V5V0 V7V6V5V0 V7V6V1V0
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3.7 SWITCHING TIME FOR EACH SWITCH The PWM switching pattern helps to determine the on time of each switch. Fig.7 depicts the switching status of upper switches S1, S3 and S5 corresponding to T0, T1 and T2 with Vref in sector 1. The pattern includes the adjacent active vectors and zero vectors symmetrically distributed into respective switching periods in each sector. It is noted that the switching status of lower switches S4, S6 and S2 is complement to that of upper switches. The on time calculations of upper switches in each sector are tabulated in Table 3.
Fig. 7. Switching Pattern in Sector 1
Fig. 8. MATLAB/Simulink model for generation of SVPWM pulses
TABLE 3. Switching time of upper switches of 2-level VSI Sector 1 2 3 4 5 6 S1 2 2 2 2 2 2 S3 2 2 2 2 2 2 S5 2 2 2 2 2 2
The sum of the respective ON times of each phase from all the sectors gives the total operation times of three phases Ta, Tb, Tc, respectively. Based on triangular carrier PWM wave comparison with Ta, Tb, Tc, the space vector pulse width modulated pulses PWM1(R+), PWM3 (Y+), PWM5 (B+) for the upper switches and PWM 2 (R-), PWM 4 (Y-), PWM 6 (B-) for the lower switches are generated as shown in Fig.8 and fed to the 2-level VSC.
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4.
SECTOR IDENTIFICATION FOR 3 LEVEL SVPWM STRATEGY
Space vector PWM with its additional advantages is showing growing popularity in multilevel converter applications. Compared to 2-level converter, SVPWM provides superior harmonic quality, easy sharing of large voltage among the series devices of 3-level converter leg and improvement of under modulation range near to 90% [20]. However, in MLC, with the increase of number of switches, the converter switching state will increase and the SVPWM technique becomes considerably more complex than that for 2-level converter [22,23].
Fig. 9. 3-level Voltage Source Inverter In this paper the authors employed the SVPWM technique for a 3-level diode clamped converter based STATCOM. Fig. 9 shows the diode clamped topology of a 3-level converter. Each phase leg consists of four semiconductor switches, four freewheeling diodes and two clamping diodes. Each phase develops an output voltage with three different levels as 0, +Vdc/2, -Vdc/2. Based on the 2-level SVPWM simplification, the 3-level SVPWM is alleviated. 4.1 SWITCHING STATES The 3-level diode clamped converter has 12 switching devices with four switches in each leg. The 12 switches contribute to 33 = 27 possible switching voltage vector combinations. Out of that, 24 are active states and remaining 3 are zero states. Based on the magnitude, the voltage vectors are characterized into four groups like zero voltage vectors, small voltage vectors, medium voltage vectors and large voltage vectors. The angular position of each switching voltage vector with respective to the reference d-axis and their respective magnitudes are shown in Table 4. It is observed that, for different switching states, there exists the same voltage level. The different three phase voltage levels that appear are 2/3 Vdc, Vdc/3 and Vdc/3.
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TABLE 4. Magnitudes of 27 Voltage Vectors at Different Switching States

Angle 0 0 Space Vector V0 Small Vector V1 Small Vector V2 Small Vector V3 Small Vector V4 Small Vector V5 Small Vector V6 Large Vector V7 Large Vector V9 Large Vector V11 Large Vector V13 Large Vector V15 Large Vector V17 V8 V10 V12 V14 V16 V18 Medium Vector Medium Vector Medium Vector Medium Vector Medium Vector Medium Vector 1 0 -1 -1 0 1 0 1 1 0 -1 -1 -1 -1 0 1 1 1 1 -1 1 -1 -1 1 -1 1 1 -1 1 -1 1 1 -1 Vector Type Zero 1 0 -1 1 0 1 0 0 -1 0 -1 0 -1 1 0 1 Switching State 1 0 -1 0 -1 1 0 1 0 1 0 0 -1 0 -1 -1 1 0 -1 0 -1 0 -1 0 -1 1 0 1 0 1 0 -1 0 1 V 3 1 V 3 1 V 3 1 V 3 2 V 3 2 V 3 2 V 3 2 V 3 2 V 3 2 V 3 3 3 1 3 3 1 3 1 3 1 1 1 2 V 3 V V V V V V 1 V 3 3 Magnitude No.of Switching combinations
2 3 4 3 5 3 3 2 3 4 3 5 3 6 5 6 2 0
2 2
2 2 1 1 1 1 1 1 1 1 1 1 1 1
5 6 2 6
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4.2 SPACE VECTOR DIAGRAM The switching voltage vectors that corresponding to the space vectors are again represented in a hexagon plane same as the 2-level converter. The hexagon plane of Fig. 10 is divided into six main sectors, where each sector covers corresponding to 60. Each sector is again subdivided into four regions 1, 2, 3 and 4 as shown in Fig. 10. By dividing the 60 span into sub regions, the position of reference vector is further deeply synthesized by the 3 adjacent switching voltage vectors.
Fig. 10. Hexagon representation of switching state vectors of 3-level VSI As a result, the quality of AC side voltage of the STATCOM is improved. The large voltage vectors point to the vertex of larger hexagon, small voltage vectors point to the vertex of inner hexagon and medium voltage vectors point to the midpoint of the side of large hexagon as shown in Fig. 10. 4.3 DETERMINATION OF SECTOR AND REGION The determination of main sectors in a multilevel converter is similar to that of 2-level VSC. Here, the reference vector is considered to be in sector 1 making an angle with respective to the d-axis. To identify the region, in which it is placed, resolve the reference vector mn into m1 and m2 along the sides of the sector as shown in Fig. 11(a).
Fig. 11(a)
Fig. 11(b)
Fig.11. Determination of region in sector 1

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The sides of the regions are assumed to have length equal to unity. To ease the calculation of the values of m1 and m2, they are projected to form a right angled triangle with sides, p, q and r as shown in Fig. 11(b). The following equations are framed using sine rule. q sin 2 sin 3 m2 2 p 2 2 22 24
p m q
25 m1 mn cos p cos 26 3 2 m1 mn cos mn sin cos 27 3 3 sin m1 mn cos 28 3 Based on the values obtained for m1 and m2 from equations (24) and (28), the region for the location of reference vector is identified from the conditions shown in Table 5. Table.5. Conditions to determine the location of reference vector in each region Condition Region m1 1 m2 1 m1 m2 1 m2 1 m2 1 m1 m2 1 m2 1 m1 1 1 2 3 4
mn sin 3 m1 mn cos r
m sin
23
The ON time calculation of the reference space vector is based on its position and location within a sector and also on the ON times of the three nearest adjacent switching vectors. 4.4 SWITCHING PATTERN The pattern followed for the switching states in each region shows considerable effect on the level of harmonic content and switching frequency. Therefore, care is taken that, only one device operates at any time during the switching transition from one state to other. Consider the reference voltage vector in region 3. It is surrounded by the three nearest switching vectors V1, V2, V8 as shown in Fig. 10. It is observed that, V1 is available with two switching states [100, 0-1-1], V2 with two switching states [110, 00-1] and V8 with one switching state [10-1]. The duty cycles of these switching vectors are uniformly distributed within the sampling time Ts which correspond to 10 segments as shown in Fig.12. With
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similar analysis, the individual switching vectors for all the regions in each sector are uniformly distributed within the sampling time. In all the sectors, region 1 is divided into 14 segments, region 2 and 4 into eight segments and region 3 into ten segments. The switching pattern of region 3 given in Fig. 12(a),(b),(c), shows the respective three phase voltages with their switching status. However, the switching status of lower switches in each phase that is S3a, S4a; S3b, S4b; S3c, S4c; are complement to that of their upper switches.
Fig. 12(a). Switching pattern for phase A voltage and demanded status of S1a & S2a
Fig. 12( b). Switching pattern for phase B voltage and demanded status of S1b & S2b
Fig. 12( c). Switching pattern for phase C voltage and demanded status of S1c & S2c 4.5 ON- TIME CALCULATION In SVPWM, volt-time balance equation is followed to determine the ON times of the switching states and the reference vector [21]. The multilevel ON time calculation is similar to that of 2-level VSC. Therefore, the ON time calculation of reference vector in a triangular sector of 2-level VSC explained in section 3.5 is also used for the calculation of any other triangular region of the sector. The ON time calculation method in any of the sectors is similar, so the operation in sector 1, region 3 is considered.
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V 1
V 8 Vdc Ta
V2
1 V 3 dc
j 1 Vdc e 3 3
j 3 Vdc e 6 3
30
29
31
Substituting equations (29), (30) and (31) into volt-time balance relationship equation (10), we get jsinTs
3 1 3 1
Vdc cos jsin Tb Vdc cos jsin Tc Vref cos

6 6 1 3 3 3
Dividing the equation (32) into real and imaginary parts eases the calculations for the duty cycle. Equating the real parts, 1 1 1 Vdc Ta Vdc Tb Vdc Tc Vref cosTs 33 2 6 3 Multiplying above equation with V dc 3 1 Vref Ta Tb Tc 3 cosTs Vdc 2 2 Equating the imaginary parts, 1 1 1 3 Vdc Tb V T Vref sinTs 3 2 dc c 3 2 Vref 3 3 Tb Tc 3 sinTs 2 2 Vdc
3 Vdc 3
32
34 35 36
Multiplying above equation with
By solving equations (34), (36) and (37), we get Ta TS 1 2Msin Tb TS 2Msin 1 3 Tc TS 1 2Msin 3
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The uniform distribution of sampling time is expressed as TS Ta Tb Tc
38
37
40
39
Where M is the Modulation index and expressed as, Vref 41 Vdc Similar procedure is applied to decide the total switching time of each switch in the remaining regions of all the sectors [24]. The method of generating the PWM pulses is the same as that in 2-L SVPWM. The total ON time of each switch in each region over a sampling time TS is compared with a triangle carrier to generate the SVPWM pulses which are then fed respectively to the 3-level diode clamped multilevel converter. 5. PERFORMANCE EVALUATION In this paper a standard IEEE 14 bus system is considered to evaluate its performance through 2-level and 3-level space vector pulse width modulation controlled STATCOM. The system is subjected to a line-line fault with fault impedance at bus-3. All the loads considered on the IEEE-14 bus system are non linear loads. The STATCOM is placed at the weakest bus-14 as it faces the lowest voltage. An analysis is made on the performance of the system under diverse conditions mentioned as below and their respective simulation results are presented in Fig. 13. a) Non linear load with line-line fault at bus-3 without STATCOM b) With 2-level SVPWM controlled STATCOM at bus-14 c) With 3-level SVPWM controlled STATCOM at bus-14 d) Comparison of both the schemes with reference to voltage, active and reactive powers e) Impact on the nearby buses 5.1 LINE-LINE FAULT The system with nonlinear load initially takes certain minimum time to approach the steady state condition. Due to sudden line- line fault, the voltages at the other buses of the network falls momentarily depending on the severity and duration of the fault [3]. However, the STATCOM regulates the voltage by balancing the real and reactive powers with the nearby buses in a very short duration. In this paper, STATCOM is assumed to be connected in the system from the starting of the operation. Therefore, during the steady state conditions, it draws a little real power for the maintenance of its DC capacitor charge and to compensate its losses. Bus-3 is subjected to a line-line fault at t=0.1sec to 0.12sec. The results from Table 6 and Fig. 13 depicts the comparative response of 2-level and 3-level STATCOM on the effective maintenance of the system during and subsequent to the fault. Fig. 13(a) shows the output voltage obtained from 3-level DCMC connected at bus 14. Fig. 13(b) shows the comparison of capacitor DC voltage. Fig. 13(c) and (d) shows the STATCOMs real and reactive current components Id and Iq exchanged during the fault disturbance. The tabulated values of line voltages, active powers and reactive powers in the Table 6 are acquired during the worst condition of the fault duration. From these results it is observed that during the time of fault clearance, 3-Level STATCOM exhibits fast fault recovery response in regulating the load voltage and regaining the steady state condition as shown in Fig. 14(a). The STATCOM injects the required reactive power instantaneously and therefore, the burden of drawing the reactive power from nearby buses is reduced as shown in Fig. 14(b)
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M 3
300 250 C a p a c it o r V o lt a g e V d c 200 150 100 50 0 2-Level SVPWM 3-Level SVPWM 0 0.02 0.04 0.06 0.08 0.1 time 0.12 0.14 0.16 0.18 0.2
Fig.13(a)
0.5
0.05 S T A T CO M real c urrent c om ponent Id 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 3-Level STATCOM 2-Level STATCOM 0 0.02 0.04 0.06 0.08 0.1 Time 0.12 0.14 0.16 0.18 0.2
Fig.13(b)
3-Level STATCOM 2-Level STATCOM
S T A T C O M Reac tiv e c urrent c om ponent
-0.5
0.02
0.04
0.06
0.08
0.1 Time
0.12
0.14
0.16
0.18
0.2
Fig.13(c)
Fig.13(d)
Fig. 13 With STATCOM connected at bus 14 (a) STATCOM 3-Level output voltage (b) Comparison of STATCOM DC capacitor voltage Vdc (c) Comparison of the STATCOM real current components Id ( d) Comparison of the STATCOM reactive current components Iq
1.4 1.2
0.02 0.03
V o lt a g e s in (p u )
R e a c t iv e P o w e r in M v a r
1 0.8 0.6 0.4 0.2 0 0 0.02 0.04 0.06 0.08 0.1 0.12 Time 0.14 0.16 0.18 0.2 Without STATCOM With 2 Level STATCOM With 3Level STATCOM
0.01
-0.01 without STATCOM With 2-Level STATCOM With 3- Level STATCOM 0 0.02 0.04 0.06 0.08 0.1 Time 0.12 0.14 0.16 0.18 0.2
-0.02
-0.03
Fig. 14 (a) Comparison of the load voltages at Bus-14 (b) Comparison of the reactive powers in line 12-13
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Table. 6 The voltages, active powers and reactive powers available in the lines during the line-line fault
Line Voltages Line No. 1-2 2-3 1-5 2-5 2-4 4-5 4-3 7-8 7-9 9-10 6-11 6-12 6-13 11-10 12-13 9-14 13-14
without statcom
Active Power in MW
without statcom
Reactive Power in Mvar Without statcom 0.075 0.03 0.0445 0.0173 0.016 0.001 0.0034 -0.02 -0.0045 0.00135 0.0156 0.009 0.0243 -0.0011 0.0022 0.00715 0.0105
2-Level 0.939 0.894 0.926 0.92 0.92 0.9 0.885 0.946 0.94 0.933 0.938 0.944 0.94 0.94 0.935 0.94 0.93
3-Level 0.93 0.9 0.926 0.92 0.92 0.9 0.88 0.945 0.94 0.935 0.938 0.945 0.94 0.94 0.94 0.95 0.936
2-Level 0.3525 0.245 0.1918 0.123 0.1366 0.2662 0.12 0.011 0.0115 0.0082 0.0313 0.023 0.0582 0.02 0.0065 0.03 0.0295
3-Level 0.38 0.288 0.2165 0.143 0.16 0.3 0.127 0.015 0.0175 0.009 0.0322 0.0263 0.0712 0.0206 0.011 0.063 0.0495
2-Level 0.0725 0.031 0.041 0.0132 0.012 0 -0.0026 -0.02 -0.0045 0.0017 0.016 0.0065 0.0144 -0.0012 -0.0005 -0.0095 -0.003
3-Level 0.05 0.02 0.024 -0.002 -0.006 -0.045 -0.0035 -0.036 -0.009 0.0035 0.0168 0.004 0.004 -0.0117 -0.004 -0.04 -0.02
0.94 0.89 0.926 0.92 0.92 0.9 0.884 0.945 0.934 0.928 0.934 0.937 0.9335 0.932 0.927 0.92 0.911
0.346 0.245 0.185 0.1173 0.1307 0.256 0.124 0.013 0.01 0.0092 0.0309 0.022 0.052 0.0191 0.0055 0.02 0.02
6. CONCLUSION This paper analyzes on the SVPWM control strategy applied for a 2-level VSC and 3level diode clamped Multilevel Converter connected as a STATCOM at bus-14 of the IEEE14 bus system under a line-line fault interruption condition at bus 3. To ensure safety, fault analysis is carried out during and subsequent to the fault occurrence and its impact on each line and bus is investigated with respect to voltage, active power and reactive power. The fast dynamic response of SVPWM controlled STATCOM under faulty conditions was evaluated based on digital time-domain simulation studies in the MATLAB/SIMULINK environment. The results reveal the superior performance of the selected SVPWM switching strategy applied on a 3-level diode clamped multilevel converter based STATCOM in balancing dc capacitor voltage and regulate line voltage, active and reactive power, due to a commanded disturbance.
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SVPWM Based 3-Level Statcom For Reactive Power Management Under Line-Line

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Fig. 1. IEEE 14 Bus System

Where, t t The DC side voltage Vdc of STATCOM is represented as,

2 LEVEL SVPWM STRATEGY

Fig.3. Hexagon representation of switching state vectors of 2 level VSI

Fig. 5. Sector Identification

Equating real and imaginary parts on both sides, 2 1 V T T cos T 3 3 V 1 T V sin T V

Solving for T and T T

n1 3T||V | sin V 3 3 n1 3T ||V | sin V 3

Fig. 7. Switching Pattern in Sector 1

Fig. 8. MATLAB/Simulink model for generation of SVPWM pulses

TABLE 3. Switching time of upper switches of 2-level VSI Sector 1 2 3 4 5 6 S1 2 2 2 2 2 2 S3 2 2 2 2 2 2 S5 2 2 2 2 2 2

SECTOR IDENTIFICATION FOR 3 LEVEL SVPWM STRATEGY

TABLE 4. Magnitudes of 27 Voltage Vectors at Different Switching States

Fig.11. Determination of region in sector 1

Vdc cos jsin Tb Vdc cos jsin Tc Vref cos

Multiplying above equation with

The uniform distribution of sampling time is expressed as TS Ta Tb Tc

S T A T C O M Reac tiv e c urrent c om ponent

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