Zero voltage switching active clamp buck-boost stage Cuk converter

B.R. Lin and C.L. Huang Abstract: The paper presents an active clamp buck-boost stage Cuk converter to achieve soft switching commutation. An auxiliary switch and a clamp capacitor are connected in parallel with the primary side of the transformer to absorb all the energy stored in the transformer leakage inductance. The resonant inductance and the clamp capacitance are resonant to achieve zero-voltage switching (ZVS) of the auxiliary switch. On the other hand, the resonance between the resonant inductance and output capacitance of the main switch will achieve ZVS of the main switch in the proposed converter. The principle of operation and system analysis are presented. Design considerations of the proposed converter are also provided. Experimental results for a 170 W prototype circuit operating at 70 kHz are given to demonstrate the effectiveness of the proposed converter.

Introduction

Soft-switching techniques, such as zero-voltage switching (ZVS) and zero-current switching (ZCS) [1, 2] for DC/DC converters, have been proposed to substantially reduce switching losses and, hence, attain high efciency at increased frequency. However, the voltage stresses on the power switches are too high in the resonant converters, especially for the high-input DC voltage. The asymmetrical PWM techniques [3 5] were proposed to achieve ZVS turn-on and to increase circuit efciency. The drawback of the asymmetrical converter is that the voltage and current stresses of switching devices are related to duty cycle. Full-bridge converters with phase-shift pulse-width modulation (PWM) technique [6, 7] have been proposed to regulate the output DC voltage and to achieve ZVS operation of power switches. However, the high cost and narrow ZVS range for the lagging leg of the phase-shift full-bridge converter are the main disadvantages. Active clamp techniques [8 10] were proposed to limit the voltage stress of the main switch and to reduce the switching losses. The high frequency operation in the Cuk converter is desirable because of the reduction of reactive component size and cost. Buck-boost conversion ratio in the Cuk converter enables arbitrary output voltage. An isolated ZVS Cuk converter is proposed in this paper to achieve ZVS operation for both main and auxiliary switches. An active clamp buck-boost stage circuit added to the Cuk converter allows the utilisation of leakage inductance of the transformer to achieve ZVS operation and to limit the voltage stress on the power switches. The ZVS operation will reduce the switching losses and increase the circuit efciency. The circuit conguration, principle of
# The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20060157 Paper rst received 23rd April and in revised form 19th July 2006 The authors are with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: linbr@yuntech.edu.tw IET Electr. Power Appl., 2007, 1, (2), pp. 173 182

operation and design considerations of the proposed converter are presented. First, the circuit conguration of the proposed converter is discussed. The system analysis, steady state analysis and circuit design consideration are presented. Finally, experimental results based on a 170W prototype circuit are presented to verify the effectiveness and performance of the proposed converter. 2 Circuit conguration

The circuit conguration of the proposed converter is shown in Fig. 1. L1 and L2 are input and output inductors, respectively. S and Sa are main and auxiliary switches. The capacitors C1 and C2 are medium for transferring energy from the source to the load. Cc and Co are the clamp capacitor and output capacitor, respectively. Lm is the magnetising inductor of the isolation transformer. D is a freewheeling diode. Lr and Cr are resonant inductor and resonant capacitor, respectively. The active clamp circuit, including the auxiliary switch Sa and the clamp capacitor Cc , allows the utilisation of transformer leakage inductance to achieve ZVS operation and limits the peak voltage stress of the main switch S. If the turn ratio of the isolation transformer is one, the proposed converter provides an output voltage which is less than or greater than the input voltage. In the proposed converter, main switch S and clamp switch Sc are all turned on at ZVS, based on the resonance during the commutation interval. This enables the converter to operate with higher switching frequency and reduction in the size of the reactive components. 3 Operation principle

Some assumptions of the proposed converter are made for the system analysis: (1) the clamp capacitance Cc is larger than the resonant capacitance Cr and the clamp capacitor voltage vCc is a constant value when main switch S is turned on; (2) the input voltage vin is a constant value; (3) the input and output inductances L1 and L2 are
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Fig. 1 Circuit conguration of the proposed active clamp Cuk converter

large enough. (The input and output currents iL1 and iL2 are considered as the constant values); (4) Joule and iron losses are neglected in both inductances and transformer; (5) the resonant inductance Lr is smaller than the magnetising inductances Lm; (6) all semiconductor components are modelled as ideal; (7) the turn ratio between the primary winding turn of transformer and the secondary winding turn is n np =ns ; and (8) the energy stored in the resonant inductance Lr is greater than energy stored in the resonant capacitance Cr to achieve ZVS operation. The key waveforms of the proposed converter are given in Fig. 2. Based on Fig. 2, the main and auxiliary switches are turned on at ZVS. The switching losses due to switch turn-on instant are effectively reduced. However, both switching are not turned off at ZCS, therefore there are some switching losses at turn-off instant. The features of the proposed converter are ZVS turn-on, low-voltage stresses on the main and auxiliary switches, less additional circuit components in the conventional isolated Cuk converter (one switch and one clamp capacitor) and easy control algorithm using commercial PWM IC and gate driver. There are six operating stages of the proposed converter in a switching period. Fig. 3 gives the equivalent circuits of the proposed converter for each operating stage.

Fig. 3 Operation stages of proposed converter

a b c d e f Stage Stage Stage Stage Stage Stage 1 2 3 4 5 6 [t1 t2] [t2 t3] [t3 t4] [t4 t5] [t5 t6] [t6 t1]

Stage 1 (t1 , t , t2, Fig. 3a): In the rst stage, main switch S is turned on and auxiliary switch Sa is turned off. The input current charges the inductor L1 . The input current iL1 increases linearly: v 1 iL1 t iL1 t1 in t t1 L1 The capacitor voltage vCr vS,ds 0. The magnetising inductor voltage vLm vC1 Lm =Lm Lr . The magnetising current iLm decreases linearly. The inductor current iLr is expressed as iLr t iC2 t=n iLm t iC2 t=n
Fig. 2
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vC 1 Lm t t1 iLm t1 Lm Lr Lm 2

Key waveforms of proposed converter

iC2 t=n vC 1 t t1 =Lm iLm t1

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The main switch current iS iL1 iLr iL1 iC1. The secondary winding voltage of transformer vs vC1Lm/ [n(Lm Lr)]. The diode D is turned off. The inductor current iL2 equals iC2 and increases linearly iL2 t iC2 t iL2 t1

voltage vCc are expressed as follows ! t t3 vCc t vCc t3 cos p iL1 t3 Cc Lm Lr s ! Lm Lr t t3 sin p iLr t3 Cc Cc Lm Lr

1 vC 1 L m L2 nLm Lr  1  vC 1 vC 2 vo t t 1 iL2 t1 L2 n

 vC 2 vo t t 1 3

The positive current iC2 discharges capacitor C2 . This stage ends at time t t2 when main switch S is turned off. Stage 2 (t2 , t , t3 , Fig. 3b): At time t t2 , main switch S is turned off. The input inductor current iL1 and capacitor current iC1 charge capacitor Cr from 0 to vC1 vCc . The capacitor voltage vCr can be given approximately as vCr t iS t2 t t2 Cr 4

! t t3 iLr t iL1 t3 iLr t3 cos p Cc Lm Lr s ! Cc t t3 sin p iL1 t3 9 vCc t3 Lm Lr Cc Lm Lr Before the clamp capacitor current iCc becomes negative value, the auxiliary switch Sa turns on at ZVS. The clamp capacitor current iCc will decrease from a positive to a negative value. When the current iCc becomes negative, the clamp capacitor Cc begins to discharge. The capacitor voltage vCr vC1 vCc . As the inductor voltages vL1 and vL2 are negative, the input and output inductor currents iL1 and iL2 decrease linearly. The diode current iD io 2 iC2 . The magnetising inductor current increases linearly. The capacitor current iC2 n(iLr iLm). The capacitor current iC2 will decrease from a positive to a negative value. This operating stage ends when auxiliary switch Sa turns off. Stage 4 (t4 , t , t5 , Fig. 3d): At time t t4 , the auxiliary switch Sa turns off. As iLr iL1 , 0, therefore the main switch current iS is negative. The primary side voltage vLm nvC 2 and the magnetising inductor current increases linearly. The negative switch current iS 1 discharges capacitor Cr from vCc vC1 to 0 in this stage. The voltage vCr is approximately given as vCr t vCc t4 vC1 iLr t4 iL1 t4 t t4 Cr 10

The primary side voltage vLm (vCr 2 vC1)Lm/ (Lm Lr) vCr 2 vC1. The secondary side voltage vs vC 1 vCr =n. The magnetising current of the transformer in this stage is expressed as vCr vC1 t t2 iLm t2 Lm

iLm t

The time interval in this stage is very short, and the input current iL1 , switch current iS and capacitor current iC1 are almost constant in this stage. The diode current at the secondary side iD 0. The output inductor current in this stage is given as iL2 t iC2 t  1 vC1 vCr vC 2 vo t t2 iL2 t2 n L2 6

where iLr t4 iL1 t4 is negative. To ensure ZVS operation of main switch S, the capacitor voltage vCr should reach zero before the end of this stage. Hence the energy stored in the resonant inductor Lr must be greater than the energy stored in the resonant capacitor Cr Lr ! Cr vCc t4 vC1 2 iLr t4 2 11

At time t t3 , the capacitor voltage vCr vC1 vCc , the antiparallel diode of auxiliary switch Sa turns on and the primary side voltage vLm vCc . The diode D turns on at time t t3 . From (4) the time interval in this stage is given as v vCc Cr t3 t2 C1 iS t2

At time t t5 , the resonant capacitor voltage vCr 0 and the antiparallel diode of main switch S turns on. The diode D at the secondary side is in the free wheeling mode. From (10), the time interval in this stage is expressed as Dt45 t5 t4 vCc t4 vC1 Cr iLr t4 iL1 t4 12

Dt23

Stage 3 (t3 , t , t4 , Fig. 3c): The antiparallel diode of auxiliary switch Sa turns on and the diode D at the secondary side turns on at time t t3 . The transformer secondary side voltage vs 2 vC2 . Before the clamp current iCc becomes negative, the auxiliary switch Sa should be turned on to achieve ZVS. The input inductor current iL1 decreases linearly with the slope of (vin 2 vC1 2 vCc)/L1 . The voltage across the primary side vLm nvC2 . The clamp capacitor voltage vCc (t3) nvC2(Lm Lr)/Lm . The capacitor voltage vC1 is almost constant in this stage. The resonant current iLr and clamp
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This time interval is very short, therefore the primary side and secondary side currents are almost constant. Stage 5 (t5 , t , t6 , Fig. 3e): At time t t5 , the resonant capacitor voltage vCr 0 and the antiparallel diode of main switch S turns on. The secondary side diode is still in the free wheeling mode. The input inductor current, primary current and main switch current increase linearly. Before the main switch current iS1 becomes positive, the main switch S should be turned on to achieve ZVS operation. The secondary side diode current iD decreases. This stage ends when main switch S turns on at ZVS.
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Stage 6 (t6 , t , t1 , Fig. 3f ): This stage begins when main switch S turns on at ZVS. The operational principle of the proposed converter in this stage is almost the same as the operation principle in stage 5. The switch current iS increases from a negative to a positive value. In this operating mode, the key voltages and currents of the circuit are expressed as follows vCr t 0; vLm nvC 2 ; iLm t iLm t6 nvC2 t t6 ; Lm 13

Fig. 5 Photograph of prototype circuit

DiL1 vin =L1 ; Dt16

DiL2 vo = L 2 Dt16

This stage ends at t t1 when diode current iD 0, at which moment Stage 6 ends and the circuit goes to the operating stage 1. 4 Steady state analyses and design consideration Based on the key waveforms shown in Fig. 2, the delay time during the transition interval between main switch S and auxiliary switch Sa at stages 2, 4 and 5 is neglected in the system analysis. When main switch S is turned on and auxiliary switch Sa is turned off at stage 1, the input and output inductor voltages vL1 vin and vL2 vC1 =n vC2 vo . When main switch S is turned off and auxiliary switch Sa is turned on at stage 3, the input and output inductor voltages vL1 vin vC1 vCc and vL2 vo . In the steady-state analysis, the voltage-second product across the input inductor, when main switch and body diode are turned on, should equal the voltage-second product when both main switch and body diode are turned

Fig. 4

Design considerations Fig. 6 Measured results of the conventional Cuk converter at rated output power
a Gate voltage and drain voltage b Drain voltage and drain current
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a Relationship between clamp voltage and input voltage with different duty cycle b Relationship between the output voltage and input voltage under Dloss 0.05 and n 5 c Relationship between the voltage stress of diode and input voltage with different duty cycle
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Fig. 7 Experimental results of gate voltages and drain voltages for switching devices S and Sa for different output power
a b c d 170 W 120 W 60 W 12 W
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off Vin DTs VC 1 VCc Vin 1 DTs 14

expressed as VCc D V 1 D in D Dloss V n1 D Dloss in 18 19 20

where D is the duty cycle of main switch S and Vin , VC1 and VCc are average voltage value of input voltage and capacitors C1 and Cc . Based on the voltage-second balance on the output inductor L2 , the following equation, can be given: VC1 =n VC2 Vo D Dloss Ts Vo 1 D Dloss Ts 15

VC1 Vin VC2 Vo

where Dloss is the duty cycle loss of the converter at the Stage 6. The duty cycle loss depends on the load current. The duty cycle loss at heavy output load is larger than the duty cycle loss at light output load. For the voltage-second balance on the primary and secondary side of transformer, the following equations can be obtained VC1 DTs VCc 1 DTs VC 1 D Dloss Ts VC2 1 D Dloss Ts n 16 17

Fig. 4a gives the relationship between clamp capacitor voltage and input voltage with different duty cycle. When duty cycle is less than 0.5, the clamp voltage VCc , Vin . When duty cycle is greater than 0.5, the clamp voltage VCc . Vin . Fig. 4b gives the relationship between output voltage and input voltage with different duty cycle. When main switch S is turned on, the current ripple on the magnetising inductor is given as follows DiLm D Dloss Ts VC1 =Lm D Dloss Ts Vin =Lm 21 The ripple currents on the input and output inductors L1 and L2 are given as DiL1 DTs Vin =L1 DiL2 1 D Dloss Ts Vo =L2 22 23

Based on (14) (17), the clamp capacitor voltage VCc , capacitor voltages VC1 and VC2 and output voltage Vo are

Fig. 8
a b c d

Experimental results of gate voltages and drain currents for switching devices S and Sa for different output power

170 W 120 W 60 W 12 W
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Fig. 9 Experimental results under the rated output power

a b c d e f Gate voltage vS,gs , inductor current iL1 , drain current iS and capacitor current iC1 Gate voltage vS,gs , capacitor current iC1 , resonant current iLr and clamp capacitor current iCc Gate voltage vS,gs , resonant current iLr capacitor current iC2 and diode current iD Gate voltage vS,gs , capacitor current iC2 , diode current iD and inductor current iL2 Drain voltages vS,ds and vSa,ds , capacitor voltage vC1 and clamp capacitor voltage vCc Gate voltage vS,gs , clamp capacitor voltage vCc , and capacitor voltages vC1 and vC2

If the ripple currents on the input and output inductors are given, the input and output inductances are expressed as L1 DTs Vin =DiL1 ; L2 1 D Dloss Ts Vo =DiL2 24

as follows s   DiL1 2 IL1;rms IL1 1 =12; IL1 s   DiL2 2 =12 IL2;rms Io 1 Io

Based on power balance between the input and output side, the average input current can be obtained as IL1 Po =hVin , where h is the circuit efciency. The average output inductor current IL2 Io . The RMS currents on the input and output inductors are expressed
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25
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Fig. 10

Experimental output voltage and load current under the step load variation

a Between Po 60 W and Po 96 W b Between Po 96 W and Po 156 W

The maximum input and output inductor currents are given as     DiL1 DiL2 IL1;max IL1 1 ; IL2;max Io 1 26 2IL1 2Io The average diode current iD is expressed as ID;av Io The peak current of diode D is expressed as iD;max 2Po Vo 1 D Dmax 28 27

Experimental results

The voltage stress of the diode is given as VD;stress VC 1 =n VC 2 Vin =n1 D Dloss 29

Fig. 4c gives the relationship between the voltage stress of the diode D and duty cycle. The turn ratio between the transformer secondary side and primary side is equal to n Dmax Dloss Vin 1 Dmax Dloss Vo 30

where Dmax is the maximum duty cycle when input voltage Vin is minimum. The voltage stresses on main switch S and auxiliary switch Sa equal vin =1 Dmax . In Stage 4, the energy stored in the resonant inductance must be greater than the energy stored in the resonant capacitance, to ensure the ZVS operation for main switch S, i.e. Lr ! Cr vCc t4 vC1 2 =iLr t4 2 . p The resonant angular frequency in states 2 and 4 is 1= Lr Cr . The delay p time td at t2  t3 and t4  t5 can be equal to p Lr Cr =2. If the resonant capacitance Cr is given, the resonant inductance 2 Lr can be expressed as Lr 4td =Cr p2 . The clamp capacitor and resonant inductor are resonant about one half of the resonant period in stage 3. We can make the design such that one half of the resonant period approximately equals turn off time of the main switch p Tr p Lr Cc 1 Dmin;Vin T 2 31

The experimental results are provided in this Section to verify the effectiveness of the proposed converter. The proposed converter was implemented with the following parameters: vin 130 V  180 V, vo 12 V, Po,max 170 W, fs 70 kHz (switching frequency). The ETD-39 core with Bmax 2000 G and Ae 1.25 cm2 was used as an isolation transformer. The turn ratio between the transformer primary side winding turn np 34 and secondary side winding turn ns 4. The magnetising inductance of the transformer is designed as Lm 300 mH. The delay time between the gate signals of main switch S and auxiliary switch Sa is 300 ns. The resonant capacitor Cr 450pF. The selected resonant inductor Lr is about 30 mH. The input and output inductances are L1 1.5 mH and L2 75 mH. The selected clamp capacitance Cc 490 nF. The selected output lter capacitance Co is 2200 mF. The capacitances C1 C2 6.6 mF. The S60SC6M is used for diode D in the secondary side. The MOSFETs IRFP460 are used for main and auxiliary switches in the proposed converter. Fig. 5 shows a photograph of the prototype circuit. Fig. 6 shows the measured gate voltage and drain voltage of power switch S for a conventional hard switching Cuk converter. From Fig. 6a, the drain voltage is still at high voltage level when the gate voltage is changed from low voltage to high

where Dmin;Vin Dmax Vin;min =Vin;max , and therefore the clamp capacitance can be obtained as Cc
180

1 Dmin;Vin T 2 p2 Lr

32

Fig. 11 Measured circuit efciencies of the proposed converter and conventional Cuk converter
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Fig. 12 Measured results of the proposed converter at the rated output power when input AC source voltage vs 90 Vrms
a c d e and b Gate voltages and drain voltages for switching devices S and Sa Drain voltages and drain currents for switching devices S and Sa Gate voltage vS,gs , inductor current iL1 , drain current iS and negative capacitor current -iC1 Gate voltage vS,gs , negative capacitor current -iC1 , negative resonant current -iLr and clamp capacitor current iCc

voltage level. From Fig. 6b, the drain voltage and drain current are overlapped during the transition interval when switch S is turned on. Hance, the switching losses have occurred and the circuit efciency of the hard switching Cuk converter decreases. Fig. 7 gives measured waveforms of gate voltages and drain voltages of main switch S and auxiliary switch Sa for different output power. Before the gate voltages are positive, the drain voltages are zero. Hence, the ZVS conditions of both switches are achieved. Fig. 8 shows the experimental waveforms of gate voltages and drain
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currents for switches S and Sa for different loading conditions. It can be observed that the drain currents iS and iSa are negative before the gate voltages vS,gs and vSa,gs are positive. The intrinsic body diodes of switches S and Sa are conducting, therefore the active switches S and Sa can be turned on to achieve ZVS operation. The key waveforms of the proposed converter at the rated output power are given in Fig. 9. The experimental results of gate voltage vS,gs , inductor current iL1 , drain current iS and capacitor current iC1 are shown in Fig. 9a. Before main switch S is turned on, the switch
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current iS is negative to discharge capacitor Cr in order to achieve ZVS operation for main switch S. When main switch S is turned on, the drain current iS equals input inductor current iL1 and capacitor current iC1 . When main switch S is turned off, capacitor current iC 1 iL1 and switch current iS 0. Fig. 9b illustrates the measured results of the gate voltage vS,gs , capacitor current iC1 , resonant current iLr and clamp capacitor current iCc . When main switch S is turned on, the clamp capacitor current is zero and capacitor current iC1 equals the resonant inductor current iLr . When main switch S is turned off, the auxiliary switch Sa is turned on. In this interval, the resonant inductor current iLr equals the capacitor current iC1 and clamp capacitor current iCc . Fig. 9c gives the experimental waveforms of gate voltage vS,gs , resonant current iLr , capacitor current iC2 and diode current iD . The diode current iD equals zero when main switch S is turned on. The measured waveforms of gate voltage vS,gs , capacitor current iC2 , diode current iD and inductor current iL2 are shown in Fig. 9d. When switch S turns on, the diode current iD 0 and iL2 iC2 . If switch S turns off, the output inductor current iL2 iC2 iD . Fig. 9e illustrates the experimental results of drain voltages vS,ds and vSa,ds , capacitor voltage vC1 and clamp capacitor voltage vCc . The sum of drain voltages vS ;ds vSa;ds vC1 vCc . When switch S turns off and auxiliary switch Sa turns on, the clamp capacitor Cc is resonant with magnetising inductor and resonant inductor. Fig. 9f gives the experimental waveforms of gate voltage vS,gs , clamp capacitor voltage vCc and capacitor voltages vC1 and vC2 . The average voltage value of capacitor C2 equals the output voltage vo . Fig. 10a gives the experimental output voltage and output current under the step load variation between Po 60 W and Po 96 W. The measured output voltage and output current under the step load variation between Po 96 W and Po 156 W are shown in Fig. 10b. From the measured results in Fig. 10, the output voltage of the proposed converter is less sensitive to the load variations. To compare the circuit efciency of the proposed converter and the conventional Cuk converter, Fig. 11 shows the measured efciencies of the proposed converter and the hard switching Cuk converter. Based on Fig. 11, the proposed converter has better circuit efciency. The measured efciency of the proposed converter is about 88.5% at the rated output power (12V/14A). Fig. 12 shows the measured results of the proposed xconverter at the rated output power under the input AC source voltage vs 90 Vrms . The ZVS feature of both switches in the proposed converter is also achieved. 6 Conclusion

buck-boost stage are presented in this paper. In the proposed circuit, the leakage inductance of the transformer is also used as one part of the resonant inductance to achieve ZVS operation of main and auxiliary switches. The advantages of the proposed ZVS Cuk converter are low switching losses on power semiconductors, low voltage stress on primary switches, low output inductor current ripple, and smaller transformer required, due to two quadrant core swing. The mathematical equations of the proposed converter in each of the operation stages are analysed. The design consideration of the proposed converter is also included. Finally the experimental results based on a prototype circuit with rated 170W output are provided to verify ZVS operation of both main and auxiliary switches.

Acknowledgment

This work is supported by the National Science Council of Taiwan under Grant NSC 96-2221-E-224.

References

The operational principle, circuit design consideration and the implementation of a Cuk converter with active clamp

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