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Surface Mount
Micromachined Accelerometer MMA2202
The MMA series of silicon capacitive, micromachined accelerometers feature
signal conditioning, a 4-pole low pass filter and temperature compensation.
Zero-g offset full scale span and filter cut-off are factory set and require no
external devices. A full system self-test capability verifies system functionality.
MMA2202D: X AXIS SENSITIVITY
Features MICROMACHINED
• Integral Signal Conditioning ACCELEROMETER
±50g
• Linear Output
• Ratiometric Performance
• 4th Order Bessel Filter Preserves Pulse Shape Integrity
• Calibrated Self-test
• Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status
• Transducer Hermetically Sealed at Wafer Level for Superior Reliability
• Robust Design, High Shocks Survivability
Typical Applications
• Vibration Monitoring and Recording
• Appliance Control
• Mechanical Bearing Monitoring
• Computer Hard Drive Protection D SUFFIX
• Computer Mouse and Joysticks EG SUFFIX (PB-FREE)
16-LEAD SOIC
• Virtual Reality Input Devices
• Sport Diagnostic Devices and Systems
ORDERING INFORMATION
VDD
G-Cell Temp
Integrator Gain Filter Comp VOUT N/C 1 16 N/C
Sensor
N/C 2 15 N/C
N/C 3 14 N/C
ST 4 13 N/C
ST
Control Logic & Clock VOUT 5 12 N/C
Self-test Oscillator
EPROM Trim Circuits Generator STATUS 6 11 N/C
VSS
VSS 7 10 N/C
VDD 8 9 N/C
STATUS
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 µF capacitor to ground.
2. These limits define the range of operation for which the part will meet specification.
3. Within the supply range of 4.75 V and 5.25 V, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the
device may operate as a linear device but is not guaranteed to be in calibration.
4. The device can measure both + and – acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output
will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.
5. The device is calibrated at 20g.
6. At clock frequency ≅ 70 kHz.
7. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages.
8. Time for the output to reach 90% of its final value after a self-test is initiated.
9. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is
high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application.
10. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The
Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 µs, unless a fault condition continues to exist. For
a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 µF capacitor to ground.
11. Time for amplifiers to recover after an acceleration signal causes them to saturate.
12. Preserves phase margin (60°) to guarantee output amplifier stability.
13. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity.
Status
Freescale accelerometers include fault detection circuitry
and a fault latch. The Status pin is an output from the fault
latch, OR'd with self-test, and is set high whenever one (or
more) of the following events occur:
• Supply voltage falls below the Low Voltage Detect (LVD)
Figure 3. Transducer Figure 4. Equivalent voltage threshold
Physical Model Circuit Model • Clock oscillator falls below the clock monitor
minimum frequency
• Parity of the EPROM bits becomes odd in
number.
The fault latch can be reset by a falling edge on the self-
test input pin, unless one (or more) of the fault conditions
continues to exist.
STATUS P1
N/C 1 16 N/C
N/C 2 15 N/C ST P0
Accelerometer
Microcontroller
N/C 3 14 N/C VSS
ST 4 13 N/C VOUT A/D In
R
C 0.1 µF
VOUT 5 12 N/C 1 kΩ C 0.01 µF
VSS VDD
STATUS 6 11 N/C
C 0.1 µF
VSS 7 10 N/C VDD
VDD 8 9 N/C VRH
C 0.1 µF
9 thru 13 Trim pins Used for factory trim. Leave 4. Use an RC filter of 1 kΩ and 0.01 µF on the output of
unconnected. the accelerometer to minimize clock noise (from the
switched capacitor filter circuit).
14 thru 16 — No internal connection. Leave
unconnected. 5. PCB layout of power and ground should not couple
power supply noise.
6. Accelerometer and microcontroller should not be a
high current path.
MMA2202D 6 7. A/D sampling rate and any external power supply
VDD STATUS
Logic 4 ST R1 switching frequency should be selected such that they
Input 1 kΩ do not interfere with the internal accelerometer
8 VDD VOUT 5 Output sampling frequency. This will prevent aliasing errors.
Signal
C1
0.1 µF C2
0.01 µF
7 VSS
1 16
2 15
Acceleration of the package in the 3 14
Activation of Self Test moves the
+X direction (center plate moves in +x 4 13 –x center plate in the −X direction,
the −X direction) will result in an 5 12 resulting in an increase in the
increase in the output. 6 11 output.
7 10
8 9
Top View
8 7 6 5 4 3 2 1
Direction of Earth’s gravity field(1)
9 10 11 12 13 14 15 16
1. When positioned as shown, the Earth’s gravity will result in a positive 1g output.
Surface mount board layout is a critical portion of the total footprint, the packages will self-align when subjected to a
design. The footprint for the surface mount packages must be solder reflow process. It is always recommended to design
the correct size to ensure proper solder connection interface boards with a solder mask layer to avoid bridging and
between the board and the package. With the correct shorting between solder pads.
0.050 in.
0.380 in. 1.27 mm
9.65 mm
0.024 in.
0.610 mm
0.080 in.
2.03 mm
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CASE 475-01
ISSUE C
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CASE 475-01
ISSUE C
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