Positive Feedback Technique for DC-Gain Enhancement of Folded Cascode Op-Amps

Sina Farahmand
ECE Dept., Integrated Circuits and Systems Lab. K. N. Toosi University of Technology Tehran, Iran s.farahmand@ieee.org
AbstractIn this paper, a novel folded cascode operational amplifier is proposed which improves DC-gain using positive feedback technique. This method does not affect the unity-gain frequency, stability, power dissipation, and output voltage swing of the conventional folded cascode Op-Amp. The proposed OpAmp was designed in a standard 0.18m TSMC 1.8V CMOS technology. Simulation results show a DC-gain enhancement of 25dB and 513MHz unity gain bandwidth for the presented OpAmp. HSPICE simulation results confirm the theoretical estimated improvements.

Hossein Shamsi
ECE Dept., Microelectronic Research Lab. K. N. Toosi University of Technology Tehran, Iran shamsi@eetd.kntu.ac.ir

I. INTRODUCTION Operational amplifiers (Op-Amps) are one of the fundamental parts of many analog and mixed-signal systems. Op-Amps are typically used in the closed-loop configurations. DC-gain of Op-Amps has an important influence on the precision of the circuits. Besides, the increasing demand for high-resolution ADCs and DACs, voltage references, and sample-and-hold circuits has forced designers to propose novel high-speed and high-gain Op-Amps [1]. In new submicron technologies, designing high-gain circuits has become difficult due to low supply and overdrive voltages [2]. To design high-gain Op-Amps with large bandwidth in low-voltage processes, innovative circuit design techniques are required. There are several techniques described in the literature to enhance DC-gain of Op-Amps. One of the conventional approaches to increase DC-gain of folded cascode and telescopic Op-Amps is easily achieved by transistor cascading. Although this approach enhances amplifier output resistance, but leads to limit the output voltage swing [3]. In two-stage Op-Amps, higher DC-gain is achieved by cascading the gain stages. In this method, a proper compensation for stable operation is required. But this compensation will consequently limit the high frequency performance of Op-Amps [4]. Another method which is widely used to enhance DC-gain of Op-Amps is gain-boosting technique [5]. The gain-boosting amplifiers add their own pole and zero to the final Op-Amp and therefore, need a number of external bias voltages and consume more power. Using positive feedback technique is a well-known method

Figure 1. Circuit schematic of the conventional folded cascode Op-Amp

to boost the DC-gain of Op-Amps without limiting the high frequency performance [6]. The main problem of the most positive feedback implementation is a strong dependence of the amplifiers gain on transistors matching. Bulk driven methods can also be used for signal amplification in lowvoltage processes [7, 8]. The principal disadvantage of a bulk-driven MOS device in CMOS technologies is its effective transconductance (gmb), which is 4 or 5 times smaller than gate-transconductance (gm) [1]. Higher circuit noise-level is another drawback of circuits using bulk driven method [9]. In this paper, a new structure is proposed based on the conventional folded cascode Op-Amp shown in figure 1. The proposed Op-Amp uses positive feedback technique for increasing the DC-gain of the conventional Op-Amp without affecting the unity gain bandwidth (UGBW), stability, and power dissipation of the circuit. This paper is organized as follows: In section II, a brief analysis of the conventional folded cascode Op-Amp is explained. In section III, structure of the proposed Op-Amp is studied in detail. Circuit specifications, such as differential gain and frequency response are calculated in this section. Section IV is dedicated to simulation results. Device sizes of the proposed Op-Amp are given in this section. Finally section V concludes the paper.

978-1-4673-0859-5/12/$31.00 2012 IEEE 261

Figure 3. Small signal model of left side of the proposed Op-Amp

III. PROPOSED FOLDED CASCODE OP-AMP Differential Mode Gain Circuit schematic of the proposed Op-Amp is shown in figure 2. The CMFB and biasing circuit are not shown for simplicity. In the proposed circuit, the connection paths between transistors M12 and M13 to the transistors M14 and M15 are connected to the gate of cascode transistors M3 and M4. This is to provide a positive feedback loop inside the Op-Amp. Besides, the CMFB circuitry corrects the offset voltage at the output of the proposed Op-Amp. To calculate the differential mode gain, the small signal analysis of the proposed Op-Amp should be explained carefully. In Fig. 2, the voltages at nodes n1 and n2 are the scaled down version of Vout- and Vout+ by a factor of 1/(g m 7,8 ro7,8 ) . The voltages at nodes x1 and x2 shown in Fig. 2, represent the gate voltages of cascode transistors which are defined as:
V x 1,2 = g m12,13 g m14,15 1 V o+,- = kV o+,g m 7,8 rds 7,8 (6)

a.

Figure 2. Circuit schematic of the proposed folded cascode Op-Amp

II. CONVENTIOANL FOLDED CASCODE OP-AMP Figure 1 shows a schematic of the fully differential folded cascode Op-Amp. The folded cascode Op-Amp is a high performance Op-Amp which is widely used in many applications. The differential DC-gain of the Op-Amp is calculated as: V V o g m 1,2 R out Av 0 = o+ (1) V in+ V in where gm1,2 is the transconductance of input devices and Rout is the single ended output resistance obtained as:

Rout [ g m7,8 rds7,8 rds9,10 ] & [ g m3,4 rds3,4 (rds & rds1,2 )]
6 , 5

(2)

where gmx and rdsx are the transconductance and the output resistance of the Mx transistor, respectively. The voltage transfer function of the folded cascode OpAmp is determined as:
AV = AV 0 S S (1+ ) (1+ ) Pa Pb

Figure 3 shows left-side small signal model of the proposed Op-Amp. The voltage at node n3 is approximately calculated as equation (7) by applying KCL at node Vo- .
1- kg m 3 rds 3 + V n3 = rds 3 Ro 1

(3)

V o - = k 'V o 1+ g m 3 rds 3 where Ro1 is defined as equation (8).

(7)

where the poles Pa and Pb are defined as follows: 1 Pa = R out C out

R o1 = g m 7 rds 7 (rds 9 &

(4)

1 g m 12

(8)

Pb =

1 [rds1, 2 & rds 5, 6 & 1 g m 3, 4 ]C n 3, 4

(5)

in which Cout = CL + Cd(M3,4) + Cd(M7,8) and Cn3,4 denotes all parasitic capacitances of the nodes n3 and n4. The DC-gain of the conventional folded cascod Op-Amp, with minimum chosen length for all transistors in a standard 0.18m CMOS technology, is not enough for many specific applications such as pipeline ADC and sample-and-hold circuits. To increase the DC-gain of the conventional folded cascode Op-Amp, a new method based on positive feedback technique is proposed in section III.

It should be highlighted that transistor M12 is carefully designed to have an extremely low gm and consequently does not decrease Ro1. The differential mode gain of the proposed Op-Amp is defined using the equation (6) and also applying KCL at node n3, as is introduced in equation (9). According to the differential mode gain of the conventional folded cascode Op-Amp and the proposed one, it is clearly understood that a few expected changes are occurred which have significant effects on the positive feedback loop-gain and stability of the proposed Op-Amp.
Avd = V o+ V o = g m1 V in+ V in 1 k' 1 + (rds 1 & rds 5 ) Ro 1

(9)

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TABLE I. Transistor M, M M, M M, M M, M

TRANSISTOR SIZES USE ED IN BOTH PROPOSED AND CONVENTIONAL OP-AMP (W/L) 10 10m / 0.18m 4 3m / 0.18m 4 3m / 0.18m 10 10m / 0.18m Tran nsistor M, M M M , M M , M (W/L) 4 6m / 0.18m 7 10m / 0.18m 2.5m / 0.18m 0.6m/ 0.18m

Figure 4. DC-gain comparison between the propose ed and conventional Op-Amp

The transfer function of the back kward path is calculated in equation (13), where ( 1 - Af Ab ) = Kf and Pc denotes a pole as is described in equation (14).
A vb = Ab S (1 + ) Pc
1 1 g m 14,15 ] ] C x 1, 2

(13) (14)

Pc = [ro
,13

&

In the equation (14), Cx1,2 represents all parasitic capacitances of the nodes x1 and x2. In practice, due to the equations (5), (14) and since gm14,15<< gm3,4 , we have Pa << Pc << Pb . According to the positive p feedback concept and using the equations (12) and (13), the overall transfer o as: function of the proposed Op-Amp is obtained
osed and conventional Figure 5. Phase margin comparison between the propo Op-Amp

To simplify estimation of the proposed Op-Amps frequency response in the next subsection, it is a assumed that the differential mode gain of the proposed Op-Am mp is described as equation (10).
Avd = g m1 R out Kf

g m 1, 2 R out A vf A v= Kf 1 - A vf A vb

(10)

where Rout is the single ended output r resistance of the conventional folded cascode Op-Amp which h is calculated in the equation (2), and parameter Kf is determin ned as:
K f = Rout ( k' 1 + ) rds 1 & rds 5 Ro 1

It is clearly understood that a zer ro occurs at the frequency of the second dominant pole and a leads to pole-zero cancellation [10]. In other words, a pole produced by the positive feedback path is cancelled by a zero and therefore, the ffected. Hence, the total stability of the Op-Amp is not af transfer function is calculated as:
Av g m 1, 2 R out Kf (1 + 1 S K f Pa ) (1 + S ) Pb

2 1

S ) Pc S S S (1 + ) (1 + ) (1 + ) K f Pa Pc Pb (1 +

(15)

(16)

(11)

A desirable value for the positive feedback loop-gain can be nsistors M12, M13, achieved using appropriate sizes for the tran M14, and M15. Due to the equation (10), the Parameter Kf should be taken a value between zero and one to increase the DC-gain of the proposed Op-Amp. B. Frequency Response es and zeros, but The proposed Op-Amp has several pole two first dominant poles are important in estimation of the frequency response. In order to simplify the calculations, it is ard and backward assumed that the Op-Amp consists of forwa paths with individual transfer functions as follows. The mined as: transfer function of the forward path is determ
A vf = Af S S (1 + ) (1 + ) Pa Pb

It is clearly understood that the stability of the proposed Op-Amp is determined and changed by different values of the he previous subsection, the parameter Kf. As it is described in th parameter Kf should be taken a valu ue between zero and one. One of the important issues in des signing the proposed OpAmp is that, the parameter Kf shou uld not be adjusted very close to zero. Otherwise, it can be e negative due to process variations and leads Op-Amp to become unstable. Thus, the tiously simulated in the proposed Op-Amp should be caut corners of fabrication process. IV. SIMULATION RESULTS E The proposed Op-Amp is design ned in a standard 0.18m TSMC 1.8V level 49 CMOS proces ss. The size of transistors for both proposed and conventional folded cascode Op-Amps are chosen identically for fair comparison and listed in Table I. Frequency responses of the prop posed Op-Amp in three different process corners are shown in figure 4, 5 and also are onse of the conventional compared with the frequency respo folded cascode Op-Amp.

(12)

where Af = gm1,2 Rout . Moreover, the pole es Pa and Pb are determined same as the equations (4) and (5), respectively.

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TABLE II. Specification

SPECIFICATIONS OF THE CONVENTIONAL AND PROPOSED FOLDED CASCODE OP-AMP Conventional Op-Amp TT (27C) 0.18m 1.8V 513MHz 51dB 1.6V 75.5 2.2mw 506 V
sec

Proposed Op-Amp TT FF SS (27C) (-40C) (85C) 0.18m 1.8V 513MHz 76dB 1.6V 75 2.1mw 516
V sec

Technology Supply Voltage UGBW DC Gain Output Voltage Swing Phase Margin Power Dissipation Slew Rate CL

0.18m 1.8V 605MHz 69dB 1.5V 78 2.2mw 534

V sec

0.18m 1.8V 470MHz 83dB 1.55V 72 2.05mw 495

V sec

1pF

1pF

1pF

1pF

Figure 6. Flip-around sample-and-hold circuit with illustration of nonoverlapping clock signals

V. CONCLUSIONS In this paper, a new folded cascode Op-Amp is presented which uses positive feedback technique to enhance the DC-gain. The proposed circuit increases the DC-gain of the conventional Op-Amp about 25dB. Simulation results prove that the utilized technique does not affect the speed, output voltage swing, stability, and power dissipation of the conventional folded cascode Op-Amp. REFERENCES
B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, New York, USA, 2001. [2] B. l. Blalock, P. E. Allen, G. A. Rincon-Mora, Designing 1V OPAmps using standard digital CMOS technology, IEEE Trans. on Circuits and Syst. II, vo1.45, no.7, pp.769-780, July 1998. [3] K. Gulati, and H. Lee, A high-swing CMOS telescopic operational amplifier, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998. [4] K. Bult, and G. Geelen, A fast-settling CMOS Op-Amp for SC circuits with 90-dB DC gain, IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990. [5] S. Li, and Q. Yulin, Design of a fully differential gain-boosted foldedcascode Op Amp with settling performance optimization, in Proc. of IEEE Conference on Electron Devices and Solid-State Circuits, pp. 441-444, Dec. 2005. [6] H. Mirzaie, H. Khameh, and H. Shamsi, New two-stage Op-Amp using gate-driven, and positive feedback techniques, in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1140-1143, Dec. 2010. [7] H. Khameh, H. Mirzaie, and H. Shamsi, New two-stage Op-Amp using hybrid cascode compensation, bulk-driven, and positive feedback techniques, in Proc. Of 8th IEEE International NEWCAS Conference, pp. 109112, Jun. 2010. [8] A. Dadashi, Sh. Sadrafshari, Kh. Hadidi, and A. Khoei, An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35m CMOS process, Analog Integrated Circuits and Signal Processing, vol.67, no.2, pp. 213222, Oct. 2010. [9] R. S. Assaad, and J. Martinez, The recycling folded cascode: a general enhancement of the folded cascode amplifier IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, sep. 2009. [10] P. Grybos, M. Idzik, K. Swientek, and P. Maj, Integrated charge sensitive amplifier with pole-zero cancellation circuit for high rates, in Proc. of IEEE Internatioanl Symposium on Circuits and Systems (ISCAS), pp. 1991-2000, 2006. [1]

Figure 7. Step response comparison of proposed and conventional folded cascode Op-Amps

The proposed method increases the DC-gain of the Op-Amp about 25dB and does not change the UGBW. In Table II, specifications of the proposed Op-Amp in three process corners are summarized and compared with the conventional Op-Amp. The value of power dissipation and UGBW in Table II are given with CMFB circuitry. Compared to the Op-Amp presented in [8], the proposed Op-Amp has lower circuit complexity, lower power dissipation, and more DC-gain improvement in lower process with minimum chosen length for all transistors which leads to lower chip area. The proposed and conventional folded cascode Op-Amps are used in a switched-capacitor flip-around sample-and-hold circuit shown in Fig. 6 to compare the steady state error of them. Figure 7 illustrates the circuit level simulation result of a large signal transient response of the both Op-Amps to a 1V (p-p) input step voltage with two non-overlapping clocks at frequency of 25Mhz. As is clear, the proposed Op-Amp reaches 99.944% of input signal final value at the end of holding period, while the output voltage of the conventional folded cascode is 99.406% of input signal at the same time.

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