Ordering number : ENN7900B

Bi-CMOS IC

LV23002M
Overview

For Radio Cassette and Mini Component System 1-chip Tuner IC Incorporating PLL

The LV23002M is a one-chip tuner IC incorporating PLL for radio cassette and mini component system.

Features
AM FM-FE FM-IF MPX PLL

Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC max VDD max Maximum input voltage VIN1 max VIN2 max Maximum output voltage VO1 max VO2 max VO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VCC VDD CE, DI, CL XIN DO XOUT, PD BO1, BO2, AOUT Ta70C Mounted on a glass epoxy board. Board size : 114.3 mm76.1mm = 1.6mm Conditions Ratings 7.0 5.0 5.0 VDD+0.3 6.0 VDD+0.3 12.0 400 -20 to +70 -40 to +125 Unit V V V V V V V mW C C

Note : This product should be handled with care because the resistance of one pin against electrostatic discharge damage is low.

Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.

92706 / 72905 MS IM B8-8314,B8-6787 / 81004 JO IM No.7900-1/13

LV23002M
Operating Condition at Ta = 25C
Parameter Recommended supply voltage Symbol VCC VDD Operating supply voltage range VCC op VDD op Conditions Ratings 5.0 3.0 4.0 to 6.0 2.5 to 3.6 Unit V V V V

Note : Use the product with the supply voltage applied to VCC and VDD. PLL block Allowable Operating Range at Ta = -20 to +70C, VSS = 0V
Parameter Supply voltage Input high level voltage Input low level voltage Output voltage Symbol VDD VIH VIL VO1 VO2 Operating frequency fIN1 fIN2 fIN3 fIN4 CE, CL, DI CE, CL, DI DO BO1, BO2, AOUT XIN ; VIN1 FMIN ; VIN2 AMIN (SNS = 1) ; VIN3 AMIN (SNS = 0) ; VIN4 10 2 0.5 Conditions min 2.5 0.7VDD 0 0 0 75 160 40 10 Ratings typ max 3.6 5.0 0.3VDD 6.0 10 V V V V V kHz MHz MHz MHz Unit

Note : Due attention must be paid on leak because the XIN pin has an extremely high input impedance. Operating Characteristics at Ta = 25C, VCC = 5.0V, VDD = 3.0V, See the specified circuit.
Parameter Symbol Conditions min [FM-FE characteristics] : fc = 98MHz, fm = 1kHz, 22.5kHzdev. 3dB sensitivity Actual sensitivity 3dB LS QS 60dBV EMF, 30%mod output reference, -3dB input S/N = Input at S/N = 30dB 3 10 dBV EMF dBV EMF Ratings typ max Unit

[FM-IF monaural characteristics] : fc = 10.7MHz, fm = 1kHz, 75kHzdev. Demodulation output Channel balance Signal-to-noise ratio Total harmonic distortion (Monaural) 3dB sensitivity IF count sensitivity Mute attenuation 3dB LS IF-C3 Mute-Att VO reference, Input level at which VO reference is -3dB. SDC0 = 1, SDC1 = 0,18pin(DO) output 100dBV, 12pin output 47 VO CB S/N THD 100dBV, 12pin output 100dBV, 13pin output /12pin output 100dBV, 12pin output 100dBV, 12pin output 270 -1.5 68 330 0 75 0.3 38 52 68 1.5 44 58 400 +1.5 mVrms dB dB % dBV dBV dB

[FM-IF stereo characteristics] : fc = 10.7MHz, fm = 1kHz, L+R = 90%, Pilot = 10%, VIN = 100dBV Separation Total harmonic distortion (Main) SEP THD L-mod, 12pin output /13pin output Main-mod, 12pin output 28 40 0.5 1.5 dB %

Continued on next page.

No.7900-2/13

LV23002M
Continued from preceding page.
Parameter Symbol Conditions min [AM characteristics] : fc = 1000kHz, fm = 1kHz, 30%mod Detection output 1 Detection output 2 Signal-to-noise ratio 1 Signal-to-noise ratio 2 Total harmonic distortion IF count sensitivity Low-range attenuation [Current dissipation] Current dissipation ICCFM ICCAM IDD [PLL characteristics] Internal return resistance Built-in output resistance Hysteresis width Output high level voltage Output low level voltage Rf Rd VHIS VOH VOL1 VOL2 XIN XOUT CE, CL, DI PD ; IO = -1mA PD ; IO = 1mA BO1, BO2 ; IO = 1mA BO1, BO2 ; IO = 5mA VOL3 VOL4 Input high level current IIH1 IIH2 IIH3 Input low level current IIL1 IIL2 IIL3 Output off-leak current IOFF1 IOFF2 H level 3-state off-leak current L level 3-state off-leak current IOFFH IOFFL DO ; IO= 1mA AOUT ; IO = 1mA, AIN = 2.0V CE, CL, DI ; VI = 6.0V XIN ; VI = VDD AIN ; VI = 6.0V CE, CL, DI ; VI = 0V XIN ; VI = 0V AIN ; VI = 0V BO1, AOUT, BO2 ; VO = 10V DO ; VO = 6.0V PD ; VO = 6.0V PD ; VO = 0V 0.01 0.01 0.16 0.16 VDD-1.0 1.0 0.25 1.25 0.25 0.5 5.0 0.9 200 5.0 0.9 200 5.0 5.0 200 200 8 250 0.1VDD M k V V V V V V V A A nA A A nA A A nA nA No input in FM mode No input in AM mode fr = 83MHz, Xtal = 75kHz, No input to tuner 20 10 1 30 20 2 40 30 5 mA VO1 VO2 S/N1 S/N2 THD IF-C LOW-CUT 23dBV, 12pin output 80dBV, 12pin output 23dBV, 12pin output 80dBV, 12pin output 80dBV, 12pin output 18pin (DO) output VO2 reference, Pin 12 output at fm = 100Hz 22 5 25 80 15 47 40 110 20 54 1.2 28 8 3.0 33 11 80 145 mVrms mVrms dB dB % dBV dB Ratings typ max Unit

No.7900-3/13

DI

unit : mm 3263

(1) IN mode

(2) IN2 mode

DI

0 P1 P2 P3 P4 P5 P6 P7 P8 (1)P-CTR P9 P10 P11 P12 P13 P14 P15 SNS DVS (3)IF-CTR CTE DNC R0 (2)R-CTR R2 R3 R1 (13)Dont care

P0

(9)O-PORT

BO1

Package Dimensions

Address

Address

(4)IFSW

IFSW

(9)O-PORT

B02

0 0 0 1 0 1 0 0

1 0 0 1 0 1 0 0

(5)BDSW (14)STSW

BDSW1

STSW

(15)SDC0

SDC0

DOC0

(6)DO-C

DOC1

DOC2

UL0

(7)UNLOCK

UL1

(8)DZ-C

DZ0

DZ1

LV23002M

Composition of DI control data (serial data input)

(3)IF-CTR

GT0

GT1

(16)SDC1

SDC1

(10)PD-C

DLC

(11)IFS

IFS

TEST0

(12)TEST

TEST1

TEST2

No.7900-4/13

LV23002M
Description of DI control Data
No. (1) Control block data Programmable divider data P0 to P15 DVS, SNS DVS 1 0 0 SNS * 1 0 LSB P0 P0 P4 Set dividing number(N) 272 to 65535 272 to 65535 4 to 4095 Actual dividing number Twice the set value Set value Set value Description Data to set the dividing number of programmable divider Binary value with P15 assued to be MSB. LSB varies according to DVS and SNS. (*: dont care) Related data

* P0 to P3 invalid when LSB:P4 To select the signal input (FMIN, AMIN) to the programmable divider and to change the input frequency range. (*: dont care) DVS 1 0 0 (2) Reference divider data R0 to R3 SNS * 1 0 Input FMIN AMIN AMIN Operation frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz

Reference frequency (fref) selection data R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * PLL INHIBIT The programmable divider and IF counter stop, with FMIN, AMIN, and IFIN inputs being in the pull-down condition (GND), and the charge pump has the high impedance. R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 25kHz 25kHz 25kHz 25kHz 12.5kHz 6.25kHz 3.125kHz 3.125kHz 5kHz 5kHz 5kHz 1kHz 3kHz 15kHz PLL INHIBIT+Xtal OSC STOP PLL INHIBIT

(3)

IF counter control data CTE GT0, GT1

IF counter counting start data CTE = 1: Counting start = 0: Counting reset Determines the counting time of universal counter GT1 0 0 1 1 GT0 0 1 0 1 Counting time 4ms 8 16 32 Wait time 3 to 4ms 3 to 4 3 to 4 3 to 4 IFS

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No.7900-5/13

LV23002M
Continued from preceding page.
No. (4) Control block data MUTE control data IFSW (5) FM/AM BAND selection control data BDSW (6) DO pin control data DOC0 DOC1 DOC2 Data to control DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 Open Low when unlock is detected. end-UC (See the item with asterisk below) Open Open Low when SDON Low when stereo Open DO pin condition Data = 0: at receiving 1: MUTE Data to determine the output of output port BDSW, controlling selection of BAND. Data = 0: AM 1: FM Description Data to determine the output of output port IFSW, controlling the MUTE function. Related data

The open condition is selected at power ON/reset. * IF counter counting end check DO pin (2)Counting end (1)Counting start (1) With end-UC set and IF counter starting (CTE=01), DO pin opens automatically. (2) At end of counting of the IF counter, DO pin goes LOW and check on counting end can be made. (3) DO pin opens when serial data is entered/output (CE pin: Hi) Note: DO pin is always in the open condition during data input (IN1 and IN2 modes, during CE: Hi period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition during data output (OUT mode, CE-Hi period), the content of internal DO serial data is output in synchronization with CL, regardless of DO pin control data (DOC). (7) Unlock detection data UL0, UL1 Phase error (E) detection width selection data to judge if PLL is locked. Phase error exceeding the detection width is judged that PLL is locked (*:dont care) UL1 0 0 1 UL0 0 1 * E Detection width Stop 0 6.67 Detection output Open Direct output of E E extended by 1 to 2ms (3)CE: HI

UL0, UL1 CTE

DOC0 DOC1 DOC2

* DO pin is LOW. Serial data output: UL = 0. (8) Phase comparator control data DZ0, DZ1 Data to control the dead zone of phase comparator DZ1 0 0 1 1 (9) Output port data BO1, BO2 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD

Dead zone width: DZA<DZB<DZC<DZD Data to determine the output of output ports BO1 and BO2 Data = 0: OPEN 1: Low

Continued on next page.

No.7900-6/13

LV23002M
Continued from preceding page.
No. (10) Control block data Charge pump control data DLC DLC 0 1 Description Data to enforce control of charge pump output Charge pump output Normal Forced to LOW Related data

In case of dead lock because of VCO oscillation stop when the VCO control voltage (Vtune) is 0V, it is possible to clear dead lock by setting the charge pump output to LOW and V tune to VCC. (Dead lock clear circuit) (11) (12) IFS LSI test data TEST0 to 2 Normally, set Data = 1. Setting Data = 0 causes the input sensitivity worsening mode and the sensitivity decreases by about 10 to 30mVrms. LSI test data TEST0 TEST1 TEST2 All set to zero at power ON/reset (13) (14) DNC Forced monaural control data STSW (15) (16) SD sensitivity control data SDC0 SDC1 Data to determine the output of output ports SDC0 and SDC1, controlling the SD sensitivity Data = SDC0: 0, SDC1: 0 SD sensitivity = 42dBV (typ) SDC0: 0, SDC1: 1 SD sensitivity = 45dBV (typ) SDC0: 1, SDC1: 0 SD sensitivity = 51dBV (typ) SDC0: 1, SDC1: 1 SD sensitivity = 56dBV (typ) Set data = 0. Data to determine the output of output port STSW, controlling the forced stereo functions. Data = 0: MONO 1: STEREO All to be set to 0

DO control data (serial data output) composition (1) OUT mode Address
DI 0 1 0 1 0 1 0 0

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

UL

C9

C8

C7

C6

C5

C4

C3

C2

C1

(1)IN-PORT

Description of the DO output data

No. (1) Control block data Stereo and SD indicators control data STIND, SDIND (2) PLL unlock data UL (3) IF counter, binary counter C19 to C0 Data latching the content of unlock detection circuit UL 0: At unlock 1: At lock or detection stop mode Data latching the content of IF counter (20-bit binary counter) C19 MSB of binary counter C0 LSB of binary counter UL0 UL1 CTE GT0 GT1 Description Data latching stereo and SD indicator conditions. Latching made in the data output (OUT) mode. STINDStereo indicator condition SDINDSD indicator condition 0: ST ON, 1: ST OFF 0: SD ON, 1: SD OFF Related data

(3)IF-CTR

C0

DO

SDIND

STIND

No.7900-7/13

LV23002M
Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH 0.75s tLC < 0.75s (1) CL: Normally HI
tEL CE tES tEH

CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data

(2) CL: Normally LOW

tEL CE tES tEH

CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data

Serial data output (OUT) tSU, tHD, tEL, tES, tEH 0.75s (1) CL: Normally Hi
tEL CE

tDC, tDH < 0.35s

tES

tEH

CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0

No.7900-8/13

LV23002M
(2) CL: Normally low
tEL CE tES tEH

CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0

(Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up resistance and substrate capacity.

Serial data timing

VIH tCH CL VIH DI VIL DO tLC Internal data latch Old New tSU tHD VIL tDC tDC tDH VIH VIL VIH tCL VIL tEL VIH tES VIL VIH tEH

CE

VIL

<< When CL stops at the L level >>

CE tCH CL VIH VIL VIH DI VIL DO tSU tHD VIL VIH tCL VIH

VIH

VIL

VIL tEL tES

VIH tEH

tDC

tDH

tLC Internal data latch Old New

<< When CL stops at the H level >>

No.7900-9/13

LV23002M
Parameter Data setup time Data hold time Clock L level time Clock H level time CE wait time CE setup time CE hold time Data latch change time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE Differs depending on the pull-up resistance and substrate capacity Pin DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Conditions min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.35 typ max unit s s s s s s s s s

No.7900-10/13

+B

Block Diagram

FM VDD
AM Low-cut

B.P.F

36 33
LPF FM OSC AM OSC

35 32 31 30 29 28 27 26 25 24 23 22

34

21

20

19

GND2

VCC2

VDD

POWER ON RESET

FM RF SD FF VCO OSC BUFFER AGC FM S-METER PILOT DET FF FF PHASE COMP MUTE ST TRIG ST SW

PHASE DETECTOR CHARGE PUMP

REFERENCE DEVIDER

SW AL LOW PROGRAMMABLE DIVIDER COUNTER UNLOCK DETECTOR

LV23002M

AM RF

AM MIX

AM DET

FM DET

DATA SHIFTREGISTOR LATCH

FM MIX VCC1 AM IF IF BUFFER FM IF DECODER VSS

UNIVERSAL COUNTER CCB I/F

REG

GND1

1 4 5 6 7 8 9 10

11

12
L-OUT

13
R-OUT

14

15

16

17

18

VDD

AM ANT

-COM
450kHz 10.7MHz

VCC

No.7900-11/13

Vt=8V

0.047F

0.047F

100k

0.01F

1k

100k

100k

0.047F

10 SVC346 16pF 10pF 100k 10pF 4.7F 100pF 0.1F 100F + + SA-151 1000pF 390pF

1000pF 10k

10pF

Test Circuit Diagram

22pF

FM IN 51k 51k 12pF SA-181 4.7k + S7 S6

10k 0.33F

GFWB3

SA-149

0.01F

1k

5.1k

VDD =3.0V

CFV-206 100k S5 S4

1000pF

SVC201

SVC201

S10

S9

S8

36 32
FM OSC BO2 BO1 A-OUT A-IN PD AM OSC AM AGC LOWCUT DET OUT MPX IN

35

34

33

31 28 25 23

30

29

27

26

10k 10000pF

24

22

21
VDD

20
X-OUT

19
X-IN

FM RFIN

GND2

FM RFOUT

VCC2

LV23002M

AM RFIN VCC1 P-DET P-COMP

REG

FM MIX

GND1

AM MIX

AM IFIN

FM IFIN

FM DET

L-OUT R-OUT

VSS

CE

DI

CL

DO

1
S1

10

11

12

13
L-OUT 0.01F

14
R-OUT 0.01F

15

16

17

18
S2 S3 51k

0.047F

AM IN 1F

51

39mH

SFELA 10M 7FA00-B0

10F

0.047F

SFULA450K U2B-B0

1F

SA-164

4.7F

3.3k

-COM
+

0.047F

100F

CDALA10M7GE001-B0

300 FM IF IN 51 0.047F

No.7900-12/13

VCC=5.0V

LV23002M
Coil specifications (bottom view)
FM BPF : GFWB3 (Soshin) 76MHz to 108MHz FM RF : SA-149 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 4.5T: US band FM OSC : SA-151 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 3.5T: US band FM IF filter: SFELA10M7FA00-B0 (Murata) FM Ceramic-discriminator: CDALA10M7GE001-B0 (Murata) AM OSC: SA-181 (Sumida) AM MIX: SA-164 (Sumida)

S VC 3 2 GND 1

4 pin31

h-f e-c

37T 74T

S pin5 3 VCC 2 1

S 4 CF

0.06UEW fo=796kHz

e - d 122T f - h 9T d - c 62T
0.06UEW fo=450kHz, Qo 65 180pF internal

6 VCC S

Qo 80 L=140H

6 GND

AM IF filter: SFULA450KU2B-B0 (Murata) MW Bar-antenna: C8E-A0105 (Toko)

c-d e-f
S 1 VC S 2 3 4 GND Pin1 Pin2

67T 9T

fo = 796kHz Qu = 180min L = 260H

Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 2005. Specifications and information herein are subject to change without notice. PS No.7900-13/13