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IS J AA

International Journal of Systems , Algorithms & Applications

Design and Implementation Of Built In Self-Test Mechanism to Minimize the Test Cost & Test Repair Cycle
Nagaraj S Vannal, 2Mahalaxmi S Bhille, 3Shanmuk S Vannal 1 Assistant Professor, 2Lecturer, 3Assistant Professor, 1 Dept. of IT, 2Dept of IS, 3Dept. of ECE, 1,2 B V Bhoomaraddi college of Engg, Hubli, Karnataka, India 3 Tontadarya College of Engg., Gadag, Karnataka, India e-mail: nagaraj_vannal@bvb.edu1, mahalaxmi.bhille@bvb.edu2, shanmuk.vannal@yahoo.co.in3
Abstract - With the ever-increasing complexity and density of present day integrated circuits, the cost of testing has become a significant part of the overall product. Thereby, Built-In SelfTest (BIST) has been proposed as a powerful design for testability technique for addressing the highly complex testing. The test is performed at the nominal operation frequency without resorting to an external high speed tester that represents an expensive Automatic Test Equipment (ATE) and which additionally does not always have a timing accuracy comparable to the IC internal speed on the boards. This paper includes the implementation of the built in self-test mechanism to minimize the test cost and test repair cycles using boundary scan technique. Keywords: BIST; JTAG; LFSR; ATE; POST
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The selected register contents shift out onto TDO on the falling edge of TCK.. TDI (Test Data Input) - Test instructions shift into the device through this pin. TDO (Test Data Output) - This pin provides data from the boundary scan registers, i.e. test data shifts out on this pin. TMS-Test Mode Select - This input which also clocks through on the rising edge of TCK determines the state of the TAP controller. TRST (Test Reset)- This is an optional active low test reset pin. It permits asynchronous TAP controller initialization without affecting other device or system logic.

I. INTRODUCTION With the ever-increasing complexity and density of present day integrated circuits, the cost of testing has become a significant part of the overall product. Thereby, Built-In SelfTest (BIST) has been proposed as a powerful design for testability technique for addressing the highly complex testing. BIST design includes on-chip/board circuitry to provide test patterns and to analyze output responses. It can perform the test internal to the chip so that the need for complex external testing equipment is greatly reduced. Using BIST many of the traditional testing problems (low accessibility of internal nodes that increases the test complexity) can be overcome. Another interesting feature of BIST strategies is that it allows rapid testing of the circuit. The test is performed at the nominal operation frequency without resorting to an external high speed tester that represents an expensive Automatic Test Equipment (ATE) and which additionally does not always have a timing accuracy comparable to the IC internal speed on the boards. Engineers design BISTs to meet requirements such as: High Reliability. Lower Repair Cycle Times. or Constraints such as: Limited Technician Accessibility. Cost Of Testing During Manufacture. II. SYSTEM OVERVIEW TAP (Test Access Port) - The pins associated with the test access controller. TCK (Test Clock) - this pin is the clock signal used for ensuring the timing of the boundary scan system. The TDI shifts values into the appropriate register on the rising edge of TCK.

Figure 1. Implementation of Built in self-test mechanism into hardware design.

A) Existing Approaches: Automatic or Automated Test Equipment (ATE): Automatic or Automated Test Equipment (ATE) is any apparatus that performs tests on a device, known as the Device Under Test (DUT), using automation to quickly perform measurements and evaluate the test results. An ATE can be a simple computer controlled digital multimeter, or a complicated system containing dozens of complex test instruments (real or simulated electronic test equipment) capable of automatically testing and diagnosing faults in sophisticated electronic packaged parts or on Wafer testing, including System-OnChips and Integrated circuits.

Volume 3, Issue ICRASE13, May 2013, ISSN Online: 2277-2677

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Design and Implementation Of Built In Self-Test Mechanism to Minimize the Test Cost & Test Repair Cycle

IS J AA

International Journal of Systems , Algorithms & Applications

Power-On Self-Test (POST): Power-On Self-Test (POST) refers to routines which run immediately after many digital electronic devices are powered on. Perhaps the most widelyknown usage pertains to computing devices (personal computers, PDAs, networking devices such as routers, switches, intrusion detection systems and other monitoring devices). Other devices include kitchen appliances, avionics, medical equipment, laboratory test equipmentall embedded devices. The routines are part of a device's pre-boot sequence. Once POST completes successfully, bootstrap loader code is invoked. B) Comparative Study: Comparison of the proposed system with existing system i.e., BIST is compared with POST and ATE w.r.t expensiveness, test time consuming, fault coverage and field support is shown in the figure 2 below

Figure 4. A 3-bit maximal-length LFSR produces a repeating string of seven pseudorandom binary numbers: 7, 3, 1, 4, 2, 5, 6.

B) Signature Analysis: Figure 5 shows the LFSR of Figure 4 with an additional XOR gate used in the first stage of the shift register. If we apply a binary input sequence to IN, the shift register will perform data compaction (or compression ) on the input sequence. At the end of the input sequence the shift-register contents, Q0Q1Q2, will form a pattern that we call a signature. If the input sequence and the serial-input signature register (SISR) are long enough, it is unlikely (though possible) that two different input sequences will produce the same signature. If the input sequence comes from logic that we wish to test, a fault in the logic will cause the input sequence to change. This causes the signature to change from a known good value and we shall then know that the circuit under test is bad. This technique, called signature analysis, was developed by HewlettPackard to test equipment in the field in the late 1970s.

Figure 2. Comparison of POST, BIST, ATE(1 Represents Low, 2 Represents Medium, 3Represents High, 0 Represents Not Present).

III. METHODOLOGY Built-in Self-Test (BIST) is a set of structured-test techniques for combinational and sequential logic, memories, multipliers, and other embedded logic blocks. In each case the principle is to generate test vectors, apply them to the circuit under test (CUT) or device under test (DUT), and then check the response.

Figure 5. A 3-bit serial-input signature register (SISR) using an LFSR (linear feedback shift register). The LFSR is initialized to Q1Q2Q3 = '000' using the common RES (reset) signal. The signature, Q1Q2Q3, is formed from shift-and-add operations on the sequence of input bits (IN).

Figure 3. Built in self test architecture.

A) LFSR- Linear Feedback Shift Register: Figure 4 shows a linear feedback shift register (LFSR). The exclusive-OR gates and shift register act to produce a pseudorandom binary sequence (PRBS) at each of the flip-flop outputs. By correctly choosing the points at which we take the feedback from an n -bit shift register, we can produce a PRBS of length 2 n 1, a maximal-length sequence that includes all possible patterns (or vectors) of n bits, excluding the all-zeros pattern.
Volume 3, Issue ICRASE13, May 2013, ISSN Online: 2277-2677

C) BIST Example: We can combine the PRBS generator of Figure 4 together with the signature register of Figure 5 to form the simple BIST structure shown in Figure 6 (a). LFSR1 generates a maximal-length (2 3 1 = 7 cycles) PRBS. LFSR2 computes the signature ('011' for the good circuit) of the CUT. LFSR1 is initialized to '100' (Q0 = 1, Q1 = 0, Q2 = 0) and LFSR2 is initialized to '000'. The schematic in Figure 6 (a) shows the bit sequences in the circuit, both for a good circuit and for a bad circuit with a stuck-at-1 fault, F1. Figure 6 (b) shows how the bit sequences are calculated in the good circuit. The signature is formed as R0R1R2 seven clock edges (on the eighth clock cycle) after the active-low reset is taken high. Figure 7 shows the waveforms in the good and bad circuit. The bad circuit signature, '000', differs from the good circuit and the signature can either be compared with the known good signature on-chip or the signature may be shifted out and compared off-chip (both approaches are used in practice).

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Design and Implementation Of Built In Self-Test Mechanism to Minimize the Test Cost & Test Repair Cycle

IS J AA

International Journal of Systems , Algorithms & Applications

played in hexadecimal (Q0 and R0 are the MSBs). The signature hex 3 or '011' (R0 = 0, R1 = 1, R2 = 1) in R appears seven positive clock edges after the reset signal is taken high. This is one clock cycle after the generator completes its first sequence (hex pattern 4, 2, 5, 6, 7, 3, 1). (b) The response of the bad circuit with fault F1 and fault signature hex 0 (circled).

(a)

The major causes of board manufacturing defects are missing components, wrong components, mis-oriented components, broken track (opens), shorted tracks (track-to-track shorts), pin-to-solder opens, pin-to-pin solder shorts. To consider the shorts, we assume that the behaviour of any short is logical i.e. the short behaves as if it were an unwanted wired-AND gate (strong 0, weak 1) or wired-OR gate (strong 1, weak 0). This is a realistic assumption given that the circuits receiving the result of a short are themselves digital and therefore will digitize the analog outcome of the short circuit.

Q1 t+1

(b) Figure 6. BIST example (a) a simple BIST structure showing bit sequences for both good and bad circuits. (b) Bit sequence calculations for the good circuit. The signature appears on the eighth clock cycle (after seven positive clock edges) and is R0 = '0', R1 = '1', R2 = '1'; with R2 as the MSB this is '011' or hex 3. bits (IN).

(c) Figure 7. The waveforms of the BIST circuit of Figure 6 (a) The good-circuit response. The waveforms Q1 and Q2, as well as R1 and R2, are delayed by one clock cycle as they move through each stage of the shift registers. (b) The same good-circuit response with the register outputs Q0Q2 and R0R2 grouped and their values disVolume 3, Issue ICRASE13, May 2013, ISSN Online: 2277-2677

Q0 t+1
1 0 1 1 1 0 0 1

R0 t+1

R2 t+1

R1 t+1

Q2t+1
0 0 1 0 1 1 1 0

0 1 0 1 1 1 0 0

0 1 0 0 1 1 0 0

0 0 1 1 1 1 1 0

0 0 0 1 1 1 1 1

0 0 0 0 1 1 1 1

Figure 8. Different tests using boundary scan technique.

IV. CONCLUSION With the implementation of BIST, it enables to test the Processor through the self-generated test with exhaustive data values. This ensures the Processor is fault free by having very high fault coverage. With embedded BIST, expensive tester requirements and procedures, starting from logic level to field level, are minimized and this reduces the system test cost and hence overall production cost.

(a)

Figure 9. Why BIST is important.

BIST implementation ensures the fault free circuit thus making sure that the input data from the Front End Subsystem through the Processor to DUT (Device Under Test) are correct as well as the DUT outputs values are reliable.
(b)

ACKNOWLEDGEMENT I deeply express my sincere gratitude to my Colleagues, Mrs. Mahalaxmi Bhille, Lecturer Dept of IS, BVBCET, Hubli and Mr. Shanmuk Vannal, Asst.Professor, Dept of E&C, TCE Gadag for their able regular source of encouragement and assistance throughout this work. I also extend my cordial thanks to Prof. Nalini Iyer, professor & HOD, Dept of IT, BVBCET, Hubli for providing me an opportunity to carry out the work. I also would like to thank Mr. Manickavelu M, Senior Technical Manager and all team members for their support and guidance.

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Design and Implementation Of Built In Self-Test Mechanism to Minimize the Test Cost & Test Repair Cycle

IS J AA

International Journal of Systems , Algorithms & Applications

REFERENCES
[1] Application-Specific Integrated Circuits by Michael John Sebastian Smith Copyright 1997 by Addison Wesley Longman, Inc. [2] Boundary Scan Tutorial A tutorial prepared by Dr R G Ben Bennetts DFT Consultant and Director, ASSET InterTech Inc.

[3] Specific BIST Architectures presentation by Gert Jervan Embedded Systems Laboratory (ESLAB) Linkping University. [4] Essentials of electronic testing for digital, memory and Mixedsignal VLSI circuits by Michael L. Bushnell Rutgers University, Vishwani D. Agrawal, Bell Labs, Lucent Technologies.

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