Buck Converter - Lab 2 1.

0 Objectives: In this lab, the student will design, construct, test, and demonstrate a buck converter. This converter is interfaced to the PV panels and battery to operate the panels at their maximum power point (MPP). 2.0 Equipment: MSP430F261x Development Board and MSP-FET430OUIF JTAG Programmer Lab Computer Battery Charger and battery Power Converter Parts Kit (Appendix C) Perf Board and Standoffs Multimeter Oscilloscope with Current Probe Bench Power Supplies RLC Meter 3.0 Background: If one directly connects the PV panels to the battery, the current and voltage are determined by the batterys charging characteristics (state-of-charge, SOC). The resulting operating point may not be at the PV panels maximum power point. To address this problem, we can introduce a DC-DC converter that adjusts the voltage over the battery so the PV panels set point is at the MPP. This lab realizes the rst part of that effort, but having the student design and build a buck converter whose input is the PV panel and whose output is the battery we wish to charge. A buck converter is a direct DC-DC converter whose input is a voltage source and whose output is a current source. Figure 1 shows the common ground conguration for this converter when the ground terminals of both sources are tied together. In our system, the input is the PV panel, which behaves more like a current source than a voltage source. We therefore need to connect a capacitor over the PV panel in parallel to provide a voltagecurrent characteristic which is more like that of a voltage source. In a similar way the output load needs to be connected in parallel with an inductor to make it behave more like a current source. Figure 1 (left) shows the conceptual interconnections of the common ground buck converter. The right side of the gure draws the schematic for the buck converter topology you will be working with. In designing a buck converter, there are at a minimum two or three components that must be specied. The inputs to the design process are 1) the input voltage, Vin , the desired 1

iin

L1

iout

+ Vin -

Iout

+ Vin -

#1 C1

#2

C2

+ Vout -

Figure 1: Buck Converter Concept (left), Schematic diagram of a buck converter (right) nominal output voltage, Vout , and the power consumption, which xes the input/output currents. The designer selects the inductors L and capacitors C to limit the amount of ripple in various currents within the circuit. The inductor is chosen to limit the current ripple in the diode and capacitor C is chosen to limit the output voltage ripple. Both the inductor and the capacitor inuence the output characteristic of the buck converter. Since you are using a PV panel as an input, you will also need to select an input capacitor Cin to limit the ripple over the panels terminals. With the selection of these components, it then becomes possible to bound the maximum and rms currents and voltages that the components must carry. This is important, for the designer must select components whose current/voltage ratings are consistent with the conditions within the circuit. If the components ratings are too high, then the circuit costs more than necessary. If the component ratings are too low, the components may fail (spectacularly) under load. Component values cannot be chosen freely. There are standard values for inductors and capacitors. These standard values may not always meet your requirements and when this is the case, the designer may need to adjust their components to achieve the desired component values. In general, the capacitor components cannot be easily adjusted. Inductors, on the other hand are easily built and in this lab, the students will design and build a lter inductor for their buck converter. Appendix A describes a design procedure for the lter inductor used in this lab. Another issue in the construction of switching converters is electro-magnetic interference or EMI. Direct DC-DC converters are switched at high frequencies 80 200 kHz and this is high so that parasitic inductances in the circuit will begin to radiate EMI. This interference can be picked up by other loops within the circuit with the end result being that what the designer thought would be nice square waves will actually have a great deal of distortion. Reducing the impact of EMI in converter circuits is a matter of careful circuit layout. The basic principles involve the usual circuit construction principles of keeping wires short and at, reducing the area over which a pulsating current loops, avoiding the use of large looping interconnections. In some cases, we can also use bypass capacitors to conne pulsating currents to small loops within the circuit with very small cross-sectional area. Appendix B discusses some of the layout issues that are relevant to the construction of your buck converter.

4.0 Pre-Lab Tasks: Step 1: Determine the capacitor C1 , C2 , and inductor L1 for the converter schematic in Figure 1. This converter takes the PV panel as the input and the battery as the output source. Step 2: Sketch the current waveforms through each of the following power stage components, Input lter capacitor, C1 Output lter capacitor C2 Inductor L1 MOSFET drain current ii n diode current id Compute the maximum, minimum, rms values of each current waveform. Step 3: Design the inductor to realize the L1 inductor in your design. Specify the wire gauge, number of turns, and air gap length. Step 4: Select the components from your parts kit to be used for the MOSFET, diode, capacitors C1 and C2 . Compare the voltage and current ratings of these parts with the expected full power voltage and currents for your design. 5.0 Tasks: Step 1 - Inductor design and construction: The lab kit contains two ferrite cores. Datasheets for these cores are linked to the course website. Copper magnet wire of various gauges are available in the lab. Construct the inductor you designed in your prelab. Select the wire gauge, wind the required number of turns on the bobbin and assemble the core. Check the inductance value L on the RLC meter and iterate if necessary. Step 2 - Buck power stage construction: Mount the power MOSFET and Schottky diode on the heat-sinks from your lab kit. Use the insulators in your kit to insulate the MOSFET and diode cases from the heatsinks: a very thin layer of thermal paste (provided by TA) is needed on both sides of the insulator to ensure good thermal conduction. A drill will be provided for drilling holes in your kets perf board to mount standoffs. Construct the power stage as shown in Figure 2 on the perf board. use # 1 AWG wire to make the interconnections in the power stage. For the MOSFET and diode, leave loops of wire long enough to insert a clip-on AC current probe to measure iL , iT , iC and iD . Otherwise, keep the wiring short for connections having pulsating currents. use twisted pairs to make the signal and return connections between boards. Step 3 - Gate Driver Circuit Construction: Connect a logic output of your MSP430 through the gate driver IC as shown in Figure 3. The schematic of the TC4428 is found on the course webpage. Be sure to include a 1 F capacitor to bypass the power supply of the TC4428. Program the table duty cycle. Before connecting the gate driver output to the MOSFET, 3

iin

iT iC1 C1

iL
+

iout iC2 +

Vg 0 - 35 V

iD -

vD

C2

V -

Figure 2: Buck Converter Schematic - power stage only measure the voltage level at the output to make sure it is generating a square wave that is large enough to drive the MOSFET.
iin iT iC1 C1
10 k 1/4 W

iL
+

iout iC2 +

Vg 0 - 35 V

iD -

vD

C2

V -

+12 V supply

+ 1 uF 1 uF 1n4148 1n4148 12 V zener

MSP430

TC4428 gate driver`

Figure 3: Buck Converter with Gate Driver Step 4 - Buck Power Stage Testing: Connect a load resistor capable of consuming the power produced by the PV panel to the converters output. Connect the gate driver output to the MOSFET gate. Be sure to put in the 10k pull-down resistor shown in Figure 3. Program the MSP430 to produce a suitable duty cycle. Apply power to the gate driver IC and verify that the correct drive signal is present at the MOSFET. With all of the power supplies turned off, connect the power stage to the laboratory bench 0-35 VDC power supply (Vg ). Use a voltage probe to measure vD (t), and a current probe to measure the transistor current iT (t). Use multimeters to measure the load resistor voltage and current. Set the load resistor to its maximum value, set Vg to zero, then turn on all power supplies. Increase Vg to a few volts and verify that vD (t) and iT (t) waveforms are correct. Be sure not to exceed the 25 V rating of your output capacitor C2 . Slowly increase Vg to the rated full-power voltage of the PV panels. Adjust the duty cycle to 4

obtain an output of 13 V, and slowly decrease the load resistance until the output power is 100W. Record the DC voltage and current of the source Vg and the load, and calculate the efciency. Show your results to the TA and if they make sense you can continue to the next step. Step 5: Bench Testing of Buck Converter: Measure the following waveforms and record for your report. Diode voltage vD (t), Transistor current iT (t) Diode current, iD (t) Inductor current iL (t) Capacitor C1 current iC 1 (t) Capacitor C1 voltage vC 1 (t) label the waveform names and scales. Label important features. Mesaure the inductor current ripple iL and compare with the value you designed for in your prelab assignment. Measure the capacitor ripple voltage, vC 1 and note the waveform of vC 1 (t). A practical capacitor model includes an equivalent series resistance (ESR) in series with an ideal capacitor. In many capacitors, including the aluminum electrolytics used in this experiment, the ESR induces a major portion of the AC voltage ripple. Based on your measured capacitor voltage and current waveforms, estimate the value of the ESR. Also estimate the power 2 (ESR). This power loss limits the maximum AC current loss induced in the ESR, PC = Irms that can be handled by the capacitor. Be sure to include in your report, your estimate of the ESR, your estimate of the power loss and the data sheet rms current rating for this capacitor. Step 6: Load Test Adjust or change the load resistor, to obtain a converter output power of about 15 W, with the duty cycle adjusted as needed to obtain an output voltage of 13 V. Record the input and output voltages, the output current, and the duty cycle. Measure and record the waveforms of iT (t) and vD (t); label the waveform names, scales, and salient features. Was it necessary to signicantly change the duty cycle? Why or why not? Repeat for an output power of approximately 1 W.

Appendix A - Filter Inductor Design:

A number of factors must be considered in the design of a magnetic device. The peak ux density must not saturate the core. The peak AC ux density should be small enough so that core losses are low. The wire size should be small enough to t the required number of turns in the core window. Subject to this constraint, the wire cross-sectional area should be as large as possible, to minimize winding DC resistance and copper loss. An air gap is needed when the device stores signicant energy. A.1 Filter Inductor: A lter inductor used in a buck converter is shown in Figure ??. In this application, the value of the inductance, L, is chosen to limit the inductor current ripple peak magnitude i to a small fraction of the full-load inductor current DC component, I . The structure and magnetic circuit model for the inductor is shown in Figure 4. In this device an air gap is used to prevent saturation of the core by the peak current I + i.

a)
core reluctance R c i(t) + v(t) n turns air gap reluctance Rg

b)
Hc Rc

ni(t) +

(t)

Rg

Figure 4: Filter inductor: (a) structure, (b) magnetic circuit model The cores magnetic led strength, Hc (t), is related to the winding current i(t) according to Hc (t) = ni(t)
c

Rc Rc + Rg

where c is the magnetic path length of the core, n is the number of turns, Rc is the core reluctance, and Rg is the air gaps reluctance. Since Hc (t) is proportional to the current i(t), Hc (t) can be expressed as a large DC component Hc0 that is proportional to the DC current I and an AC ripple Hc that is proportional to the current ripple i. A sketch of B (t) versus Hc (t) for this application is found in Figure 5. This device operates with the minor B-H loop illustrated. The size of the minor loop and hence the core loss depends on the magnitude of the inductor current ripple i. The copper loss 6 Figure 5: Filter Inductor: minor B-H loop
minor B-H loop, filter inductor Bsat

Hc Hc0 B-H loop, large excitation

Hc

depends on the rms inductor current ripple, essentially equal to the DC component I . Typically, the core loss can be ignored and the design is driven by the copper loss. The maximum ux density is limited by saturation of the core. A.2 Filter Design Constraints: Let us consider the design of the lter inductor shown in Figure 4. We assume that the core and proximity losses are negligible, so the inductor losses are dominated by low frequency copper losses. The inductor, therefore can be modeled as a series connection with an inductor L and resistance R. The resistance R represents the resistance of the windings. We want to obtain a given inductance L and a given winding resistance. The inductor should not saturate when a given worst-case peak current Imax is applied. Note that the specication of R is equivalent to specication of the copper loss Pcu , since
2 Pcu = Irms R

The inductor winding resistance inuences both converter efciency and output voltage. Hence in design of a converter it is necessary to construct an inductor whose winding resistance is sufciently small.
core

It is assume that the inductor geometry is topologically equivalent to that in Figure 4. An equivalent magnetic circuit is shown in this gure also. The core reluctance Rc and the air gap reluctance Rg are Rc =
c

wire bare area AW core window area WA

c Ac

Rg =

0 Ac

Figure 6: The winding must t in the core window area

where c is the core magnetic path length, Ac is the core cross sectional area, c is the core permeability, and g is the air gap length. It is assume that the core and air gap have the same cross-sectional areas. Application of a magnetic type of KVL relation yields, ni = (Rc + Rg ) Usually Rc Rg , and so we can approximate the above equation as ni Rg (1)

so that the air gap dominates the inductor properties. From these considerations we identify four design constraints. 1. Maximum ux density: Given a peak winding current Imax , we want to operator the core ux density at a peak value Bmax . The value of Bmax is chosen to be less than the 7

worst-case saturatuation ux density of the core material. Substitution of = BAc into equation (1) yields, ni = BAc Rg We then let I = Imax and B = Bmax to obtain nImax = Bmax Ac Rg = Bmax
g

(2)

0
g

(3) are

This is the rst design constraint where the turns ratio n and the air gap length the unknowns. 2. Inductance: The given inductance of the device is L= n2 0 Ac n 2 = Rg g

(4)

This is the second design constraint where the turns ratio n, the core area Ac , and gap length g are unknown. 3. Winding Area: As shown in Figure 6, the winding must t through the window (i.e., the hole in the center of the core. The cross-sectional area of the conductor, or base area, is AW . If the winding has n turns, then the area of copper conductor in the window is nAW . If the core has a window area WA , then we can express the area available for the winding conductors as WA Ku where Ju is the window utilization factor or ll factor. Hence the third design constraint can be expressed as WA Ku nAW (5)

The ll factor 0 < Ku < 1 is the fraction of the core window area that is lled with copper. Round wire does not pack perfectly; this reduces Ku by a factor of 0.7 to 0.55 depending on the winding technique. The wire has insulation; the ratio of wire conductor area to total wire area varies from 0.95 to 0.65. The bobbin uses some of the window area. Typical values for Ku for cores with winding bobbins are 0.5 for a simple low-voltage inductor, 0.25 0.3 for an off-line transformer, 0.05 0.2 for a high-voltage transformer at the kV level and 0.65 for a low-voltage foil transformer or inductor. 4. Winding Resistance: The resistance of the winding is R=
W

AW

(6)

where is the resistivity of the conductor material, W is the length of wire, and AW is the wire base area. The resistivity of copper at room temperature is 1.724 106 -cm. The length of the wire comprising an n-turn winding can be expressed as
W

= n(MLT) 8

(7)

where (MLT) is the mean-length-per-turn of the winding. This is a function of the core geometry. The fourth constraint on the resistance R is therefore, R= n(MLT) AW (8)

5. Core Geometrical Constant Kg : The four constraints in equations (3), (4), (5), and (8) involve the quantities Ac , WA , and MLT which are functions of the core geometry. The quantities Imax , Bmax , 0 , L, Ku , R, and are given specications and known ahead of time. The variables n g , and AW are unknowns that need to be solved for. Eliminations of the unknowns n g , and AW leads to the following equation A2 L2 I 2 c WA 2 max (MLT) Bmax RKu (9)

The quantities on the right side of equation (9) are specications or other known quantities. The left side of the equation is a function of the core geometry alone. A core must be chosen whose geometry satises equation (9). The quantity Kg = A2 c WA (MLT) (10)

is called the core geometrical constraint. It is a gure-of-merit that describes the effective electrical size of magnetic cores. 3.0 Filter Inductor Design Procedure: Equation (9) shows how specications impact core size. Increasing the inductance or peak current requires an increase in core size. Increasing the peak ux density allows a decrease in core size and hence it is advantageous to use a core material which exhibits a high saturation ux density. Allowing a larger winding resistance, R and hence larger copper loss, leads to a smaller core. Of course, the increase copper loss and smaller core size will lead to a higher temperature rise, which may be unacceptable. Equation (10) shows how core geometry affects core capabilities. An inductor capable of meeting increased electrical requirements can be obtained by either increasing the core area Ac or the window area, WA . Increase of the core area requires additional iron ore material. Increase of the window area implies that additional copper winding material is used. We may trade off iron for copper by changing the core geometry in a way that maintains the Kg in equation (10). The design procedure outlined above can now be summarized as a more systematic design procedure. This lter design procedure should only be regarded as a rst-pass approach. One usually has to iterate about this design to achieve the specied performance. The following quantities are specied using the units noted: The following procedure is used to design the lter inductor 9

Table 1: Filter Inductor Variables name symbol units Wire resistivity (-cm) Peak winding current Imax (A) Inductance L (H) R ( ) Winding resistance Winding ll factor Ku Core maximum ux density Bmax (T) core cross-sectional area Ac (cm2 ) WA (cm2 ) core window area mean length per turn MLT (cm) 1. Determine core size: Kg
2 L2 Imax 108 2 RK Bmax u

(cm5 )

(11)

Choose a core which is large enough to satisfy this inequality. 2. Determine air gap length:
g

2 0 LImax 104 2 A Bmax c

(m)

(12)

with Ac expressed in cm2 and 0 = 4 107 H/m. The air gap length is given in meters. The value is approximate since it neglects certain non ideal effects. Core manufacturers sell gapped cores. Rather than specifying the air gap length, the equivalent quantity AL is used. AL equal the inductance, in mH, obtained with a winding of 1000 turns. When AL is specied, it is the designers responsibility to obtain the correct gap length. Equation (12) can be modied to yield the required AL as follows, AL =
2 A2 10Bmax c 2 LImax

(mH per 1000 turns)

(13)

where Ac is given in cm2 , L is in Henries, and Bmax is in Tesla. 3. Determine the number of turns: This is given by the equation n= LImax 104 Bmax Ac (14)

4. Evaluate wire size: The bare wire area, AW , must satisfy AW Ku WA n (15)

10

Select wire with bare copper area less than are equal this value. You will need to use an AWG (American Wire Gauge) table to do this. As a check, the winding resistance can be computed as R= n(MLT) AW (16)

11

Appendix B - Buck Converter Layout Issues:

Building the converter circuit requires some care about the layout. Figure 7 shows one of the issues we nd in such circuits. This gure shows the two major loop currents within the converter. One of these current loops, i2 (t), is relatively constant in value. The other loop current, however, i1 (t), pulsates at a frequency determined by the converters switching frequency. To keep the current constant in the second loop, we have two switch fast, 80 kHz, which is fast enough to cause problems if the circuit is not laid out with some care.
iin L iout Rload

+ Vin -

#1

i1(t)

#2

i2(t) C

+ Vout -

i1(t)

Iload 0

i2(t)

Iload

Figure 7: Pulsating Currents in Buck Converter If we layout the circuit as shown in the original schematic, the pulsating current goes around a large loop and the parasitic inductances in the wire will cause a great deal of trouble. This will be seen in the non-ideal nature of the switching signals at the gate of the MOSFET as the pulsating currents will couple into the gate driver signals. What one often does is reduce the area over which the pulsating current moves by adding a bypass capacitor as shown in Figure 8. The capacitor shunts the pulsating AC current to a smaller loop that just includes the diode and the MOSFET. Moreover, by arranging the wires in this loop so they are close and move opposite directions, one is able to reduce the impact of the parasitic inductances in the network.
iin L iout Rload C

i1(t)
iin L iout Rload

+ Vout -

+ Vin -

i1(t)

pulsating current around large loop interacts with parasitic inductances in a way that can severely distort the square wave signals driving the MOSFETs gate

reduce area of loop with bypass capacitor and rearrangement of return wiring

Figure 8: Reducing EMI effects in the buck converter 12

Another issue one sees in these converters is a loss in power efciency due to power consumption in the gate driver circuit. The gate driver does not switch on instantaneously and during this turn-on interval, the current leaving the gate driver can be very large. This current ow has an impact on overall converter efciency, but also due to its high frequency content, it will again interact with parasitic inductances to generate additional EMI. We again use a bypass capacitor as shown in Figure 9 to limit the area over which this pulsating current ows.
converter power stage +15 Supply ucon power MOSFET + + +15 Supply ucon power MOSFET converter power stage

+ -

+ -

gate driver

gate driver

Figure 9: Reducing interference from the gate driver The students should think about how to improve their original design. To optimize the layout, they may need to reconnect components with shorter length of wires.

13

Appendix C - Power Converter Parts Kit:

Integrated Circuit TC4428A MSP430F2617 Power Semiconductor HUF75321 MBR1645 Small Discretes 1N4148 1N5242B Capacitors 330 F 3300 F 2200 F 22 F 10 F 1 F 0.1 F 0.47 F Resistor 10 k 1 4 22 Transformer and Magnetics 78604/9c PQ 32/20 PQ 26/25

Gate Driver IC; Microcontroller;

Power MOSFET, 55V 35A; Schottky Diode, 45V 16A;

Signal Diode, 100V 0.3A 4ns; 12V Zener Diode;

25V Electrolytic Capacitor; 35V Electrolytic Capacitor; 63V Electrolytic Capacitor; 200V Electrolytic Capacitor; 25V Multilayer Ceramic Capacitor; 25V Multilayer Ceramic Capacitor; 50V Multilayer Ceramic Capacitor; 100V Multilayer Ceramic Capacitor;

Resistor; 30 W Power Resistor; 30 W Power Resistor; Variable Power Resistor;

1 4W

2:1 Micro Transformer; Ferrite Core; Ferrite Core.

14

Appendix D - Selecting Parameter for Buck Converter:

iin

L1

iout

+ Vin -

#1 C1

#2

C2

+ Vout -

Figure 10: Circuit Diagram of Buck Converter This appendix shows an example of choosing inductor and capacitor parameters for the buck converter. As shown in Figure 10, the circuit demonstrates the structure of the converter, as well as component parameters that need to be determined. Consider the input voltage Vin = 15V 25V and the output voltage being xed as Vo ut = 12V . The maximum output power level of the circuit should be 100W , which corresponds to a charging current of 8.33A. The switching frequency is 80kHz with a period of 12.5s. The derivation is as following: First set the output capacitor to be C = 0. When the input voltage is 25V , the duty ratio V of the MOSFET is D1 = 12 25V = 48% and the corresponding conduction ratio of diode is 1 D2 = 1 D1 = 52%. Assuming the inductor current is within 1%, which is iL = 6 A. When the power MOSFET is off, the voltage over the inductor is VL = 13V and the interval is t = D2 T = 6.5s. Then there is: |VL | L di i L . dt t

Then the inductor must satisfy: 1 13 6.5 106 , L 6 L 507H.

The inductor should be at least 507H to meet the requirement when C2 = 0. This is also too large to be constructed in our lab, so that we may have C = 0 to have a smaller inductor. Now choosing the inductor to be L = 50H , the capacitor can be determined as following:

15

The inductor current varies by i = 13 D2 T , L 13 6.5 106 = , 50H = 1.69A.

The inductor can be treated as a triangular equivalent source, while the output is a xed source. Since the capacitor is parallelled to the inductor, while iC is positive, the voltage vC increases by an amount of V = 1 iC dt, C VC 0 12V 2%.

As a result, the capacitor should satisfy C 6.25 106 1.69/2 = 22F. 0.24V

The introduction of output capacitor reduces the required inductor value, but still satises the ripple requirement.
V In another case, the input voltage is 15V , then the duty ratio of the MOSFET is D1 = 12 15V = 80% and D2 = 1 D1 = 20%. Still assuming the inductor current is within 1%, which is iL = 1 6 A. When the power MOSFET is off, the voltage over the inductor is VL = 3V and the interval is t = D2 T = 2.5s. Then there is:

|VL | L

di i L . dt t

Then the inductor must satisfy: 3 2.5 106 1 , L 6 L 45H.

Since the inductor value is much smaller than the selected value above, the previous parameter selection can be kept for this case. As a result, considering the standard values of capacitors, the combination of fswitch = 80kHz , L = 50H , C = 47F , and 48% D1 80% meets all the requirements. 16