398 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

1, JANUARY 2013
A DCDC Converter Based on the Three-State
Switching Cell for High Current and Voltage
Step-Down Applications
Juan Paulo Robles Balestero, Fernando Lessa Tofoli, Grover Victor Torrico-Bascop e, Member, IEEE,
and Falcondes Jos e Mendes de Seixas
AbstractThis paper presents a pulsewidth modulation dcdc
nonisolated buck converter using the three-state switching cell,
constituted by two active switches, two diodes, and two coupled
inductors. Only part of the load power is processed by the active
switches, reducing the peak current through the switches to half
of the load current, as higher power levels can then be achieved
by the proposed topology. The volume of reactive elements, i.e., in-
ductors and capacitors, is also decreased since the ripple frequency
of the output voltage is twice the switching frequency. Due to the
intrinsic characteristics of the topology, total losses are distributed
among all semiconductors. Another advantage of this converter is
the reduced region for discontinuous conduction mode when com-
pared to the conventional buck converter or, in other words, the
operation range in continuous conduction mode is increased, as
demonstrated by the static gain plot. The theoretical approach is
detailed through qualitative and quantitative analyses by the ap-
plication of the three-state switching cell to the buck converter
operating in nonoverlapping mode (D < 0.5). Besides, the math-
ematical analysis and development of an experimental prototype
rated at 1 kW are carried out. The main experimental results are
presented and adequately discussed to clearly identify its claimed
advantages.
Index TermsBuck converter, dcdc converters, three-state
switching cell (3SSC).
I. INTRODUCTION
P
ULSEWIDTH modulation (PWM) dcdc converters are
widely employed in numerous applications, e.g., audio am-
pliers [1], uninterruptible power supplies [2], fuel cell powered
systems [3], and fork lift vehicles [4], although many other ones
Manuscript received February 14, 2012; revised March 29, 2012; accepted
April 24, 2012. Date of current version September 11, 2012. This work was sup-
ported by the National Council for Scientic and Technological Development,
Coordenac ao de Aperfeicoamento de Pessoal de Nvel Superior, Fundac ao de
Amparo ` a Pesquisa do estado de Minas Gerais, and the Fundac ao de Amparo ` a
Pesquisa do Estado de S ao Paulo. Recommended for publication by Associate
Editor K. Ngo.
J. P. R. Balestero is with the Federal Institute of Education, Science
and Technology of Santa Catarina, Santa Catarina 89813-000, Brazil (e-mail:
juan@ifsc.edu.br).
F. L. Tofoli is with the Department of Electrical Engineering, Federal
University of S ao Jo ao del-Rei, S ao Jo ao del-Rei 36307-352, Brazil (e-mail:
fernandolessa@yahoo.com.br).
G. V. Torrico-Bascop e is with the Eltek Energy AB, Stockhom 191 24,
Sweden (e-mail: grover.torrico@eltekvalere.com).
F. J. M. de Seixas is with the Department of Electrical Engineering,
University Estadual Paulista, S ao Paulo 18618-970, Brazil (e-mail: falcon@
dee.feis.unesp.br).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2012.2197419
can be easily found. Conventional hard switching converters
with a single active switch such as buck, boost, buckboost, C uk,
single-ended primary-inductance converter (SEPIC), and Zeta
typically present low power density, while attempts to further
minimize the size of lter elements lead to increased switching
losses, compromising the efciency of the converters.
In order to overcome such limitation, several soft switching
approaches have been introduced in the literature. Soft switching
is supposed to reduce the overlap between voltage and current
during the commutation, and can be classied in either active
or passive methods, as one must choose between the aforemen-
tioned snubbers for a given application.
Active methods can reduce the switching losses by using aux-
iliary switches. Unfortunately, an auxiliary switch increases the
complexity of both power and control circuits. Synchroniza-
tion problems between control signals of the switches during
transient also complicate the control strategy. Circuit cost is in-
creased and reliability is affected by using active snubbers [5].
A passive lossless snubber can effectively restrict switching
losses and electromagnetic interference (EMI) noise using no
active components and no power dissipative components. No ad-
ditional control is needed and no circulating energy is generated.
Circuit structure is as simple as RCD (resistorcapacitordiode)
snubbers while circuit efciency is as high as active snubbers
and resonant converters [6], [7]. Low cost, high performance,
and high reliability are the distinct advantages of a passive loss-
less snubber [8]. However, soft switching may not be achieved
for the entire load range, and besides the accurate design of the
resonant tank is not a trivial task, even what is also valid when
active snubbers are considered [9].
Signicant effort has then been made to improve the charac-
teristics of the traditional nonisolated dcdc converters in the
last few years. For instance, the study of a dcdc buck con-
verter with three-level buck clamping, zero voltage switching
(ZVS), active clamping, and constant-frequency PWM is pro-
posed in [10]. A family of converters is also derived, which
combines the advantages of reduced voltage across the switches
using a three-level commutation cell, and decreased switching
losses obtained from a soft switching technique.
As the power rating increases, it is often required to asso-
ciate converters in series or in parallel. By using interleaving
techniques in high current applications, the currents through the
switches become just fractions of the input current [11]. Inter-
leaving effectively doubles the switching frequency and also
partially cancels the input and output ripples, as the size of
0885-8993/$31.00 2012 IEEE
BALESTERO et al.: DCDC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 399
the energy storage inductors and differential-mode EMI lter in
resulting implementations can be reduced [12].
In the last few years, many converters based on the three-
state switching cell (3SSC) have been proposed. The cell can be
obtained by the association of two two-state PWM cells (2SSC)
interconnected to a center tap autotransformer, fromwhich novel
converters can be derived. General advantages over conventional
topologies can be achieved, e.g., the inductor is designed for
twice the switching frequency, with consequent reduction of size
and weight; the current through the switches is half of the input
current; part of the input power is delivered to the load by the
transformer instead of the main switches, consequently reducing
conduction and commutation losses; lower cost switches can be
used.
Many dcdc converters based on the 3SSC have been intro-
duced in the last few years [13][18]. However, the aforemen-
tioned works are basically concerned with high voltage gain
boost-based topologies dedicated to dc voltage step-up appli-
cations. Literature does not present further detailed studies re-
garding the remaining dcdc nonisolated topologies using the
3SSC.
Within this context, this paper proposes the complete study
of the dcdc converter based on the 3SSC. Initially, some the-
oretical background on the 2SSC and the 3SSC is presented,
leading to the conception of the improved buck converter us-
ing the so-called cell type B. Then, the converter operation
in nonoverlapping mode (NOM) is described, where the main
characteristics of the topology are discussed. An experimental
prototype is then implemented, while the detailed discussion
of experimental results is supposed to validate the theoretical
assumptions and also demonstrate the merit of the proposal.
II. CONCEPTION OF THE 3SSC AND THE PROPOSED
BUCK CONVERTER
The canonical switching cell is an approach that allows us to
obtain and classify the classical dcdc converters, from which
some families of converters can be derived [19]. Buck, boost,
and buckboost converters, which are second-order systems, as
well as C uk, SEPIC, and Zeta, which are fourth-other systems,
have a single switching cell that is part of their respective power
stages. Literature has also shown appreciable effort to improve
the characteristics of the original structures, even though the
novel resulting topologies are more complex approaches with
higher component count.
The aforementioned switching cell is composed of three ter-
minals, which are active, passive, and common. Its behavior is
based on the complementary operation of two switches con-
nected by the common terminal. In other words, one switch is
turned ON while the remaining one remains turned OFF, and
vice versa. Therefore, this arrangement can be called 2SSC.
With the aim of achieving higher power density, switching
frequency is usually increased, with consequent reduction of
size and volume of reactive elements. Consequently, it leads to
the increase of both switching losses and the volume of heat
sinks. This practice, therefore, compromises the very reduction
of physical dimensions in static power converters.
The aforementioned losses must then be reduced, and soft
switching circuits using the resonance phenomenon have been
widely proposed as a possible solution. By using well-known
techniques such as ZVS and zero current switching, the perfor-
mance of converters can be improved. However, even though
switching losses are mitigated or eliminated, conduction losses
are still of major concern and may even increase depending on
the adopted snubber.
With the aim to further reduce voltage and/or current stress,
the association of semiconductors or even converters in series or
in parallel has been thoroughly investigated. Other topologies
can also be obtained, such as multilevel converters [20].
It is also possible to increase the efciency by the use of
the 3SSC, which has been employed in recent publications [21]
and is originally derived from the dcdc pushpull converter. In
order to obtain the cell type B, let us consider the classical push
pull topology shown in Fig. 1, which is formed by switches S
1
and S
2
, two rectier diodes D
1
and D
2
in the secondary side,
and a high-frequency transformer. The circuit corresponds to a
dcacdc conversion system. If the central tap transformer is
considered ideal with unity turns ratio, the primary and sec-
ondary windings can be replaced by the respective magnetizing
inductances, which are coupled and constitute an autotrans-
former. The negative terminal of the output stage represented
by V
o
, which was formerly connected to the central tap of the
transformer, is then connected to the negative pole of the input
voltage source to generate a boost topology, as seen in Fig. 1(c).
Otherwise, if connected to the positive pole, a buckboost con-
verter is derived. The cell type B can then be applied to the
dcdc buck converter substituting the 2SSC, while the resulting
topology is presented in Fig. 2.
It can be seen that the 3SSC is formed by two controlled
switches S
1
and S
2
, two diodes D
1
and D
2
, one autotransformer
T
1
T
2
, and one inductor L. Even though the resulting cell seems
more complex with higher component count than the conven-
tional 2SSC, the advantages over its counterpart will be clearly
demonstrated in this study. For instance, the use of the 3SSC
may lead to the need of switches with reduced current rating,
which is desirable in step-down high-current applications.
Considering that the operation of the switch and the diode
of a same leg is complementary, two modes regarding the
main switches can be obtained for the proposed topology. If
the duty cycle D is higher than 0.5, overlapping mode (OM)
occurs, where two switches remain turned ON at the same
time. Otherwise, if D < 0.5, the converter operates in NOM,
while only one switch remains turned ON in a given operating
stage.
The proposed approach can be seen as the integration of the
interleaving technique and the 3SSC. The following advanta-
geous characteristics can be then addressed to the introduced
topology:
1) Reduced size, weight, and volume of magnetics, which are
designed for twice the switching frequency analogously
to the interleaved buck converter.
2) The current stress through each main switch is equal to
half of the total output current, allowing the use of semi-
conductors with lower current ratings.
400 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Fig. 1. 3SSC type B.
Fig. 2. Buck converter based on the 3SSC.
3) Losses are distributed among the semiconductors, leading
to better heat distribution and consequently more efcient
use of the heat sinks.
4) Part of the input power, i.e., 50%, is directly transferred
to the load through the diodes and the coupled inductors
(autotransformers), and not through the main switches.
As a consequence, conduction and switching losses are
reduced. This is the main difference between the func-
tionality of this approach and that of the interleaved buck
topology.
5) The use of the 3SSC allows the parallel connection of
switches and, therefore, inexpensive power devices and
drives can be used.
6) Energy is transferred from the source to the load during
most part of the switching period, which is a distinct char-
acteristic of the proposed converter, since in other buck-
type converters, it only occurs during half of the switching
period. As a consequence, reduction of current peaks and
also conduction losses are expected.
7) The drive circuit of the main switches becomes less
complex because they are connected to the same refer-
ence node, what does not occur in the interleaved buck
converter.
For the detailed description of the dcdc buck converter using
the 3SSC in NOM, the following assumptions are made:
1) the converter operates in steady state;
BALESTERO et al.: DCDC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 401
Fig. 3. Operating stages of the proposed converter in NOM-CCM. (a) First stage. (b) Second stage. (c) Third stage. (d) Fourth stage.
2) switching frequency is constant and PWM is employed to
drive the switches;
3) the gating signals of the switches are 180

displaced;
4) the turns ratio of the autotransformer is unity;
5) the magnetizing current is much lower than the load
current;
6) all semiconductor and passive elements are ideal.
A. Operation in NOM and Continuous Conduction Mode
(CCM) (D < 0.5)
The converter operation can be dened according to four
operating stages as shown in Fig. 3. The respective main theo-
retical waveforms are presented in Fig. 4, where each one of the
variables is dened as follows:
1) V
g (S1)
, V
g (S2)
gating signals applied to switches S
1
and
S
2
, respectively;
2) I
L
current through inductor L, while the maximum and
minimum values assumed by this quantity are I
M
and I
m
,
respectively;
3) I
S1
current through switch S
1
;
4) I
D1
current through diode D
1
;
5) I
V o
current through the output stage, which is the sum
of the currents through the output capacitor I
Co
and the
load I
o
;
6) V
S1
voltage across switch S
1
;
7) V
D1
voltage across diode D
1
;
8) V
L
voltage across inductor L.
Fig. 4. Main theoretical waveforms for NOM-CCM.
402 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
First stage [t
0
, t
1
] [see Fig. 3(a)]: Initially, switch S
1
is
turned ON, while switch S
2
is turned OFF. The current through
the inductor is divided in two parts. The rst one ows through
T
1
and D
2
with energy being delivered to the load. The second
one ows through T
2
and S
1
. Current sharing is maintained
since the number of turns for T
1
and T
2
is the same. The current
through L increases linearly. Windings T
1
and T
2
have the same
impedance, and the voltages across them are equal to half of the
input voltage V
i
. This stage nishes when S
1
is turned OFF.
Second stage [t
1
, t
2
] [see Fig. 3(b)]: Switch S
1
is turned
OFF, while switch S
2
remains OFF. The voltage across inductor
L is inverted. Diode D
1
is forward biased while D
2
remains
conducting. The energy stored in L during the previous stage is
then transferred to the load. The current ows through T
1
T
2
,
according to the given polarity, what causes the magnetic owin
the core to be null. The current returns to the source analogously
to the previous stage. This stage nishes when S
2
is turned ON.
Third stage [t
2
, t
3
] [see Fig. 3(c)]: Due to symmetry of the
circuit, this stage is similar to the rst one, although switch S
2
is
turned ON instead and S
1
remains turned OFF. Diode D
1
keeps
conducting and D
2
is reverse biased.
Fourth stage [t
3
, t
4
] [see Fig. 3(d)]: This stage is similar to
the second one, as the same equivalent circuit and operating
conditions are valid in this case.
1) Output Characteristic of the Converter: The static gain
expressions for the converter operating in CCM, discontinuous
conduction mode (DCM), and critical conduction mode (CRM)
are given by (1), (2), and (3), respectively. The procedure used
to obtain such expressions is the same as that employed in [21]
and will not be described here in detail.
Expression (1) clearly shows that the static gain for the pro-
posed converter in CCM is the same as that of the conventional
buck converter
G
CCM NOM
=
V
0
V
i
= D (1)
G
DCM NOM
=
1
2

D
2
+D
2
(2)
G
CRM NOM
=
1
4

1
4

__
1 16
_
(3)
where
=
2LI
o
V
i
T
s
(4)
and
I
o
output current [A];
T
s
switching period [s];
Dduty cycle.
Fromexpressions (1)(3), it is possible to determine the static
gain of the proposed converter operating at D < 0.5, as the
obtained curves are presented in Fig. 5.
Analogously to the conventional buck converter, the output
voltage is a function of the load current in DCM, and this op-
erating region must be avoided. It is worth to mention that the
maximum static gain in CRM occurs at = 0.0625 and D =
0.25 for the proposed converter. Considering the classic buck
converter, the maximum gain in CRM is veried when = 0.25
Fig. 5. Comparison between static gain curves of the conventional and pro-
posed buck converters.
Fig. 6. Ripple current through the inductor in NOM.
and D = 0.5. In practical terms, it means that the CCM region
is wider for the proposed converter. That is, for a given operat-
ing point, the necessary inductance becomes one fourth of that
required for the classical buck converter.
2) Filter Elements: The ripple current through the inductor
(I
L
) is given as
I
L
=
T
s
(1 2D) D
2L
V
i
. (5)
Expression (5) can be normalized so that the ripple current is
obtained as
=
L I
L
T
s
V
i
=
(1 2D) D
2
. (6)
Expression (6) is plotted in Fig. 6, where one can see that the
maximum ripple current occurs at D = 0.25 and = 0.0625.
BALESTERO et al.: DCDC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 403
TABLE I
DESIGN SPECIFICATIONS
Parameter Value
Input voltage V
i
=200 V
Inductor current ripple (20% of the
input current)
I
L
=3.33 A
Switching frequency f
s
=30 kHz
Rated output power P
o
=1 kW
Output voltage V
o
=60 V
Output voltage ripple V
o
=0.6 V
By choosing arbitrarily the ripple current, the inductance can
be determined as
L =
(1 2D) DT
s
V
i
2I
L
=
T
s
V
i
2I
L
. (7)
Considering the maximum ripple current which represents
the worst case, the inductance can be obtained by
L =
T
s
V
i
16I
L
. (8)
The critical inductance, whose value assures operation in
CCM, is given by
L
crit
=
V
i
T
s
4I
o
. (9)
The output capacitor can be determined as
C
o
=
I
L
4f
s
V
o
(10)
where
V
o
is the output voltage ripple [V] and
f
s
is the switching frequency [Hz].
III. DESIGN PROCEDURE
A design example of the proposed 3SSC buck converter,
which is supposed to operate in NOM, is presented as follows.
The specications are listed in Table I and were used in the
implementation of an experimental prototype. Some important
calculations are performed in order to showthe loss mechanism.
It is also worth to mention that both conduction and commuta-
tion losses are estimated under rated load condition.
A. Preliminary Calculation
Considering the operation in CCM, the static gain is
G = D =
60
200
= 0.3. (11)
The output current is
I
o
=
P
o
V
o
=
1000
60
= 16.667A. (12)
B. Inductor
The inductance is given by (7) as
L =
(1 2 0.3) 0.3 200 33.33 10
6
2 3.33
= 120 H.
(13)
The rms and peak currents through the inductor are given by
(14) and (15), respectively
I
L(rms)
=

I
2
o
+
_
V
2
i
T
2
s
D
2
(2D 1)
2
48L
2
_
= 16.69 A (14)
I
L(pk)
= I
0
+
V
i
T
s
(1 2D)D
4L
= 18.33 A (15)
The core loss in the inductor can be obtained from
P
Lb(core)
= B
2.4
_
K
H
f
L
+K
E
f
2
L
_
V
e
= 0.098 W (16)
where B = 0.04 is the magnetic ux variation, K
H
= 4
10
5
is the hysteresis loss coefcient, f
L
= 2 f
s
= 60 kHz
is the operating frequency of the inductor, K
E
= 4 10
10
is
the eddy-current loss coefcient, and V
e
= 42.5 cm
3
is the core
volume.
The copper loss in the inductor is given by
P
L(copper)
=
l
Lt
N
L
I
2
L(rms)
n
L
S
f
= 0.976 W (17)
where = 2.078 10
6
m is the copper resistivity at 70

C,
l
Lt
= 11.6 cm is the average length of one turn, N
L
= 25 is the
number of turns of the inductor, n
L
= 15 is the number of wires
in parallel, and S
f
= 0.003221 cm is the cross-sectional area of
copper wire AWG23.
C. Autotransformer
The maximum voltage across the windings is
V
T 1
=
V
i
2
= 100 V (18)
The rms and peak currents through transformer T
1
are given
by (19) and (20), respectively
I
T (rms)
=
1
2

I
2
o
+
_
V
2
i
T
2
s
D
2
(2D 1)
2
48L
2
_
= 8.35 A (19)
I
T (pk)
=
I
o
2
+
V
i
T
s
(1 2D)D
8L
= 9.17 A. (20)
The core loss in the autotransformer can be obtained from
P
T (core)
= B
2.4
_
K
H
f
T
+K
E
f
2
T
_
V
e
= 0.94 W (21)
where B = 0.15 is the magnetic ux variation, K
H
= 4 10
5
is the hysteresis loss coefcient, f
T
= 2 f
s
= 60 kHz is the
operating frequency of the transformer, K
E
= 4 10
10
is the
eddy-current loss coefcient, and V
e
= 42.5 cm
3
is the core
volume.
The copper loss in the windings of the transformer is given
by
P
T (copper)
=
2l
T t
N
T
I
2
T (rms)
n
T
S
f
= 0.94 W (22)
where = 2.078 10
6
m is the copper resistivity at 70

C,
l
T t
= 11.6 cm is the average length of one turn, N
T
= 14 is the
number of turns of the 1:1 autotransformer, n
T
=5 is the number
404 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
of wires in parallel, S
f
=0.005176 cmis the cross-sectional area
of copper wire AWG20.
D. Main Switches
The threshold voltage across one main switch is
V
S1
= V
i
= 200 V. (23)
The average current I
S1(avg)
and the rms current I
S1(rms)
through the switch are given by (24) and (25), respectively
I
S1(avg)
=
1
2
I
O
D = 2.5 A (24)
I
S1(rms)
=

_
D
4

_
I
2
o
+
V
2
i
T
2
s
D
2
(2D 1)
2
48L
2
_
= 4.57 A.
(25)
MOSFET 5015VBR manufactured by APT was then chosen
as the main switch, whose characteristics are drain to source
voltage V
DS
= 500 V, diode forward voltage V
S (F )
= 1.3 V,
drain current I
D
= 32 A, on resistance R
DS(on)
= 0.15 , rise
time t
r
= 14 ns, and fall time t
f
= 11 ns.
The conduction loss regarding each main switch is
P
S1(cond.)
=V
S1(F )
I
S1(avg)
+R
DS(on)
I
2
S1(rms)
= 6.383 W
(26)
The switching loss during turn ON and turn OFF for a single
switch is
P
S1(sw)
=
f
s
2
(t
r
+t
f
)I
S1(avg)
V
S1
= 0.188 W. (27)
E. Main Diodes
The reverse voltage across one diode is
V
D1
= V
i
= 200 V. (28)
The average current I
D1(avg)
, the rms current I
D1(rms)
, and
the peak current I
D1(pk)
through the diode are given by (29),
(30), and (31), respectively
I
D1(avg)
=
I
O
2
(1 D) = 5.83 A (29)
I
D1(rms)
=
1
2

_
(1 D)
_
I
2
o
+
V
2
i
T
2
s
D
_
D
1
2
_
2
12L
2
_
=6.984 A
(30)
I
D1(pk)
=
I
o
2
+
V
i
T
s
(1 2D)D
8L
= 9.17 A. (31)
Ultrafast diode RHRP840 was then chosen, whose charac-
teristics are reverse voltage V
D(rev.)
= 400 V, forward voltage
V
D(F )
= 1.7 V, average forward current I
F
= 8 A, and reverse
recovery time t
rr
= 30 ns.
Estimating the intrinsic resistance of the diode fromthe curves
given in the datasheet as R
D
=50 m, conduction loss regarding
each diode becomes
P
D1
= V
D1(F )
I
D1(avg)
+R
D1
I
2
D1(rms)
= 12.35 W. (32)
Fig. 7. Comparison between the theoretical efciency curves for the conven-
tional buck and 3SSC-based buck converter.
Switching losses regarding the diodes are given as
P
S1(sw)
=
1
2
_
V
D(F )P
V
D(F )
_
I
D1(avg)
t
rise
f
s
+V
D1
Q
rr
f
s
= 0.3366 W (33)
where V
D(F )P
= 2.1 V is the maximum value assumed by the
forward voltage, t
rise
= 18 ns is the rise time of the current
through the diode, and Q
rr
= 56 nC is the amount of charge
stored in the intrinsic capacitance of the diode.
F. Theoretical Comparison With Other Buck-Based Topologies
The proposed converter can be compared with similar ap-
proaches from the theoretical point of view, such as the clas-
sical buck converter. Since the current stress through the main
switches is reduced analogously to the interleaved buck con-
verter, this topology will also be considered in the analysis.
The aforementioned converters were then properly designed
according to the specications in Table I. The same semicon-
ductors chosen for the 3SSC-based buck converter were used to
establish a fair comparison. Losses in semiconductors and mag-
netic elements were then estimated by using the methodology
described in Section III-AIII-E, considering the output power
ranging from 100 W to 1 kW. The theoretical efciency curves
for the converters are shown in Fig. 7, where it can be seen that
high efciency results for the proposed converter over the entire
load range, what is basically due to the signicant reduction of
the current stress through the semiconductors and the use of the
3SSC.
The performance of the interleaved buck converter is similar
to that of the proposed topology, basically due to parallel oper-
ation of the semiconductors. Considering the circuit in Fig. 2,
it can be seen that the drive circuitry for switches S
1
and S
2
does not demand isolation because their source terminals are
both connected to the same reference node, what is an advan-
tage over the interleaved topology. Besides, current sharing is
of great concern in interleaving converters [22], [23], what is
assured in the 3SSC buck converter due to the autotransformer
without the use of special control schemes.
It is also worth to establish a fair comparison with similar
approaches that exist in the literature. For instance, the work
proposed in [24] introduces an interleaved buck converter with
BALESTERO et al.: DCDC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 405
Fig. 8. Voltage (CH2) and current (CH3) waveforms for switch S
1
.
coupled inductors in a same magnetic core. A small capacitor
is also introduced to obtain a turn-off snubber, while switching
losses are minimized and conduction losses are increased due
to additional amount of circulating reactive energy. Besides,
furthermore, soft switching for the entire load range is difcult
to obtain when dealing with passive snubbers [25].
A synchronous dcdc buck converter with interleaved mul-
tiphase and integrated coupled inductors is studied in [26].
Of course, the aforementioned topology employs two switches
per phase and may not be competitive in terms of component
count and robustness with the conventional interleaved con-
verter. However, the coupled inductors cannot be treated as two
individual inductors because of the coupling effect, and the mu-
tual inductance between the windings will affect the converter
operation. This inconvenience is not veried in the proposed
topology.
IV. EXPERIMENTAL RESULTS
An experimental prototype was then implemented according
to the previous session. Fig. 8 presents the voltage and current
waveforms regarding switch S
1
, which are similar to those ones
for switch S
2
. An RCD snubber could be employed to alleviate
the voltage peak across the switch, although it may reduce the
efciency.
Fig. 9 shows the voltages across switches S
1
and S
2
, as well
as the currents through inductor L and switch S
2
. It becomes
evident that the switching frequency is half of the ripple current
frequency, what leads to the reduction of magnetic elements.
Fig. 10 represents the voltages across D
1
(CH1) and D
2
(CH2), and also the currents through D
1
(CH3) and D
2
(CH4).
It can be seen that overlapping occurs for the diodes during the
second and fourth operating modes, as predicted in Fig. 3(b) and
(d), respectively. However, it must be mentioned that the main
switches do not remain turned ON simultaneously.
Fig. 11 shows the voltages across D
1
and S
1
, and also their
respective currents. It becomes evident that the operation of such
semiconductor elements is complementary.
Fig. 9. Voltages across switches S
1
(CH1) and S
2
(CH2), current through
inductor L (CH3), and current through switch S
2
(CH4).
Fig. 10. Voltages across D
1
and D
2
(CH1 and CH2, respectively) and currents
through D
1
and D
2
(CH3 and CH4, respectively).
Fig. 11. Voltages across D
1
and S
1
(CH1 and CH2, respectively) and currents
through D
1
and S
1
(CH3 and CH4, respectively).
406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Fig. 12. Static gain as a function of the output current.
Fig. 13. Efciency as a function of the output power.
Fig. 12 presents the variation of the static gain plotted as a
function of the output current. Experimental results seem to be
very close to those predicted in the theoretical analysis.
The experimental prototype was evaluated over a wide load
range and the efciency curve of the converter operating at
30 kHz is presented in Fig. 13. Even though the efciency curve
does not match the one shown in Fig. 7 exactly, the prole of
both plots is similar. That is, the use of the 3SSC leads to high
efciency, which is higher than 94% practically over the entire
output power range, demonstrating the merit of the proposed
converter. This is not observed in typical buck topologies that
are not based on the 3SSC. Energy transfer from the source to
the load occurs during almost the entire switching period for
the 3SSC topology. On the other hand, in the conventional buck
converter, it does only occur during part of the switching period,
namely when the main switch is OFF and the output capacitor is
charged. It certainly contributes for the reduction of the current
peak in the switches causing efciency to increase.
V. CONCLUSION
A dcdc buck converter based on the 3SSC has been pre-
sented. When the 3SSC is employed, the current is distributed
among the semiconductors. Furthermore, only part of the energy
from the input source ows through the active switches, while
the remaining part is directly transferred to the load without
being processed by these switches, i.e., this energy is delivered
to the load through passive components, such as the diodes and
the transformer windings.
Despite the increase in the number of semiconductors, the
current levels on these devices are reduced, enabling the use
of inexpensive switches and simplied command circuits be-
cause the isolated drive is not required like in the interleaved
buck converter. In front of these characteristics, its use is rec-
ommended for high-power high-current applications where the
traditional approach may be inadequate, while good current
sharing is achieved.
In addition, the overall losses are distributed among all semi-
conductors, reducing the heat sink efforts. The reactive compo-
nents operate with twice the switching frequency, with signi-
cant reduction in weight and volume of such components.
Considering the operation in NOM (D < 0.5) and the same
ratings, the following characteristics can be addressed with the
3SSC-based converter if compared with the conventional buck
topology:
1) increased number of semiconductor elements;
2) the operating area in CCM is wider;
3) the ripple current through the inductor is reduced, as well
as the currents through the switches;
4) reactive elements are designed for twice the switching
frequency, causing the required critical inductance to be
smaller, for instance;
5) only 50% of the power is delivered to the load through the
main switches due to the magnetic coupling between the
transformer windings.
Besides, an important advantage of the proposed converter
operating in OM (D >0.5) is the continuous nature of the input
current, which is inherently discontinuous in the conventional
buck converter, what may lead to the use of an input lter for
some applications.
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Juan Paulo Robles Balestero was born on Febru-
ary 20, 1978, in Jales, Brazil. He received the B.Sc.
and M.Sc. degrees in electrical engineering from the
State University of S ao Paulo, Ilha Solteira, Brazil,
in 2004 and 2006, respectively.
He is currently a Professor with the Federal Insti-
tute of Education, Science and Technology of Santa
Catarina, Chapec o, Brazil. His research interests in-
clude dcdc converters and converter topologies.
Fernando Lessa Tofoli was born on March 11, 1976,
in S ao Paulo, Brazil. He received the B.Sc., M.Sc.,
and Ph.D. degrees in electrical engineering from the
Federal University of Uberlandia, Uberlandia, Brazil,
in 1999, 2002, and 2005, respectively.
He is currently a Professor with the Federal
University of S ao Jo ao del-Rei, S ao Jo ao del-
Rei, Brazil. His research interests include power-
quality-related issues, high-power factor rectiers,
and soft-switching techniques applied to static power
converters.
Grover Victor Torrico-Bascop e (M04) received
the B.Sc. degree in electrical engineering from San
Sim on University, Cochabamba, Bolivia, in 1993,
and the M.Sc. and doctorate degrees in electrical
engineering from the Federal University of Santa
Catarina, Florianopolis, Brazil, in 1996 and 2001,
respectively.
From2001 to 2002, he was an Advisor with Emer-
son Energy System, Brazil, where he developed ac/dc
three-phase rectiers. In 2003, he was a Senior De-
sign Engineer with Emerson Network Power Com-
pany, Ltd., Stockholm, Sweden. From 2004 to 2009, he was a Senior Engineer
in Power Electronics Designs with the R&D Group, Eltek Valere AB, Sweden,
where he developed ac/dc three-phase and single-phase highly efcient recti-
ers and dc/dc multioutput supplies to the telecom industry. Since July 2009,
he has been a Senior Design Engineer with GTB Power Electronics Research
and Technology AB, Kista, Sweden, where he is currently a Consultant and
is offering new high-efciency (HE) circuit topologies to the power electronic
industry. He has published more than 20 technical papers and is the holder of
two patents. His main research areas are in industrial power electronics and
creating new platforms with HE topologies for high-power and green energy
applications.
Falcondes Jos e Mendes de Seixas was born in Jales,
SP, Brazil in 1965. He received the B.S. degree in
electrical engineering from the Engineering School
of Lins, Lins, Brazil, in 1988 and the M.S. and Ph.D.
degrees in electrical engineering from the Federal
University of Santa Catarina, Florianpolis, Brazil, in
1993 and 2001, respectively.
He is currently an Assistant Professor at the De-
partment of Electrical Engineering, Universidade Es-
tadual Paulista (UNESP), Ilha Solteira, Brazil. His
research interests include power factor correction,
switching mode power supplies, and multipulse transformer applications.