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1. 2. 3. 4. Fundamental Digital Gates Combinational Gates Basic Logic Gates Summary Logic NAND
NOT
Q = NOT A
AND
Q=A.B
OR
Q=A+B
XOR
Q=A+B
Buffer
NOT Gate [edit] Digital Gate Combinational Gates Symbol Mathematical Expression Truth Table AB 01 10
NOT Gate
Y = is NOT A
NAND Gate [edit] Digital Gate Combinational Gate Symbol Mathematical Expression Truth Table AB 01 10
Buffer
Y = is NOT A
NOR Gate [edit] Digital Gate Combinational Gate Symbol Mathematical Expression Truth Table AB 01 10
NOT
Y = is NOT A
XNOR Gate [edit] Basic Gates Combinational Gate Symbol Mathematical Formula Truth Table AB 01 10
NOT Gate
Y = is NOT A
NOT
Q = NOT A
AND
Q=A.B
NAND
Q=A.B
OR
Q=A+B
NOR
Q=A+B
XOR
Q=A+B
XNOR
Q=A+B
100 111 ABQ 000 010 100 111 ABQ 000 011 101 111 ABQ 000 011 101 111 ABQ 000 011 101 110 ABQ 000 011 101 110
NOT [edit]
A NOT gate is made by joining the inputs of a NAND gate. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT part.
Desired Gate
NAND Construction
AND [edit]
An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND. Desired Gate NAND Construction
OR [edit]
If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. However to be an OR gate, if any input is 1, the output must also be 1. Therefore, if the inputs are inverted, any high input will trigger a high output. Desired Gate NAND Construction
0 0 1 1
0 1 0 1
0 1 1 1
NOR [edit]
A NOR gate is simply an OR gate with an inverted output: Desired Gate NAND Construction
XOR [edit]
An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low. This effectively represents the formula: "(A NAND (A NAND B)) NAND (B NAND (A NAND B))". Desired Gate NAND Construction
1 1
0 1
1 0
XNOR [edit]
An XNOR gate is simply an XOR gate with an inverted output: Desired Gate NAND Construction