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IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 4, APRIL 2001

Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide
G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, Robert A. Weller, Member, IEEE, S. T. Pantelides, Leonard C. Feldman, Member, IEEE, O. W. Holland, M. K. Das, and John W. Palmour, Member, IEEE

AbstractResults presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO2 interface states near the conduction band edge by high temperature anneals in nitric oxide. Hilo capacitance-voltage (CV) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2 1013 to 2 1012 eV 1 cm 2 following anneals in nitric oxide at 1175 C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 3035 cm2 V-s following the passivation anneals. Index TermsInterface states, mobility, MOSFETs, nitridation, oxidation, silicon carbide.

I. INTRODUCTION ILICON carbide is the only wide band gap semiconductor that has a native oxide, and metal-oxide-semiconductor field effect transistors (MOSFETs) have been fabricated using both 4H- and 6H-SiC. The 4H polytype has higher bulk carrier mobility [1], and is hence the polytype of choice for power MOSFET fabrication. However, reported channel mobilities for 4H n-channel, inversion mode devices are substantially lower than for 6H-MOSFETs. For power device applications, the advantage provided by 4H-SiC of lower epilayer resistance for a given operating voltage is compromised by the low channel mobility. Schorner, et al. [2] attribute the poorer performance of 4H devices to a large, broad interface state density located at approximately 2.9 eV above the valence band edge in both
Manuscript received November 17, 2000; revised December 27, 2000. This work was supported by DARPA Contract MDA972 98-1-0007 and EPRI Contract W0806905. Research at Oak Ridge National Laboratory sponsored by the Division of Material Sciences, U.S. Department of Energy, under Contract DE-AC05-00OR22725 with UT-Battelle, LLC. The review of this letter was arranged by Editor T.-J. King. G. Y. Chung, C. C. Tin, and J. R. Williams are with the Physics Department, Auburn University, AL 36849 USA (e-mail: williams@physics.auburn.edu). K. McDonald and R. K. Chanana are with the Department of Physics and Astronomy, Vanderbilt University, Nashville, TN 37235 USA. R. A. Weller is with the Department of Electrical Engineering and Computer Science, Vanderbilt University, Nashville, TN 37235 USA. S. T. Pantelides and L. C. Feldman are with the Department of Physics and Astronomy, Vanderbilt University, Nashville, TN 37235 USA. They are also with Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA. O. W. Holland is with the Solid State Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA. M. K. Das and J. W. Palmour are with Cree Research, Inc., Durham, NC 27713 USA. Publisher Item Identifier S 0741-3106(01)02864-6.

polytypes. More of these states lie in the band gap for 4H-SiC eV compared to 6H-SiC eV where they act to reduce channel mobility through field termination, carrier trapping and Coulomb scattering. Afanasev, et al. [3] proposed that interface states in SiC/SiO structures result from carbon clusters at the interface and defects in a near-interface sub-oxide that is produced when the oxidation process is terminated. The large interface trap density near the conduction band edge proposed by Schorner, et al. has been observed experimentally for both n-SiC [4], [5] and p-SiC [6]. Li, et al. [7] originally reported improvements in the electrical performance of dry oxides on 6H-SiC annealed in nitric oxide (NO). We have recently annealed wet oxides in NO [8] and found that the interface state density near the conduction band edge in n-4H-SiC can be reduced to levels comparable to the interface state density near the conduction band edge in 6H-SiC. Results presented in this letter show that the effective channel mobility for inversion-mode 4H-SiC MOSFETs improves significantly following high temperature anneals in nitric oxide. II. EXPERIMENT Five micron 4H-SiC -epilayers cm on n -substrates were oxidized for MOS capacitor fabrication using standard, wet oxidation techniques that have been described elsewhere [9]. Dry oxide layers were also grown using identical procedures except that the TCA and H O bubblers were bypassed. Following oxidation (wet or dry) to produce 40 nm oxide layers, samples were annealed in a second furnace in NO (1 atm, 0.5 l/min, 1175 C, 2 h). Molydenum was sputter-deposited to form oxide gate contacts, and large area substrates using backside ohmic contacts were formed to the Ag colloidal paste. Standard high frequencylow frequency (1 MHz/quasistatic) capacitancevoltage (CV) and ac conductance techniques were used for interface state density measurements near the conduction band edge. Lateral 4H-SiC MOSFETs were also fabricated with either cm or 10 m cm -4H-epilayers. 3 m All dry and wet oxide layers (thickness 40 nm) were grown and passivated at either Auburn or Vanderbilt except for one control wafer with 3 m epi that was oxidized at Cree, Inc. A 40 nm oxide layer was grown on this control wafer using Crees standard oxidation process1200 C dry O for 2.5 h, 1200 C Ar for 1 h and 950 C wet O for 3 h. Lateral MOSFETs were fabricated and characterized at Cree on the control wafer and

07413106/01$10.00 2001 IEEE

CHUNG et al.: IMRPOVED INVERSION CHANNEL MOBILITY FOR 4H-SiC MOSFETS FOLLOWING HIGH TEMPERATURE ANNEALS IN NITRIC OXIDE

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Fig. 1. Interface state density for n-4H-SiC MOS capacitors before and after anneals in NO at 1175 C for 2 h. The hilo CV measurements were made at room temperature and confirmed with AC conductance measurements. Re-ox refers to samples that were not annealed in NO. In agreement with the suppositions of Schorner, et al. [2], the passivation anneal is noticeably more effective for 4H-SiC.

Fig. 2. Field effect mobility for dry oxide 4H-SiC MOSFETs fabricated with and without an NO passivation anneal at 1175 C for 2 h.

on a second wafer (also with 3 m epi) that was oxidized at Auburn using the wet 1100 C oxidation process described in [9] and subsequently passivated with NO at Vanderbilt. Nitrogen source/drain implants for both wafers were activated at Cree with a 3 h, 1200 C Ar anneal. Sputtered Mo was patterned to form MOSFET gates with dimensions 250 m 250 m. Lateral MOSFETs with dry oxides were processed entirely at Auburn starting with 10 m -epilayers. These devices had a gate length of 120 m and source/drain dimensions of 200 m (length) 400 m (width). Molydenum was sputter-deposited for gate contacts. Nitrogen source/drain implants were annealed at 1575 C for 30 min inside a polycrystalline SiC pillbox in 1atm of flowing Ar. Nickel was deposited on the source/drain regions; however, the contacts were not annealed prior to making channel mobility measurements. III. RESULTS AND DISCUSSION The results of standard hilo (quasistatic) CV measurements for -4H-SiC MOS capacitors following NO passivation anneals of 2 hr at 1175 C are shown in Fig. 1. Re-ox refers to samples that were not annealed in NO. Re-oxidation is a standard wet oxidation termination step [10] that is carried out at several hundred degrees below the oxidation temperature of 1100 C in order to reduce the interface state density near mid-gap for -SiC/SiO [4], [10], [11]. As shown in Fig. 1, NO passivation reduces the interface state density significantly. The trap density at 0.1 eV below the conduction band edge decreases by approximately one order of magnitude (from about to eV cm after NO annealing. AC conductance measurements performed at Cree for similar samples confirm the CV data presented in Fig. 1. The results of mobility measurements for a lateral 4H-SiC MOSFET fabricated with a dry oxide are shown in Fig. 2. The device has a peak channel mobility of approximately 30 cm /Vs, and shows a 14 improvement in peak mobility as a result of the NO passivation anneal. Similar results are obtained for wet oxide MOSFETs. Fig. 3(a) shows a plot of drain current versus gate voltage that was used to determine a peak effective mobility of 5 cm /V-s for a device fabricated with Crees standard drywet oxide. Fig. 3(b) shows the improvement in mobility

Fig. 3. (a) Drain current as a function of gate voltage for a MOSFET fabricated with Crees standard, drywet oxidation procedure. Analysis (@I =@V ; V = 50 mV) resulted in a peak effective mobility of 5 cm /Vs. (b) Mobility versus gate voltage and I V characteristics for a device fabricated with a wet oxide grown at Auburn and an NO anneal performed at Vanderbilt. I V characteristics for the standard device are included for comparisons that show reduced threshold voltage and significantly improved turn-on behavior for the passivated MOSFET.

that can be achieved with NO passivation. Drain current-gate voltage characteristics are also plotted in Fig. 3(b) for the standard and passivated MOSFETs. The standard device exhibits the soft turn-on, high threshold, and single digit mobility [Fig. 3(a)] typical of 4H-SiC MOSFETs. However, the MOSFET annealed in NO has a 5 V threshold, relatively sharp turn-on, and a peak channel mobility of 37 cm /Vs. The characteristics of both the dry and wet oxide devices are consistent with a lower interface state density near the conduction band edge. Also, the mobility versus gate voltage behavior for both the wet and dry oxide devices is similar to that of silicon MOSFETs [12] with only a 1520% reduction in mobility at the higher gate voltages where the devices will typically be operated. However, unlike silicon, the mobilities reported here

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for SiC are a much smaller fraction of the bulk mobility (10% for SiC compared to 50% for Si). This difference can be attributed to the fact that, even after NO passivation, the interface state density near the conduction band edge is still ten times higher for SiC compared to Si. Full wafer testing for the wet oxide devices resulted in a yield of 90% and an average effective mobility of 33 cm /Vs. Furthermore, every working device on the 3.5 cm diameter wafer had a peak mobility greater than 30 cm /Vsan indication that the NO passivation process was very uniform. Measured channel mobilities for lateral 4H-SiC MOSFETs fabricated with standard epilayers and standard thermal oxidation techniques are typically well below 10 cm /Vs. A number of attemptsincluding the NO passivation process reported hereinhave been undertaken in an effort to improve the effective channel mobility. Sridevan, et al. [13] reported n-channel mobilities as high as 165 cm /V-s for deposited and Ar. Ogino, et al. oxides subsequently annealed in wet [14] observed significant improvements in mobility (as high as 99 cm /V-s) following low dose N implants into the channel region that were designed to adjust device threshold voltage. Yano, et al. [15] fabricated MOSFETs with wet thermal oxides grown on the (11 0) face of 4H-SiC and reported effective channel mobilities of around 30 cm /Vs. However, to our knowledge, the results reported in this letter are the first to show substantial improvement in the inversion channel mobility for lateral n-channel MOSFETs fabricated with standard thermal oxidation techniques and standard 4H-SiC. Whether used separately or in conjunction with other techniques such as low dose implantation, the NO passivation process represents significant progress in 4H-SiC MOSFET development.

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