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Ye Ye Mon

W W L Keerthipala

School of Electrical& Computer Engineering Curtin University of Technology Perth, WA 6845, Australia

T a n Li San

Tel : 61-8-9266-7901

Fax: 61-8-9266-2584

Email: ywmon0iinet.net.au

Abstract: This papex presents the analysis and simulation of single phase Multi-level and Multi-modular PWM inverters and three phase Multi-level inverters using the solhare called Power System Computer Aided Design (PSCAD). Multi-level voltage source inverters offer several advantages compared to their conventional ones. This technology is based on t h e synthesis of the AC .voltage from several different voltage levels on the DC bus. As the number of voltage levels on the DC si& increase, the synthesised output adds more steps, producing staircase wave which approaches the sinusoidal wave with the minimum harmonic distortion. To achieve this,one of the switchmg techniques called Pulse-Width Modulation (PWM) is applied. In this technique, the comparison of &er frequency and fundamental frequency is performed to produce modulated frequency. As the carrier hquency increases,the width of the modulated signal become narrower and hence it leads to a smoother output waveforms. The effect on Total Harmonic Distortion (THD) is investigated on both proposed Multi-level and Multi-Module designs.

Power Converters both AC to DC and DC to AC are crucial in Hybrid power conversion schemes. In order to integrate renewable energy sources such as Solar and Wind energy with the existing power supplies or with an isolated Diesel generator, it is essential to have power conversion scheme which can be readily convert AC to DC and vice versa. Another application involving power converter is in hospitals, which required certain machines to be turned on 24 hours. In the emergency case like power failure, the back-up battery, which is in DC, is needed to be converted to AC in order to have un-interruptible power supply. PWM technique which is used in this analysis has been coded as the most popular and economical method of the voltage and frequency control [5]. The justification for PWM multi level converter is to achieve a higher voltage and in turn higher power processing capability. By applying this method, it varies the conduction time of the switching transistor during the ON period to control and regulate the output voltage predetermined value. The advantages are that it produces excellent performance for tight line and load regulation and achieve stability during temperature variation. The simulation results, analysis and designs of the most feasible Multi-level and Multi-module inverters are presented.

II. SINGLE-PHASE MULTI-LEVEL INVERTERS

1. INTRODUCTION In AC-DC conversion, rectifier refers to a converter when the average power flow is from AC to DC side and in DC-AC

conversion, inverter refers to the converter when the average power flow from DC to AC side [5]. The power flow through may be reversible. Converters can be classified accordiflg to how the devices within the converters are switched. There are t h r e e possibilities:

0)

Line frequency converters: the utility line voltage present at one side of the converter facilitates the turn-off of the power semiconductor devices. Switching converters: the controllable switches in the converter are turned on and off at higher frequencies compared to the line frequencies. Resonant and quasi-resonance converters: the controllable switches turn on and/or off at zero andlor zero current [5].

Multi-level inverters are the modification of basic bridge inverters. They are normally connected in series to form stacks of levels. The following sections discuss about the Multi-level inverters and the measure of T o t a l Harmonic

Distortions (THD).

(ii)

The basic circuit design of single-phase 2 level topology is illustrated in figure 1. It is conslructed by modifying the conventional bridge rectifier and adding bidirectional switches, such as IGBTs, to the inverter circuit, The DC capacitor voltage source is supplied by 120V c o n q t DC battery energy storage. This particular inverter prdpce a 50Hz,AC output voltage of 240 Vrms and 339.411 Vpeak.

(iii)

0-7803-6338-8/00/$10.00(~)2000 IEEE

469

The operation of the gates as shown in figure 1 is based on the bidirectional switching technique. The number of main operating switches canbe given by:

The circuit design of the single phase three-level is constructed by adding another bridge inverter in series to the two-level inverter. Since the tenn level refers to the number of DC buses that the inverter can be accessible, the three-level inverter has configuration of three accessible DC buses with nodes connected to the DC link capacitors. These capacitors act as energy tanks for the inverter and are connect& in series. They provide nodes or DC buses for the multi-level inverters to be connected. Primarily, the dc-link voltage across each capacitor tank is assumed to be the voltage sources of the multi-level inverters. The number of capacitor tanks can be given by:

The number of auxihary switches can be given by:

(1)

Where N is the number of inverter-levels employed.

(2)

Applying the above two expressions, the utilization of switches for two-level inverter can be designed. There are two main operating switches( G1 and G3)and two auxiliary 4 ) . Extending the basic principle from switches ( G2 and G u r n off G1, PWM switching technique, G2 is served to t thereby diverting the current &om G1. Whereas, G4 served to tum off G3, thereby diverting the current from G3. In other words, the complimentay switch pair is defined such that huning on one pair switches will exclude the other from being turned on. Thdore, for positive half of the output waveform, GI and G4 is ON whereas G2 and G3 is OFF. Similarly, for the negative half, G2 and G3 are ON whereas GI and G4 are OFF.The output waveform before feeding into the filter is illustrated in figure 2.

Where N is the number of inverter-levels employed. From the above expression (3), it can be intended that two DC-link capacitors will be employed here. Each DC capacitor source has a voltage of 60V across and supplied by 120 V constaut DC battery energy storage. The output has the same value as that of two-level inverter. There are four carrier signals compared with one modulating signal. carrier 1 and 2 for the positive cycle are set to produce a voltage magnitude of 0.5 to 1 and 0 to 0.5 in 1 unit level respectively. Whereas, carrier 3 and carrier 4 for the negative cycle are set to produce a voltage magnitude of 0 to -0.5 and -0.5 to 1 unit level respectively. The output waveform for the 3-leve inverter is as shown in figure 3.

= t

1 0 -1

O

0 . -

0.118

0.127

0 . 1 -

0.148

N o t e &om the waveform that a three-level inverter produces two levels of output voltage with respect to a zero reference level. Therefore, compad with the two-level inverter, the shape of it is closer to the shape of the sinusoidal waveform. The THD measured is 21.98% which is around half of that of

2-level inverter.

The gate s i @ are controlled by the PWM switching logic where t h e carrier firequency of 5000Hz is c o m p a r e d with the modulating fresuency of 50Hz to produce pulses with amplitude value of 1. These frequencies are used throughout the analysis. The wavefonn shown in figure 2 is line-to-line voltage and the total harmonic distortion is measured using the PSCAD software.The value of THD of 2-level inverter is

42.63% without filtering.

The circuit design of a single-phase, four level inverter is coI1stf)lcted by modifying the previous three-level inverter topology whereby another single-phase bridge inverter is ed series. added to the configuration and c o ~ e ~ t in

470

accessible to the inverter. The nodes of these DC buses are connected to the DC l i n k capacitor. Therefore, from expression (3), three capacitors are employed and each has a 40V across and supplied by the 120V constant DC battery energy storage. It has the same output values as the abovementioned inverters. Since the number of triangular carrier signal per phase can be given by expression (4), there are three triangular carriers per phase with respect to the zero reference voltage level.

set to produce a voltage magnitude of 0 to 0.25, 0.25 to 0.5, 0.5 to 0.75 and 0.75 to 1 respectively. Whereas, triangular carriers 5,6,7 and 8 representing the negative cycle are set to produce a voltage magnitude of 0 to -0.25, -0.25 to -0.5 and -0.5 to -1 respectively. The carrier fkquency and the modulating frequency have the same value as in the abovementioned inverters. The output waveform for the 5-level inverter is shown in figure 5.

(4)

4

0.12

0.14

0.16

0.18

0.2

Triangular carriers 1,2 and 3 representing the positive half cycle are set to produce a voltage magnitude of 213 to 1, 113 to 2/3 and 0 to 1/3 respectively. Whereas, triangular carriers 4,5 and 6 representing the negative cycle are set to produce a voltage magnitude of 0 to -1/3, -1/3 to -2/3 and -213 to -1 respectively. All six carrier signals have a high frequency of 5000 Hz and modulating frequency of 50 Hz. The output waveform for the 4-level inverter is shown in figure 4.

3

2

1

Note from the output waveform that there are four levels of output voltage per phase with respect to the zero voltage level. This 5-level inverter topology shown better overall system performance compared to the four-level inverter previously mentioned. The THD measured is 11.30%. Therefore, in summary, as the number of inverter levels increases, more steps are added to the output and hence more desirable sinusoidal waveforms are achieved. In addition, the total harmonic distortion is reduced as the level increased. Therefore, the overall system performance is improved with lesser harmonics.

0 -1

a

J

0.01

om

0.-

0.04

produces three-levels of output voltage per phase with respect to a zero reference voltage level. Thus, theoretidy speaking, a four-level inverter achieve better overall system performance compared to the two-level and three-level in terms of obtaining a more desirable sinusoidal waveform. The THD measured is 20.32Yi which is lesser than the 3level inverter.

Multi-module inverter is an extension of the Multi-level P W M inverter scheme where the multi-level inverters are connected i n parallel. For example, based on the above 5level inverter system, the multi-modular system shown in figure 6 is developed [5]. In this modular system, each module of a 5-level converter is controlled using a phaseshifted P W M technique. The phase-shift introduced is calculated with respect to the period of the carrier signal and the number of modules being in parallel. Multimodular PWM inverter topology has employed the phase-shifted &er synthesis so as to achieve a higher sampling rate. This way, the switching rate of each modular semiconductor devices can be kept low, hence producing a lower switchingloss and higher power ratings. The phase-shifted delay of each module can be given by: T numberof mod ules

The power circuit design of a single-phase five-level topology is constructed by modifying the four-level inverter topology whereby another single phase bridge inverter is added to the configuration series connection. There are five DC buses that are accessible to the inverter. The nodes of these DC buses are c o ~ e c t e d to the DC-link capacitors. From expression (4), four capacitors are employed and each has 30 V across them and is supplied by 120V constant DC batteq energy storage. It has the same output values as in the previous inverter. In order to have the five-levei Staircase output, the zero level voltage level is considered as the reference. Triangular carriers 1 , 2 3 and 4 representing the positive half cycle are

Delay =

47 1

16.47% which is less than the 2-module inverter. The output waveform for the 3-module inverter is as shown in figure 8.

Note from this waveform that more steps are added on and hence a more desirable sinusoidal output is obtained.

PI

A. Two-module inverter

C. Four-module inverter

The circuit of a single-phase four-module is constructed by connecting four modules of two-level inverter in parallel at their DC buses and AC terminals. As in the above-mentioned module system, there are two main operating switches and two auxiliary switches in each module. From equation (9, the phase-shift of each triangular carrier is of 45 degrees. The carrier fresuency and modulating frequency are the same as the above-mentioned system.

The circuit of a single-phase two-module inverter is constructed by connecting two modules of two-level inverter t their DC buses and AC terminals in a similar in parallel a fashion as in figure 6. Two-level inverter is employed in this study to demonstrate the performance of multi-modular PWM inverter topology due to its simplicity. DC link capacitors served as the energy tank which is supplied by the DC battery voltage source. In this case,the DC capacitors voltage is supplied by 120 V constant DC voltage source. There are two main operating switches for each module and two auxiliary switches for each module which is similar to two-level inverter. The only difference is that the triangular carrier signal in each module has its individual phase-shift with respect to its neighbour. From equation (9,the phase shift in each triangular carrier for the two- module of twolevel inverter is of 90. The active devices need only to switch at 100 Hz with the modulating signal at 50 Hz.Hence, with this low switching frequency, a lower switch loss can be achieved compared to the two-level inverter alone. The THD measured is 22.73%. The output Waveform for the 2-module inverter is shown in figure 7.

-2

08055

o.oii

o n 1 6 5 0.-

The output waveform is illustrated in figure 9. The THD measured is 12.33% which is less than 3-module inverter. Note also from this waveform that more steps are added on and hence a more desirable sinusoidal output is obtained.

-2 -1

:r i,l

3-

D. Five-module inverter

The power circuit of a single-phase five-module inverter is constructed by connecting five modules of 2-level inverter in parallel at their DC buses and AC terminals. As in the abovementioned module system, there are two main operating switches and two auxiliary switches in each of the five modules. From expression (3, the phase-shift of each triangular is of 36 degrees. The same Canier fresuency and modulating frequency are applied as in above-mentioned systems. The output waveform of the four-module inverter is shown in figure 10. The THD measured is 9.08%, which is less than 4-module inverter. As more steps are added on to this waveform, a smoother sinusoidal output is obtained.

OB025

0.035

0.045

B . Threemodule inverter

The power circuit of a single-phase, 3- module inverter is constructed by connecting three modules of 2-level inverter t their DC buses and AC terminals. As in the in parallel a two-module system, there are two main operating switches and two auxiliary switches in each module. From equation (9,the phase s h i f t of each triangular CaRier is of 60 degree. The carrier frequency and modulating fresuency are the same as the above-mentioned system. The THD measured is

-1

5 0-

o m 5

om1

0.0965

0.182

472

In summary, as the number of modules increases, the more steps are added on to the output waveform and hence achieve a more desirable sinusoidal waveform. The carrier frequency of only 100 Hz is employed and hence switching loss is less compared to the 5000Hz employed in the multi-level inverters. In addition, the Multi-modular PWM inverter topology has the potentials of increasing current capacity, meeting harmonic standards by employing harmonic cancellation methods without the need of expensive filtering, and achieving a high frequency bandwidth.

modifjrlng the conventional bridge topology as shown in figure 17(a) and adding bidirectional switches, such as IGBT's, to the inverter Circuit. The DC voltage source is supplied by the 50Hz, lOOV constant DC battery energy storage. This inverter produces a 50Hz, lOOV peak At the end of each phase output, the transformer and filter is added to get the smooth sinusoidal waveform.

The output voltage waveform after going through the filtering circuit for the whole analysis is the same and is illustrated in figure 11and it is a smooth sinusoidal waveform. IV. THREE-PHASE "-LEVEL

INVERTERS

Three-phase multi-level inverter topology is based on the basic bridge-rectifier which is also an extension of singlephase multi-level inverter. To understand the operation of the three-phase inverter, please refer to figure 12.

Note from this three-phase design that for each phase there are only two gate switches compared to 4 gate switches that was utilized in the single-phase, two-level inverter design. Therefore, the amount of switches involved is reduced by half and hence reduce the switching losses. PWM switching technique is used and a triangular carrier frequency of 5000 Hz and modulating hquency of 50Hz is applied. Extending the basic switching principle from PWM technique, G2 is a compliment of G1 for phase A. Likewise, G4 is a compliment of G3 for pbase B and G6 is a compliment of G5 for phase C. Since the phases are 120 degrees apart from one another, the logic control for each phase is the same but 120 degree apart. Each triangular carrier signal is set to produce voltage magnitude of -1 to 1 in per unit level.

From the above picture, for instance, if the magnetic field is to spin in the counter-clockwise direction, phase C is positive, the coil next to it is therefore negative i.e. phase B. The remaining phase, which is phase A then needs to be connected to the positive bus. In the next cycle, phase C then switched to negative while the remaining phases are positive. This phenomenon is then repeated with two phases connected to positive and one phase connected to negative at any instant. The control circuitq of this inverter is relatively simple and easy to design but at low speeds, the motor will run with more noise as the ripple exposed to each winding is high resulting in increased torque pulsations and more noise. Therefore, multi-level inverters are taken into considemtion.

A. Three phase, 2-level inverter

The simplified circuit design for three-phase, two-level topology is illustrated in figure 13. It is constructed by

figure 14. The THD measured for phase A is 27.85%, phase B is 25.95% and phase C is 27.54%.

473

The circuit design for three-phase, three-level topology is

constructed by addmg another bridge inverter in series to the two-level inverter.

V. CONCLUSIONS

The following obiectives were achieved. The simulations of single-phase multi-level inverters, multi-module inverters and three-phase multi-level were done on EMTDC/PSCAD sohare. This three-phase, three-level inverter has configuration of Analysis in terms of total harmonic distortion was three accessible DC buses with nodes connected to the DC performed. l i n k capacitors as in single-phase inverter. From expression It was proved that as the levels of inverter increased, (3), the two DC-link capacitors are employed. This inverter system performance in terms of harmonics and more has a smaller fundamental component compared to the two desirable sinusoidal waveforms were achieved for both level due to the introduction of zero-reference voltage level. single-phase an three-phase inverters. For multi-module inverters, lower carrier frequency was Since the principle of multi-level topology synthesises a s t a i r employed and hence switching loss is reduced. case output voltage waveform fkom several levels of voltages, The less number of IGBT gate switches were employed a three-level inverter will produce two-levels of output for the three-phase system and hence switching loss is voltage with respect to zero reference level. The logic control redlld. for each phase is the same but 120 degree apart Triangular carrier signal 1 and 2 is set to produce voltage magnitude of VI. ACKNOWLEDGEMENTS 0 to 0.5 and 0.5 to 1 for positive half of the modulating signal. Whereas, triangular carrier signal 3 and 4 are set at 0 Authors would like to thank the School of Electrical and to 4 . 5 and 4 . 5 to -1 respectively. The output waveform of Computer Engineering, Curtin University of Technology for this 3-level inverter is illustrated in figure 15. The THD the facilities provided. measured for phase A is 21.95%, phase B is 16.95% and h a nthe 2-level inverter. phase C is 19.91% which is lesser t W. REFERENCES

EMTDCPSCAD Simulation Software Manuals, HVDC Research Centre, Winnipeg, Manitoba, Canada, 1994 release, Version 2.

B. Mokrytzki Pulse Width Modulated Inverters for AC motor Drives, IEEE Transactions On Industry And General Applications, Vol lGA-3, No.6, NovemeberlDecember,1967, Pp.493-503.

C. Newton and M.Suer, Neutral Point Control for Multi-level Invester theory, design and operational Limitations, IEEE Industry Applications Society, Annual meeting. New Orleans Louisiana, October 5-9, 1997, Pp. 1336-1343.

V.G. Agelidis, W.W. L Keerthipala and W.B. Lawerence, MultiModular Multi-lecel PWM Converter Systems, Nordic Workshop on Power and Industrial Electronics, Espoo, Finland, August 26-27,1998.

N. Mohan, T. M. Undeland and W. P. Robbins, Power Electronics: Converters, Applications and Design, 2 Edition, John Wiley & Sons, New York,1995.

In summary, as the number of inverter levels increases, more steps are added to the output and hence more desirable sinusoidal waveforms are achieved. In addition, the total harmonic distortion is reduced as the level increased. So far, the overall system performance is improved with lesser harmonics for three-phase system as well. The three-phase inverters are more widely used in applications such as induction motors.

Y. Slnivastava and S. Y. (Ron) Hui, Analysis of Random PWM switching Methods for Three-Level Power Converters, IEEE Traasactionson Power Electronics, VoL.14, No.6, November 1999, Pp. 1156-1163.

.M i , A New High -Power-Factor Three-phase C. A. Munoz and 1 AC-DC Converter: Analysis, Design, and Experimentation, IEEE T r a n s a c t i o n s on Power Electronics, Vol. 14, No.1, January 1999, Pp 90-96.

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