Class 03: Semiconductor Processing

Topics: 1. Introduction 2. Photolithography - Overview I 3. Photolithography - Overview II 4. Photolithography - Printing Techniques 5. Photolithography - Masks and Photoresist 6. Photolithography - Photoresist and Exposure 7. Photolithography - Limits of Printing 8. Photolithography - Sources of Light 9. Wafer Growth 10. Doping - Diffusion 11. Doping - Ion Implantation or II 12. Oxidation 13. Deposition 14. Etching
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Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Overview I (Jaeger p.14)
Overall steps in Photo process Impact of Clean Room Rating on Particle Size

Stepper

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Overview II (Runyan p.37; Mason)

Transfer desired pattern to an optical mask that is clear except where a pattern/shape is desired Cover the entire wafer surface with photoresist (~1m thick) Expose the wafer to light through the optical mask (takes ~ 1-5 seconds exposure) Use chemical processing to remove PR only where it has been exposed to light (the pattern is now transferred from the optical mask to the wafer surface) Subsequent process steps (e.g. oxidation, diffusion, deposition, etching). These will affect only the areas where there is no PR and be blocked where the PR remains. After all necessary processing through pattern, remove all PR in chemical process.

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Printing Techniques (Jaeger p. 25)
Contact Proximity Projection

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Masks and Photoresist (Jaeger p.15)

Positive photoresist

Cross section of mask shown in the diagrams to the left

Proximity printing shown, but not done today all projection printing

Final on-wafer layer

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Photoresist and Exposure (Runyan p.174, 178)
What is resist?A resist is a combination of a: (1) resin that can withstand the etch solution (2) sensitizer that is photosensitive (3) adhesion promoter to stick the solution to the layer (4) thinner to modify the viscosity Negative Resist-exposure to light makes resist more difficult to etch Positive Resist-exposure to light makes resist easier to etch Acid vs. Base : after exposure to light, positive resist become acidic, development in a base allows for removal of resist Clearing the Resist : this means the action of developing the resist and washing away the exposed (+ resist) areas Scumming : this occurs when the resist thickness and/or exposure time along with development does not sufficiently clear the resist

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Photolithography - Limits of Printing (Runyan c.5)
Contrast-difference in amount of light needed to clear the resist and the amount of light where an image just begins to form Resolution-minimum size feature that can be formed with the resist Numerical aperature: NA = n sin f (fundamental to lens) when image is formed at focal point of lens, then NA = 2 F = 2 (focal length/diameter) Projection printing resolution: Sr = 0.6 l / NA (aka Rayleigh limit)

Depth of focus: The amount of defocusing that can be tolerated across the shot (die) Depth of focus: d = wavelength / (2NA)2 This means that resolution is obtained at the expense of DOF As NA increases, smaller feature size (better resolution), but lower DOF

Resolution of feature in the X-Y plane vs. Spacing of features (near the diffraction limit)

Higher DOF (looser acrosswafer variation)

Lower DOF (tighter acrosswafer variation) Lower resolution (bigger feature size)
Joseph A. Elias, PhD

Higher resolution (smaller feature size)

Class 03: Semiconductor Processing

Photolithography - Sources of Light (Runyan c.5)
Source Hg Lamp Description G-line H-line I-line Wavelength (nm) 436 405 365 Feature size(um) 0.90 0.70, 0.50 0.35 Numerical Aperature Depth of Focus (um)

0.40, 0.48

2.3, 1.6

Excimers XeF XeCl KrF ArF F2

DUV DUV DUV DUV VDUV

351 308 249 193 157

0.35, 0.25 0.18, 0.15

0.35

1.0

Optical and UV Spectrum of High-Pressure Hg Lamp

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Wafer Growth (Runyan p.23, p.31; Mason) Methods - (1) Czochralski (CZ) (2) Horizontal Bridgman (3) Float Zone we will discuss only method #1 as it is the dominant production for Si

Create large ingots of semiconductor material by heating, twisting, and pulling. (~ 1-2 meters long by 100-300mm diameter) Entire ingot aligned to the same crystal lattice orientation (single-crystal). Remove all impurities all one element. Slice ingot into very thin (~400-750 m) discs called wafers. Some wafer are uniformly doped with specific impurities (e.g. Boron for p-type wafer with N A = 1014 cm-3 )

Joseph A. Elias, PhD

Class 03: Semiconductor Processing

Doping - Diffusion (Mason)
A masking layer (e.g. PR) is used to block the wafer surface except where the dopants are desired. The wafer is placed in a high-temperature furnace (~1000C) where the atmosphere contains the desired impurity in gaseous form. Through the process of diffusion, impurity atoms, which are in high concentration in the atmosphere, will diffuse into the substrate, where they have a low concentration (initially zero). After some time (~0.5 10 hours) the impurity atoms are uniformly distributed into the exposed wafer surface at a shallow depth (0.5 - 5 m) at a concentration that can be reliably controlled (~101 2 -101 9 cm- 3 ). Before Diffusion
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oxide

atoms/cm x, depth into wafer

n-type substrate (ND)

After Diffusion
3

oxide xj n-type substrate (ND) x

atoms/cm

Joseph A. Elias, PhD

10

Class 03: Semiconductor Processing

Doping - Ion Implantation or II (Mason, Martin p.39, Runyan p.486)
Implantation is functionally similar to diffusion, but here the atoms are shot into the wafer at high velocity (across a very strong electric field) and they embed themselves into the wafer surface. A short (~10min.) annealing step at elevated temperatures (~800C) is used to fit the new atoms into the substrate crystal lattice. Implantation is more uniform across the wafer than diffusion and allows for very precise control of where the impurities will be. In addition, its peak concentration can be beneath the wafer surface, and it does not required a long period of time at high temperature (which can be harmful). However, an implanted junction must remain near the surface of the wafer (~ 0.1 - 2 m) and cannot go as deep as a diffused junction. The impurity concentration profile (concentration vs. depth) is different for diffusion and implantation, however both are well known and predictable.

Joseph A. Elias, PhD

11

Class 03: Semiconductor Processing

Oxidation (Mason; Runyan c.3)

DRY oxidation

WET oxidation

When a Si wafer is exposed to O2 at high temperatures (~1000C) a native oxide is grown on the surface of the wafer. Because material (O 2 ) is being added to the wafer, the wafer grows in thickness, and ~ 50% of the oxide grows
beneath the surface and the other half on top of the (original) surface. Native oxide growth is used in MOS fabrication to grow the field oxide (the region outside of the active region) and to create the gate oxide layer, the thickness of which can be well controlled

Joseph A. Elias, PhD

12

Class 03: Semiconductor Processing

Deposition (Mason; Runyan p.124, 133)
Dielectrics: Offer a variety of dielectric materials including SiO 2 and SiN. Can be deposited on top of all other materials used in semiconductor fabrication. Can be deposited in thick layers (~1-2 m).
Polysilicon: Granular Si with similar material properties to single-crystal Si and SiO 2. Native thermal oxide, SiO 2 , can be grown on top of polysilicon. Can withstand subsequent high temperature steps (unlike metal) Can be doped to set resistance (low for interconnects, high for resistors) Used to form MOS gates, resistors, capacitors, and memory cells. Metals: Form low resistance interconnections. Can not withstand high temperature process steps. Many metal interconnect layers can be used which are insulated by deposited dielectrics.

CVD-Chemical Vapor Deposition

Sputter Deposition

Joseph A. Elias, PhD

13

Class 03: Semiconductor Processing

Etching (Mason; Runyan p.269, 281)
Chemical Etching: Selective etching of desired material. Can be masked by PR or oxide.
Isotropic etch will undercut masking layer Chemical-Mechanical (Reactive Ion Etching): Mechanical etching process with some chemical selectivity. Can be masked by PR or oxide. Anisotropic etch no undercut. Mechanical (Ion Milling): No material selectivity, must be blocked by thick mask. Anisotropic etch no undercut.

Joseph A. Elias, PhD

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