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Structural Modeling
Prof.S.Sivanantham School of Electronics Engineering VIT University Vellore, Tamilnadu. India E-mail: ssivanantham@vit.ac.in
Objectives
After completing this chapter, you will be able to: Describe what is the structural modeling Describe how to instantiate gate primitives Describe D ib how h to t model d l a design d i in i gate t primitives i iti Describe inertial and transport delays Describe how to specify delays in gates Describe hazards and their effects in gate networks
Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Structural Modeling
Structural style: Modeled as a set of interconnected components. Modules/UDPs - Modules/UDPs may or may not be synthesized. - A gate-level module is usually synthesizable. Gate primitives: There are 12 gate primitives. - Gate primitives are synthesizable. Switch primitives: There are 16 switch primitives. - They are usually used to model a new logic gate circuit at switch level. - They are not synthesizable, synthesizable in general. general
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Gate Primitives
and/or gates have h one scalar l output and d multiple l i l scalar l inputs i are used to realize the basic logic operations include and or xor nand nor xnor buf/not gates have one scalar input and one or multiple scalar outputs are used to realize the not operation, are used to buffer the output of an and/or gate, gate are used as controlled buffers include buf not bufif0 notif0 bufif1 notif1
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and/nand Gates
i1 i2
out
i1 i2
out
and 0 1 x z
i2 0 0 0 0 0 1 0 1 x x x 0 x x x z 0 x x x
nand 0 1 x z
i2 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x
i1
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or/nor Gates
i1 i2
out
i1 i2
out
or 0 1 x z
i2 0 0 1 x x 1 1 1 1 1 x x 1 x x z x 1 x x
nor 0 1 x z
i2 0 1 0 x x 1 0 0 0 0 x x 0 x x z x 0 x x
i1
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xor/xnor Gates
i1 i2
out
i1 i2
out
xor 0 1 x z
i2 0 0 1 x x 1 1 0 x x x x x x x z x x x x
xnor 0 1 x z
i2 0 1 0 x x 1 0 1 x x x x x x x z x x x x
i1 1
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buf/not Gates
in in 0 1 x z out 0 1 x x
out
in in 0 1 x z out 1 0 x x
out
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bufif0/notif0 Gates
in ctrl ctrl 1 x z z z z L H x x
out
in ctrl ctrl 1 x z z z z H L x x
out
bufif0 0 1 x z
0 0 1 x x
z L H x x
notif0 0 1 x z
0 1 0 x x
z H L x x
in n
in n
bufif1/notif1 Gates
in ctrl ctrl 1 x 0 1 x x L H x x
out
in ctrl ctrl 1 x 1 0 x x H L x x
out
bufif1 0 1 x z
0 z z z z
z L H x x
notif1 0 1 x z
0 z z z z
z H L x x
in
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instance_name is optional.
module basic_gates (x, y, z, f) ; input x, y, z; output f ; wire a, b, c; // internal nets // Structural modeling using basic gates. nor g1 (b, x, y); not g2 2 (a, ( x); ) and g3 (c, a, z); nor g4 (f, b, c); endmodule
x y z
g1 g2 a g3
b g4 c f
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Array of Instances
Array instantiations may be a synthesizer dependent! Suggestion: you had better to check this feature before using the synthesizer.
wire [3:0] out, in1, in2; // basic array instantiations of nand gate. nand n_gate[3:0] (out, in1, in2); // this is equivalent to the following: nand n_gate0 (out[0], in1[0], in2[0]); nand n_g gate1 (out[1], ( [ ], in1[1], [ ], in2[1]); [ ]); nand n_gate2 (out[2], in1[2], in2[2]); nand n_gate3 (out[3], in1[3], in2[3]);
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s1 s c1 c2 c3
c_out
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module mux4_to_1_structural (i0, i1, i2, i3, s1, s0, out); i3 input i0, i1, i2, i3, s1, s0; output out; wire s1n, s0n; // Internal wire declarations wire y0, y1, y2, y3; s1 // Gate instantiations not (s1n, s1); // Create s1n and s0n signals. not (s0n, s0); and (y0, i0, s1n, s0n); // 3-input and gates instantiated and d (y1, ( 1 i1 i1, s1n, 1 s0); 0) and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or ( (out, ,y y0, ,y y1, ,y y2, ,y y3); ); // 4-input p or g gate instantiated endmodule
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c g d i e h f op ep
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x f y S
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triand/ wand 0 1 x z
0 0 0 0 0
1 0 1 x 1
x 0 x x x
z 0 1 x z
trior/ wor 0 1 x z
0 0 1 x 0
1 1 1 1 1
x x 1 x x
z 0 1 x z
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VDD
RL
f
w Q2n Q1n Q2n Q1n
Representing Hierarchy
fulladd n_sum U1 halfadd U2 halfadd n carry1 n_carry1 n_carry2 U3 carry
Create hierarchy by Instantiating module(s) Connecting module ports to local port, net or variable
a b
sum
Y You must d declare l most local l l cin objects before you use them
module fulladd (input a, b, cin, output sum, carry); wire n_sum, n_carry1, n_carry2; halfadd U1(.a(a), .b(b), .sum(n_sum), .carry(n_carry1)); halfadd U2(.a(n_sum), .b(cin), .sum(sum), .carry(n y _carry2)); y or U3(carry, n_carry2, n_carry1); endmodule
Built-in OR primitive
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12
fulladd instance
a b sum U1 halfadd b carry a n_sum n_carry1
module fulladd (input a, b, cin, output sum, carry); wire n_sum, n_carry1, n_carry2; halfadd U1(a, b, n_sum, n_carry1); h lf dd U2(n_sum, halfadd U2( cin, i sum, n_carry2); 2) or U3(carry, n_carry2, n_carry1); wire n_carry1 of module endmodule fulladd mapped to output carry of instance U1 of module halfadd module halfadd (a, b, sum, carry); input a, b; output sum, carry; assign g sum = a ^ b; assign carry = a & b; endmodule ECE301 VLSI System Design FALL 2011 a b
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sum halfadd carry
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x y
f
y
10 12 14 16 18 20
2 b
10 12 14 16 18 20
wire a; and #4 (b, x, y); // Inertial delay and #4 (a, x, y); not #1 (f, a);
Inertial delay
2 a 2 f 2
10 12 14 16 18 20
10 12 14 16 18 20
10 12 14 16 18 20
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x y
f
x 2 y 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20
wire #2 a; // Transport delay and #4 (b, x, y); // Inertial delay and #4 (a, x, y); not #1 (f, (f a);
Inertial delay Transport delay
b 2 a 2 f 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20
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// Only specify one delay and #(5) a1 (b, x, y); // Only specify one delay using min:typ:max not #(10:12:15) n1 (a, x); // Specify two delays using min:typ:max and #(10:12:15, 12:15:20) a2 (c, a, z); // Specify three delays using min:typ:max or #(10:12:15, 12:15:20, 12:13:16) o2 (f, b, c);
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(b)static-0 hazard
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module hazard_static (x, y, z, f); input x, y, z; output f; // internal declaration wire a, b, c; // internal net // logic circuit body and #5 a1 (a, (a x, x y); not #5 n1 (c, x); and #5 a2 (b, c, z); or #5 o2 (f, b, a); endmodule
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t pd t pd
t pd t pd d
a b f
t pd t pd t pd
t pd
t pd t pd
t pd
Hazard
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x=y=z=1 w a b c d e f
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// dynamic hazard example module hazard_dynamic(w, x, y, z, f); input w, x, y, z; output f; // internal declaration wire a, b, c, d, e; // internal net // logic circuit body nand #5 nand1 (b, x, w); not #5 n1 (a, w); nand #5 nand2 (c, a, y); nand #5 nand3 (d, b, c); nand #5 nand4 (e, w, z); nand #5 nand5 (f, d, e); endmodule
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