NAR-2200 Series Communications Appliance

User s Manual
Revision: 1.00

Portwell Inc.
3F, No. 92, Sec. 1, Nei-Hu Rd., Taipei 114, Taiwan, R.O.C. Headquarter: +886-2-2799-2020 FAX: +886-2-2799-1010 http://www.portwell.com.tw EMAIL: INFO@MAIL.PORTWELL.COM.TW

Table of Contents
Chapter 1
1.1 1.2 1.3

Introduction ..................................................................................................2
About This Manual...................................................................................................2 Manual Organization................................................................................................2 Technical Support Information .................................................................................2

Chapter 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12

Get Started....................................................................................................3
Included Hardware ..................................................................................................3 Before You Begin ....................................................................................................3 The Chassis ............................................................................................................4 Open the Chassis .................................................................... ! Install or Remove a SODIMM .................................................. ! Remove and Install Battery...................................................... ! Install Compact Flash .............................................................. ! I n s t a l l 3 . 5 H a r dd i s k ................................................................ ! Product Specifications .............................................................................................8 Hardware Configuration Setting ...............................................................................9 Use a Client Computer ..........................................................................................14 BIOS Setup Information.........................................................................................15

Chapter 3
3.1 3.2

Operation Guide .........................................................................................22

Brief Guide of PPAP-2200 .....................................................................................22 System Architecture............................................................................................... 22

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Chapter 1 Introduction

1.1

About This Manual

This manual describes all required information for setting up and using the NAR-2200 All mentioned below applies to the whole system, unless specially stated. NAR-2200 provides the essential components for delivering optimal performance and functionality in the value communications appliance market segment. This manual should familiarize you with NAR-2200 operations and functions. NAR-2200 family has one, Five or Six on-board Ethernet ports to serve communication appliances, such as Firewall, which needs more Ethernet ports to connect external network (internet), demilitarized zone and internal network. NAR-2200 features:
Versatile networking One COM ports

and I/O capabilities: 1, 5 or 6 Ethernet ports

1.2

Manual Organization

The manual describes how to configure your NAR-2200 system to meet various operating requirements. It is divided into three chapters, with each chapter addressing a basic concept and operation of this whole system.
Chapter 1: Introduction. This section briefly talks about how this document is organized. It includes some guidelines for users who do not want to read through everything, but still helps you find what you need. Hardware Configuration Setting and Installation. This chapter shows how the hardware is put together, including detailed information. It shows the definitions and locations of Jumpers and Connectors that you can easily configure your system. Descriptions on how to properly mount the main memory are also included to help you get a safe installation. Reading this chapter will teach you how to set up NAR-2200. Operation Information. This section gives you illustrations and more information on the system architecture and how its performance can be maximized.

Chapter 2:

Chapter 3:

Any updates to this manual, technical clarification and answers to frequently asked questions would be posted on the web site: http://isc.portwell.com.tw

1.3

Technical Support Information

Users may find helpful tips or related information on Portwell's web site: http://www.portwell.com.tw. A direct contact to Portwell's technical person is also available. For further support, users may also contact P o r t w e l l s headquarter in Taipei or your local distributors. Taipei Office Phone Number: +886-2-27992020

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Chapter 2 Get Started

This section describes how the hardware installation and system settings should be done.

2.1
PPAP-2200 Communication One null serial port cable.

Included Hardware

The following hardware is included in your kit:

Appliance System Board.

2.2

Before You Begin

To prevent damage to any system board, it is important to handle it with care. The following measures are generally sufficient to protect your equipment from static electricity discharge: When handling the board, uses a grounded wrist strap designed for static discharge elimination and touches a grounded metal object before removing the board from the antistatic bag. Handle the board by its edges only; do not touch its components, peripheral chips, memory modules or gold contacts. When handling memory modules, avoid touching their pins or golden edge fingers. Put the value communications appliance system board and peripherals back into the antistatic bag when they are not in use or not installed in the chassis. Some circuitry on the system board can continue operating even though the power is switched off. Under no circumstances should the Lithium coin cell be used to power the real-time clock be allowed to be shorted. The coin cell can heat under these conditions and present a burn hazard. WARNING!
1. "CAUTION: Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer. Discard used batteries according to the ma n u f a c t u r e r s i n s t r u c t i o n s " 2. This guide is for technically qualified personnel who have experience installing and configuring system boards. Disconnect the system board power supply from its power source before you connect/disconnect cables or install/remove any system board components. Failure to do this can result in personnel injury or equipment damage. 3. Avoid short-circuiting the lithium battery; this can cause it to superheat and cause burns if touched. 4. Do not operate the processor without a thermal solution. Damage to the processor can occur in seconds. 5. Do not block air vents. Minimum 1/2-inch for clearance required.

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2.3

The Chassis

The system is integrated in a customized chassis (Fig. 2-1, Fig. 2-2). On the front panel you will find the Power LED, Hard Disk LED and LAN LED. The back panel has Six LAN ports and a COM port.

Fig. 2-1 Front view of the Chassis

Fig. 2-2 Back view of the Chassis

2.4

Open the Chassis

1. Take off the four screws (three at the rear side and two at the right/left side and remove the top lead (Fig. 2-3).

Fig. 2-3 Take off two screws

2. The top lead (Fig. 2-4) can be removed from the base stand (Fig. 2-5).

Fig. 2-4 The top lead

Fig. 2-5 The base stand

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2.5

Install or Remove a SODIMM

Follow these steps to upgrade or remove RAM module: 3. I n s t a l l t h es y s t e m me mo r yb yp u l l i n gt h es o c k e t sa r ma n dp r e s s i n gi t i n t ot h es l o t g e n t l y . (Fig. 2-6, 2-7)

Fig. 2-6 The memory slot

Fig. 2-7 Install SODIMM

4. By pulling the arms, the SODIMM can eject itself (Fig. 2-8).

Fig. 2-8 Eject a SODIMM module

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2.6 Remove and Install Battery

5. Press the metal clip back to eject the button battery (Fig. 2-9). 6. Replace it with a new one by pressing the battery with fingertip to restore the battery (Fig. 2-10).

Fig. 2-9 Eject the battery

Fig. 2-10 Restore the battery

2.7

Install Compact Flash

The system has an internal drive bay for one Compact Flash card drive. If the CF is not preinstalled, you can install it by yourself. Follow the steps below to install the CF: 7. Fasten the five screws to lock bracket together (Fig. 2-11a, 2-11b).

Fig. 2-11a Remove L type base under button case

Fig. 2-11b Push CF into the bracket

8. Completion CF to the System Chassis (Fig. 2-12)

Fig. 2-12 completion CF in system NAR-2 2 0 0U s e r s Manual

Fix all screws back (Fig. 2-13). 6

2.8

I n s t a l l 3 . 5 Hard disk

The system has an internal drive bay for one 3.5" hard disk drive. If the HDD is not pre-installed, you can install by yourself. You need the parts from the accessory-bag as shown on Figure 2-14. They are one HDD-bracket, several screws. (from left to right).

(Fig. 2-14)3.5 HDD kit

(Fig. 2-15) Fix the hard disk drive on the HDD bracket with four screws. Plug the IDE cable into hard disk drive connector

(Fig. 2-16) Completion HDD with bracket and fixed screws.

(Fig. 2-17) Finished.

9. Connect Power Cable and IDE Cable before assemble hard disk. After assemble hard disk, put IDE Cable and Power cable into main board.

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2.9
Model: Main Processor:

Product Specifications

NAR-2200
NAR-2200-601: IntelR 915GME platform w/ Celeron-M/Pentium-M socket type CPU desktop platform. NAR-2200-621: Intel 915GME platform w/ ULV Celeron-M BGA 600MHz CPU desktop platform.

BIOS: Main Memory: Chipset: SATA Interface VGA PCI IDE Interface: Serial Ports: USB Interface: Auxiliary I/O Interfaces:

Award system BIOS with 512KB flash ROM to support DMI, PnP, APM function Two 200-pin SODIMM socket supports DDRII. DDR2 400/533, up to 2GB. North Bridge: IntelR 915GME South Bridge: ICH6-M 2 Serial ATA ports supported. One 2x5 Pin pin-header for internal VGA interface is required. One 40 Pin for DMA/33/66/100 IDE Storage Support two high-speed 16550 compatible UARTs with 16-byte T/R FIFOs Support two USB 2.0 ports for high speed I/O peripheral devices System reset switch, power okay LED, Ethernet activity LED, Ethernet speed LED, general purpose LED, alert LED, Bypass LED and HDD LED interface Support one AC Adaptor with Adaptor input (power requirement: Input: 100-240V, Output: 12V == 7A) FSP084-1ADC11, FSP Power Supply (AC-DC) Adapter. Black. Maximal 6 Ethernet interfaces with RJ45 connector to be built onboard. Ethernet controller: The two PCI interfaces should be co-layout with R R Intel 82541PI (GbE) and Intel 82551ER (FE). NAR-2200-601 is PGA with Four 82573L GbE ports (four ports from left side) + Two 82551ER FE. NAR-2200-621 is BGA with Four 82573L GbE ports (four ports from left side) + Two 82551ER FE.
Full configuration
Eth-0 Eth-1 Eth-2 Eth-3 Eth-4 Eth-5 Console USB

Power Input:

On-board Ethernet:

PXE port Bypass Segment

Hardware Monitor: Environmental Requirements: Dimension:

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Support on-board hardware monitor for CPU fan, System fan ,System voltages Operating Temperature: 5C ~ 40C Storage Temperature: 0C ~ 70C Relative Humidity: 5% 95%, non-condensing 214mm(L) x 225mm (W) x 52mm (H) 8

2.10 Hardware Configuration Setting

This section gives the definitions and shows the positions of jumpers, headers and connectors. All of the configuration jumpers on PPAP-2200 are in the proper position. The default settings set by factory are marked with a star ( ).

Jumpers
In general, jumpers on PPAP-2200 system board are used to select options for certain features. Some of the jumpers are configurable for system enhancement. The others are for testing purpose only and should not be altered. To select any option, cover the jumper cap over (Short) or remove (NC) it from the jumper pins according to the following i n s t r u c t i o n s . H e r eN Cs t a n d s f o r N o t C o n n e c t e d .

P PAP-2200 Jumper Table

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PPAP-2200 ZR0 jumper setting: (default setting)

JP2: CMOS Clear JP2 Function 1-2 Short Normal Operation 2-3 Short Clear CMOS Contents JP4: FSB Frequency selection JP4 Function 1-2 short CPU FSB frequency=400MHz 2-3 short CPU FSB frequency=533MHz Note: The DDR2 frequency is followed the CPU FSB frequency. For example, the DDR2 module populated is DDR2 533, the CPU must be 533MHz FSB. Please use same frequency of memory module and CPU. Neither CPU/DDR=533/400 nor 400/533 are allowed. This is the limitation of 915GM chipset.

CPU VCCA voltage input (JP5B) JP5B Function 2-4 short VCCA=1.8V (Banias) 4-6 short VCCA=1.5V ( Dothan) N o t e : w r o n gv o l t a g es e l e c t i o nma y d a ma g et h eC P U . P l e a s es u r v e y t h eC P U s t y p eb e f o r e setup this jumper setting. PCI-E x16 graphic port enable/disable (JP5C) JP5C 7-8 short 7-8 open Function Reserved PCI-E x16 graphic port enabled

DDR2 memory frequency selection (JP5D) JP5D Function 9-10 open reserved 11-12 open 9-10 open The memory module is DDR2 400 11-12 short 9-10 short The memory module is DDR2 533 11-12 open 9-10 short reserved 11-12 short J15: Reset to default function J15 1-2 Short 1-2 Open Function RESET TO DEFAULT Normal mode

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Connector Setting Connector J1~J6 J7 J8 J9 J10 J11 J12J13 J14 J15 J16 J17
J18

Function LAN LED HDD LED +Power LED TV out connector PS/2 Keyboard & Mouse Connector CPU FAN connector IDE connector SATA connector +5V & +12V power connector(only output) RESET TO DEFAULT CPLD Programming connector 8-bit GPO LED connector
External thermal sensor connector

Remark

J19 J20 J22 J23 J24~J29 J30 J31 J32 J33 CN2 CN4 JP3

PCI Connector PCI-E Connector COM2 connector POWER S/W RJ45 connector USB connector POWER JACK connector SYS FAN connector CF Connector VGA connector COM1 connector By-pass LED

J9: PS/2 Keyboard & Mouse Connector PIN No. 1 3 5 7 Signal Description Keyboard data KB/MS ground Keyboard clock NC (key) PIN No. 2 4 6 8 Signal Description Mouse data KB/MS VCC (+5V) Mouse clock NC (key)

J17: 8-bit GPIO connector define

Pin 1 3 5 7 9

Signal Name GPIO GPIO GPIO GPIO Ground

Pin 2 4 6 8 10

Signal Name GPIO GPIO GPIO GPIO +5V

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J7: HDD LED +Power LED connector define

Pin 1 3

Signal Name +5V +5V

Pin 2 4

Signal Name -HD -PWR

CN2: VGA connector define

Pin 1 3 5 7 9

Signal Name RED GREEN BLUE HSYNC VSYNC

Pin 2 4 6 8 10

Signal Name DDCCLK Ground DDCDATA Ground N/C

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2.11 Use a Client Computer

Connection Using Hyper Terminal
If users use a headless NAR-2200, which has no mouse/keyboard and VGA output connected to it, the console may be used to communicate with NAR-2200. To access NAR-2200 via the console, Hyper Terminal is one of the choices. Follow the steps below for the setup:
1. Execute HyperTerminal under C:\Program Files\Accessories\HyperTerminal 2. Enter a name to create new dial

3. For the connection settings, make it Direct to COM1.

4. Please make the port settings to Baud rate 19200, Parity None, Data bits 8, Stop bits 1

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5. Turn on the power of NAR-2200, after following screen was shown

6. Users can then see the boot up information of NAR-2200

When me s s a g e H i t <DEL> if users want to run Setup a p p e a r d u r i n gP O S T , after turning on or rebooting the computer, press <Tab> key immediately to enter BIOS setup program.
7. This is the end of this section. If the terminal did not port correctly, please check the previous steps.

2.12 BIOS Setup Information

NAR-2200 is equipped with the Award BIOS within Flash ROM. The BIOS has a built-in setup program that allows users to modify the basic system configuration easily. This type of information is stored in CMOS RAM so that it still retains during power-off periods. When system is turned on, NAR-2200 communicates with peripheral devices and checks its hardware resources against the configuration information stored in the CMOS memory. Whenever an error is detected, or the CMOS parameters need to be initially defined, the diagnostic program will prompt the user to enter the Setup program. Some errors are significant enough to abort the start-up.

Entering Setup
When users see the me s s a g e H i t < D E L >i f users want to run Setup , after turning on or rebooting the computer, press <Del> key immediately to enter BIOS setup program. If users want to enter Setup but fail to respond before the message disappears, please restart the system either by first turning it off and followed by turning it on (COLD START) or simply press t h e" R E S E T " b u t t o n . WA R MS T A R T (press <Ctrl>, <Alt>, and <Delete> keys simultaneously) will do, too. Unless users press the keys at the right time, the system will not boot, an error message will display and users will be asked to do it again. When no setting is stored in BIOS or the setting is missing, a message Press <F1> to run Setup will appear. Then press <F1> to run Setup or resume HIFLEX BIOS Setup. users can use the keyboard to choose among options or modify the system parameters to match the options with your system. The table shown on next page will show all of keystroke functions in BIOS Setup.
Keys to navigate within Setup menu
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Key Up () Down () Left () Right () Enter PgUp PgDn

Move to the previous item Move to the next item

Function

Move to the item on the left (menu bar) Move to the item on the right (menu bar) Enter the item you desired Increase the numeric value or make changes Decrease the numeric value or make changes Increase the numeric value or make changes Decrease the numeric value or make changes Main Menu: Quit and not save changes into CMOS Status Page Setup Menu and Option Page Setup Menu: Exit current page and return to Main Menu General help on SETUP navigation keys Load previous values from CMOS Load the fail-safe defaults from BIOS default table Load the optimized defaults Save all the CMOS changes and exit

Esc F1 F5 F6 F7 F10

Main Menu
Once users enter NAR-2200 Award BIOS CMOS Setup utility, should start with the Main Menu. The Main Menu allows user to select from eleven setup functions and two exit choices. Use arrow keys to switch among items and press <Enter> to accept or bring up the sub-menu.
Phoenix Award BIOS CMOS Setup Utility

NOTE: It is strongly recommended to reload the optimized default setting if CMOS is lost or BIOS is updated. NAR-2 2 0 0U s e r s Manual 16

Standard CMOS Setup Menu

This setup page includes all the items within standard compatible BIOS. Use the arrow keys to highlight the item and then use the <PgUp>/<PgDn> or <+>/<-> keys to select the value or number in each item and press <Enter> to certify it. Follow command keys in CMOS Setup table to change Date, Time, Drive type and Boot Sector Virus Protection Status.
Screen Shot: Phoenix Award BIOS CMOS Setup Utility

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Menu Selections Item Date Time Options

mm:dd:yy hh:mm:ss EGA/VGA CGA 40 CGA 80 MONO

Description
Set the system date. Note that the 'Day' automatically changes when set the date Set the system time

Video

Select the default video device

Base Memory Extended Memory Total Memory

N/A N/A N/A

Display the amount of conventional memory detected during boot up Display the amount of extended memory detected during boot-up Display the total memory available in the system

Advance BIOS Features

This section allows user to configure system for basic operation. Users will be able to s e l e c t t h es y s t e m s d e f a u l t s p e e d , b o o t -up sequence, keyboard operation, shadowing and security.
Screen Shot: Phoenix Award BIOS CMOS Setup Utility

Internal Cache/External Cache

These two categories speed up memory access. However, it depends on CPU/chipset
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design.
Enabled Disabled
Enable cache Disable cache

Quick Power On Self Test

This category speeds up Power On Self Test (POST) after power up the computer. If it is set to Enable, BIOS will shorten or skip some check items during POST.
Enabled Disabled
Enable quick POST Normal POST

Boot Up NumLock Status

Select power on state for NumLock. The choice: Enabled/Disabled.

Gate A20 Option

This entry allows user to select how the gate A20 is handled. The gate A20 is a device used to address memory over 1 Mbytes. Originally, the gate A20 was handled via a pin on the keyboard. But now, though keyboards still provide this support, it is more common, and much faster, for the system chipset to provide support for gate A20.
Normal Fast
Keyboard Chipset

Typematic Rate Setting

Keystrokes repeat at a rate determined by the keyboard controller. When enabled, the typematic rate and typematic delay can be selected. The choice: Enabled/Disabled.

Typematic Rate (Chars/Sec)

Set the how many number of times a second to repeat a keystroke when a key is holding down. The choice: 6, 8, 10, 12, 15, 20, 24 and 30.

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Typematic Delay (Msec)

Set the delay time after the key is held down before it begins to repeat the keystroke. The choice: 250, 500, 750 and 1000.

Security Option
Select whether the password is required every time the system boots or only when enter setup.
System Setup
The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt. The system will boot and access to Setup will be denied if the correct password is not entered at the prompt.

Note: To disable security, select PASSWORD SETTING at Main Menu and then user will be asked to enter password. Do not type anything and simply press <Enter>, it will disable security. Once the security is disabled, the system will boot up and user can enter Setup freely.

OS Select for DRAM > 64MB

Select the operating system that is running with more than 64MB of RAM on the system. The choice: Non-OS2, OS2.

Console Redirection
Set the UNIX Console redirect to the terminal from COM1. The choice: Enabled/Disabled.

Baud Rate
Set the RS-232 baud rate speed. The choice: 9600, 19200, 38400, 57600 and 115200.

Advanced Chipset Features

This section allows user to configure system for AT clock, DRAM timings...

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Integrated Peripherals

Onboard LAN BootROM

User can press L for boot from LAN.

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Chapter 3 Operation Guide

3.1

Brief Guide of PPAP-2200

PPAP-2200 is a Communication Appliance computing board based on Intel 915GV chipset technology. PPAP-2200 has SIX on-board LAN ports to serve communication appliances, such as Firewall, which needs SIX Ethernet ports to connect external network (internet), demilitarized zone and internal network. Different I/O management policies can be applied respectively to individual network to achieve the highest security level. The target market segment is communication appliance including Virtual Private Network, Load Balancing, Quality of Service, Intrusion Detection, Virus Detection, Firewall and Voice Over IP. This PPAP-2200 system board is eligible with INTEL processor package (INTEL Celeron M) and two slot for DDR2RAM module. The enhanced on-board PCI IDE interface supports 1 drive up to PIO mode 4 timing and Ultra DMA/100 synchronous mode, SATA I feature. The on-board super I/O chipset integrates two serial ports driven by two high performance 16550C-compatible UARTs to provide 16-byte send/receive FIFOs. The two Universal Serial Bus ports provide highspeed data communication between peripherals and PC. The on-board flash ROM is used to make the BIOS update easier. The high precision Real Time Clock/Calendar is built to support Y2K for accurate scheduling and storing configuration information. All of these features make PPAP-2200 excellent in stand-alone applications. If any of these items is damaged or missing, please contact your vendor and save all packing materials for future replacement and maintenance. Figure 3-1 PPAP-2200 Board

3.2

System Architecture

The following illustration of block diagram will show how PPAP-2200 gives a highly integrated system solution. The most up-to-date system architecture of PPAP-2200 includes two main chips. It contains INTEL 915GM and ICH-6 M to support INTEL Celeron -M processor, DDR2 SODIMM, USB 2.0 port, communication, Ultra DMA/100 IDE Master storage, SATA I storage. The on-board super ICH6-M supports two UARTs and hardware monitoring. PPAP-2200 has built-in onboard INTEL celeron-M processor EBGA package 400MHz system bus for cost-effective and high performance application. The INTEL 915GM provides a completely integrated solution for the system controller and data path components in a INTEL mobile processor system. The INTEL 82801DBM I/O Controller Hub mobile (ICH6-M) provides a highly integrated multifunction for the best industry applications. It supports up to for Ultra ATA/33/66/100 IDE master interface, SATA I interface. Universal Serial Bus (USB2.0) controllers,

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All detailed operating relations are shown in Fig. 3-2 (PPAP-2200 System Block Diagram).

PPAP-2200VL-4201 Block Diagram

Intel -M/ Intel Celeron Celeron-M/ Pentium -M Pentium-M 40-pin IDE connector IDE CF Socket FSB: 400/533 MHz

DDR2 400/533 DDR2 400/533 DDR2 DDR2400/533 400/533

on Module (Crypto card)

SATA-1 SATA-2

82915GME MCH
DMI (1GB/s) in each direction

on Module in R/M

Add PCI

PCI Vertical slot

PCI -E x4 golden finger

E x4 PCI Add

82801FBM ICH6-M
BIOS/Firmware 4 PCI -E x1 2 PCI

PCI -E GbE -0
(82573L)

PCI -E GbE -1
(82573L)

PCI -E GbE -2
(82573L)

PCI -E GbE -3
(82573L)

PCI GbE -0
(82551ER )

PCI GbE -1
(82551ER )

USB -pin ------------Dual USB

RJ45 System Console

Bypass 0

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

Figure 3-2

PPAP-2200 Block Diagram

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Chapter 4

Programming guide

4.1

GPIO Sample Code

// Portwell Confidential ! // Portwell Intellectual Property, All rights reserved. // //////////////////////////////////////////////////////////////////////////////// // // Program : 3727GPIO.CPP // Descript. : PPAP-3727 GPIO test program // Designer : Frank Hsu // Language : Borland C++ 5.02 // O.S. : MS-DOS/Win98 only // Upddate : 11222006 Release // // //////////////////////////////////////////////////////////////////////////////// // // // GPIO on PPAP-3727 // PPAP-3727 J30_Pin1=GPIO1:from SUPER I/O_GPIO17 // J30_Pin2=GPIO2:from SUPER I/O_GPIO16 // J30_Pin3=GPIO3:from SUPER I/O_GPIO15 // J30_Pin4=GPIO4:from SUPER I/O_GPIO14 // J30_Pin6=GPIO5:from SUPER I/O_GPIO10 // J30_Pin7=GPIO6:from SUPER I/O_GPIO11 // J30_Pin8=GPIO7:from SUPER I/O_GPIO12 // J30_Pin9=GPIO8:from SUPER I/O_GPIO13 // <<<<< Be careful Pin5=GND , Pin10=VCC >>>>> // // Programming Guide : // Step1 : CR29_Bit[7..6]P[0,1] to select GPIO10~17 pin // Step2 : LD7_CR07h_P[07h] : point to LD7 // Step3 : LD7_CR30h_bit0_P1 : Enable LD7 // Step4 : Start 4 test items ( t1 , t2, t3, t4 ) // LD7_CRF0h definition : GPIO17 ~ 10 : 1 = input , 0 = output pin // LD7_CRF2h_P[00h] : Always let CRF1 ( GPIO data port ) non-invert. // LD7_CRF1h : GPIO17~10 data port , // t1 : GPO17,16,15,14 output [1,1,1,1] to GPI10,11,12,13 // t2 : GPO17,16,15,14 output [0,0,0,0] to GPI10,11,12,13 // t3 : GPO10,11,12,13 output [1,1,1,1] to GPI17,16,15,14 // t4 : GPO10,11,12,13 output [0,0,0,0] to GPI17,16,15,14 // #include "stdlib.h" #include "conio.h" #include "stdio.h" #include "dos.h"

// for delay(), and sleep()

// Global constant --------- Start -------------#define config_W83627 0x2E // Hardware strapping #define GPIO1_LDN 0x07 // W83627 GPIO1 LDN = 0x07 for GP10~17 #define CR07 0x07 #define CR29 0x29 #define CR30 0x30 #define CRF0 0xF0 #define CRF1 0xF1 #define CRF2 0xF2 #define portb 0x61 #define refresh_status 0x10 NAR-2 2 0 0U s e r s Manual 24

void fixdelay_15us () { // delay 15 us unsigned char char_ah,char_al ; char_ah = inportb ( portb ) & refresh_status ; fixdelay_loop : char_al = inportb ( portb ) & refresh_status ; if(char_ah == char_al ) goto fixdelay_loop ; } // end of fixdelay_15us

main() { unsigned char al_char ; printf("\n\n PORTWELL PPAP-3727 GPIO,3727GPIO.exe, V1.00 11-22-2006,All rights reserved.\n\n");

printf("\n PPAP-3727 J30_Pin1=GPIO1:from SuperIO_GPIO17 "); printf("\n J30_Pin2=GPIO2:from SuperIO_GPIO16 "); printf("\n J30_Pin3=GPIO3:from SuperIO_GPIO15 "); printf("\n J30_Pin4=GPIO4:from SuperIO_GPIO14 "); printf("\n J30_Pin6=GPIO5:from SuperIO_GPIO10 "); printf("\n J30_Pin7=GPIO6:from SuperIO_GPIO11 "); printf("\n J30_Pin8=GPIO7:from SuperIO_GPIO12 "); printf("\n J30_Pin9=GPIO8:from SuperIO_GPIO13 "); printf("\n\n Put 4 jumper cap on J20 pin header pin1-6, 2-7, 3-8,4-9.\n"); printf("\n\n Be careful !!! J30 pin5 (GND), and pin10 (Vcc) can not be shorted\n"); printf("\n\n Ready ? If yes , then Press any key to start test ......."); getche() ; // W83627THG Super IO GP10~13 , 23~26 are used for PPAP-3719 GPIO // GP10~13 located at LD7 , GP23~26 located at LD8 // ***** First : define the Multiplexed pins --- start outportb ( config_W83627 , 0x87 ) ; // enter config mode outportb ( config_W83627 , 0x87 ) ; fixdelay_15us(); // CR29Bit[7,6]_P[01] , Define the multiplexed pin,GPIO10~17 outportb ( config_W83627 , CR29 ) ; al_char = ( inportb ( config_W83627 +1 ) & 0x7D ) | 0x40 ; outportb ( config_W83627 , CR29 ) ; outportb ( config_W83627+1 , al_char ) ;

// Enable GPIO1 and GPIO2 and Set Non-inverse outportb ( config_W83627 , CR07 ) ; outportb ( config_W83627+1 , GPIO1_LDN ) ; outportb ( config_W83627 , CR30 ) ; al_char = inportb ( config_W83627 +1 ) | 0x01 ; outportb ( config_W83627 , CR30 ) ; outportb ( config_W83627+1 , al_char ) ; outportb ( config_W83627 , CRF2 ) ; outportb ( config_W83627+1 , 0x00 ) ; //LD8---------------------------------------------------

/* NAR-2 2 0 0U s e r s Manual 25

Testing way : Use PPAP-3719 GPIO ( 8 bi-direction pins from Super IO W83627THG ) Initialization for W83627THG must be done first in Main(). --- t1 SGPO17 Write 0 to SGPI10 , SGPI10 = 0 ? ,if yes, pass ; if no, failed SGPO16 Write 0 to SGPI11 , SGPI11 = 0 ? ,if yes, pass ; if no, failed SGPO15 Write 0 to SGPI12 , SGPI12 = 0 ? ,if yes, pass ; if no, failed SGPO14 Write 0 to SGPI13 , SGPI13 = 0 ? ,if yes, pass ; if no, failed --- t2 SGPO17 Write 1 to SGPI10 , SGPI10 = 1 ? ,if yes, pass ; if no, failed SGPO16 Write 1 to SGPI11 , SGPI10 = 1 ? ,if yes, pass ; if no, failed SGPO15 Write 1 to SGPI12 , SGPI10 = 1 ? ,if yes, pass ; if no, failed SGPO14 Write 1 to SGPI13 , SGPI10 = 1 ? ,if yes, pass ; if no, failed --- t3 SGPO10 Write 0 to SGPI17 , SGPI26 = 0 ? ,if yes, pass ; if no, failed SGPO11 Write 0 to SGPI16 , SGPI25 = 0 ? ,if yes, pass ; if no, failed SGPO12 Write 0 to SGPI15 , SGPI24 = 0 ? ,if yes, pass ; if no, failed SGPO13 Write 0 to SGPI14 , SGPI23 = 0 ? ,if yes, pass ; if no, failed --- t4 SGPO10 Write 1 to SGPI17 , SGPI26 = 1 ? ,if yes, pass ; if no, failed SGPO11 Write 1 to SGPI16 , SGPI25 = 1 ? ,if yes, pass ; if no, failed SGPO12 Write 1 to SGPI15 , SGPI24 = 1 ? ,if yes, pass ; if no, failed SGPO13 Write 1 to SGPI14 , SGPI23 = 1 ? ,if yes, pass ; if no, failed */

// GPIO Direction setting for t1 and t2 test items ============== outportb ( config_W83627 , CR07 ) ; outportb ( config_W83627+1 , GPIO1_LDN ) ; outportb ( config_W83627 , CRF0 ) ; outportb ( config_W83627+1 , 0x0F ) ; // Input direction ; SGPI10~13 // Output direction ; SGPO17~14 // t1 ----outportb ( config_W83627 , CR07 ) ; outportb ( config_W83627+1 , GPIO1_LDN ) ; outportb ( config_W83627 , CRF1 ) ; outportb ( config_W83627+1 , 0x0F ) ;

// Write 0 ,

outportb ( config_W83627 , CRF1 ) ; al_char = inportb ( config_W83627+1 ) & 0x0F ; if( al_char == 0x00 ) goto next_t2 ; outportb ( config_W83627 , 0xaa ) ; // exit config mode printf("\n\n Error#01 : PPAP-3727 GPIO test failed(GPO17->GPI10_w0x0). But=0x%X \n\n",al_char); exit(1);

// t2 -----next_t2: outportb ( config_W83627 , CRF1 ) ; outportb ( config_W83627+1 , 0xFF ) ;

// Write 1 ,

outportb ( config_W83627 , CRF1 ) ; al_char = inportb ( config_W83627+1 ) & 0x0F ; if( al_char == 0x0F ) goto next_t3 ; outportb ( config_W83627 , 0xaa ) ; // exit config mode printf("\n\n Error#02 : PPAP-3727 GPIO test failed(GPO17->GPI10_w0xF). But=0x%X \n\n",al_char); exit(1);

// GPIO Direction setting for t3 and t4 test items ============== NAR-2 2 0 0U s e r s Manual 26

next_t3: outportb ( config_W83627 , CRF0 ) ; outportb ( config_W83627+1 , 0xF0 ) ; // Output direction ; SGPO10~13 // Input direction , SGPI17~14 // t3 ----------------outportb ( config_W83627 , CRF1 ) ; outportb ( config_W83627+1 , 0xF0 ) ; // Write 0 , outportb ( config_W83627 , CRF1 ) ; al_char = inportb ( config_W83627+1 ) & 0xF0 ; if( al_char == 0x00 ) goto next_t4 ; outportb ( config_W83627 , 0xaa ) ; // exit config mode printf("\n\n Error#03 : PPAP-3727 GPIO test failed(GPO10->GPI17_w0x0). But=0x%X \n\n",al_char); exit(1); // t4 -----------------next_t4: outportb ( config_W83627 , CRF1 ) ; outportb ( config_W83627+1 , 0xFF ) ;

// Write 1 ,

outportb ( config_W83627 , CRF1 ) ; al_char = inportb ( config_W83627+1 ) & 0xF0 ; if( al_char == 0xF0 ) goto gpio_done ; outportb ( config_W83627 , 0xaa ) ; // exit config mode printf("\n\n Error#04 : PPAP-3727 GPIO test failed(GPO10->GPI17_w0xF). But=0x%X \n\n",al_char); exit(1) ; // gpio_done : outportb ( config_W83627 , 0xaa ) ; // exit config mode printf("\n\n PPAP-3727 GPIO test okay. ^_^ \n\n"); exit(0); } // end of main()

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4.2
/include/gloab.h unsigned int cnt=0;

WDT Sample Code

/include/WDT.h #include <time.h> // Global constant --------- Start -------------#define LDN8 0x08 // WDT in LDN8 #define CR07 0x07 #define CR20 0x20 #define CR2B 0x2B #define CR2D 0x2D #define CR30 0x30 #define CRF5 0xF5 #define CRF6 0xF6 #define CRF7 0xF7 #define portb 0x61 #define refresh_status 0x10 #define Bit7_6_AND0 0x3F #define Bit4_AND0 0xEF #define Bit3_AND0 0xF7 #define Bit2_AND0 0xFB #define Bit0_AND0 0xFE #define Bit4_OR1 0x10 #define Bit3_OR1 0x08 #define Bit2_OR1 0x04 #define Bit0_OR1 0x01 #define second_unit 0x69 // Global constant --------- End --------------

// Global Variable ----- Start --time_t t; struct tm *d; unsigned char W627_CONFIG = 0x2E , W627_DATA = 0x2F , W627_EDHG = 0x00 ; // Global Variable ---- end -----

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/application/test_all/common.c #include <stdio.h> #include <string.h> unsigned int cnt=0; unsigned char *status[5] = {"","Status=Ok","Status=Fail","Status=Testing"}; /*------------------------------------------------------------------------*/ void showprocitem(int fn) { system("clear"); printf("+--------------------------------------------------------------------+\n"); printf("| Portwell watch dog timer test program version:1.00 |\n"); printf("| Author:Jason Wu |\n"); printf("+--------------------------------------------------------------------+\n"); printf("| Product select |\n"); printf("| [\x1b[%d;%dm1\x1b[m] NAR5510/NAR7090 [\x1b[%d;%dmESC\x1b[m] exit program |\n",36,1,36,1); printf("| \x1b[%d;%dmSelect function\x1b[m:%-24c\x1b[%d;%dmstatus\x1b[m:\x1b[%d;%dm%20s\x1b[m|\n",33,1,fn,33,1,31,1,""); printf("+--------------------------------------------------------------------+\n\n"); } void showtitle_THG(unsigned int sts) { system("clear"); printf("+----------------------------------------------------------------------------+\n"); printf("| Portwell watch dog timer test program version:1.00 |\n"); printf("| Author:Jason Wu |\n"); printf("+----------------------------------------------------------------------------+\n"); printf("| Product Type :NAR-5510/NAR-7090 \x1b[%d;%dm%15s\x1b[m|\n",33,1,status[sts]); printf("| Refresh SYS_WDT 1 times. < choice > Twd : Refresh interval |\n"); printf("| PRESS Ctrl+C KEY TO STOP REFRESHING SYS_WDT & DISABLE SYS_WDT. |\n"); printf("| < 1 >: 2 seconds : 0.385 second. < A >: 40 seconds : 34.011 second. |\n"); printf("| < 2 >: 3 seconds : 1.374 seconds. < B >: 48 seconds : 40.824 seconds. |\n"); printf("| < 3 >: 4 seconds : 2.363 seconds. < C >: 60 seconds : 51.044 seconds. |\n"); printf("| < 4 >: 8 seconds : 5.604 seconds. < D >: 120 seconds : 102.088 seconds. |\n"); printf("| < 5 >: 10 seconds : 7.033 seconds. < E >: 4 minutes : 204.176 seconds. |\n"); printf("| < 6 >: 16 seconds : 13.736 seconds. < F >: 8 minutes : 408.352 seconds. |\n"); printf("| < 7 >: 20 seconds : 17.033 seconds. < G >: 10 minutes : 510.439 seconds. |\n"); printf("| < 8 >: 24 seconds : 20.330 seconds. < H >: 30 minutes :1531.318 seconds. |\n"); printf("| < 9 >: 32 seconds : 27.198 seconds. < I >: 60 minutes :3060.000 seconds. |\n"); printf("| < 0 >: Enable WDT ( This will reset system within 1 second.) |\n"); printf("| <esc>: return main window |\n"); printf("+----------------------------------------------------------------------------+\n"); } void showtitle_EDHG(unsigned int sts) { system("clear"); printf("+----------------------------------------------------------------------------+\n"); printf("| Portwell watch dog timer test program version:1.00 |\n"); printf("| Author:Jason Wu |\n"); printf("+----------------------------------------------------------------------------+\n"); printf("| Product Type :NAR-5510/NAR-7090 \x1b[%d;%dm%15s\x1b[m|\n",33,1,status[sts]); printf("| Refresh SYS_WDT 1 times. < choice > Twd : Refresh interval |\n"); printf("| PRESS Ctrl+C KEY TO STOP REFRESHING SYS_WDT & DISABLE SYS_WDT. |\n"); printf("| < 1 >: 8 ms : 4.350 ms. < A >: 2 seconds : 0.385 second. |\n"); printf("| < 2 >: 32 ms : 24.675 ms. < B >: 8 seconds : 5.604 seconds. |\n"); printf("| < 3 >: 96 ms : 78.750 ms. < C >: 16 seconds : 13.736 seconds. |\n"); printf("| < 4 >: 128 ms : 105.750 ms. < D >: 32 seconds : 27.198 seconds. |\n"); printf("| < 5 >: 146 ms : 121.500 ms. < E >: 48 seconds : 40.824 seconds. |\n"); printf("| < 6 >: 186 ms : 161.700 ms. < F >: 60 seconds : 51.044 seconds. |\n"); printf("| < 7 >: 226 ms : 202.800 ms. < G >: 120 seconds : 102.088 seconds. |\n"); printf("| < 8 >: 246 ms : 232.800 ms. < H >: 4 minutes : 204.176 seconds. |\n"); NAR-2 2 0 0U s e r s Manual 29

printf("| < 9 >: 255 ms : 237.000 ms. < I >: 30 minutes :1531.318 seconds. |\n"); printf("| < 0 >: Enable WDT ( This will reset system within 1 second.) |\n"); printf("| <esc>: return main window |\n"); printf("+----------------------------------------------------------------------------+\n"); } unsigned int WDT_test_T(void) { unsigned char rst=0x00; W627_Init(); showtitle_THG(0x00); do{ if(((rst>=0x30)&&(rst<=0x39))||((rst>=0x41)&&(rst<=0x49))||((rst>=0x61)&&(rst<=0x69))) { switch(rst) { case 0x31 : WDT_RFSHs_m(0x69,2,0.385 ) ; break ; case 0x32 : WDT_RFSHs_m(0x69,3,1.374 ) ; break ; case 0x33 : WDT_RFSHs_m(0x69,4,2.363 ) ; break ; case 0x34 : WDT_RFSHs_m(0x69,8,5.604 ) ; break ; case 0x35 : WDT_RFSHs_m(0x69,10,7.033 ) ; break ; case 0x36 : WDT_RFSHs_m(0x69,16,13.736 ) ; break ; case 0x37 : WDT_RFSHs_m(0x69,20,17.033 ) ; break ; case 0x38 : WDT_RFSHs_m(0x69,24,20.330 ) ; break ; case 0x39 : WDT_RFSHs_m(0x69,32,27.198 ) ; break ; case 0x41 : WDT_RFSHs_m(0x69,40,34.011) ; break ; case 0x61 : WDT_RFSHs_m(0x69,40,34.011) ; break ; case 0x42 : WDT_RFSHs_m(0x69,48,40.824) ; break ; case 0x62 : WDT_RFSHs_m(0x69,48,40.824) ; break ; case 0x43 : WDT_RFSHs_m(0x69,60,51.044) ; break ; case 0x63 : WDT_RFSHs_m(0x69,60,51.044) ; break ; case 0x44 : WDT_RFSHs_m(0x69,120,102.088) ; break ; case 0x64 : WDT_RFSHs_m(0x69,120,102.088) ; break ; case 0x45 : WDT_RFSHs_m(0x5a,4,204.176) ; break ; case 0x65 : WDT_RFSHs_m(0x5a,4,204.176) ; break ; case 0x46 : WDT_RFSHs_m(0x5a,8,408.352) ; break ; case 0x66 : WDT_RFSHs_m(0x5a,8,408.352) ; break ; case 0x47 : WDT_RFSHs_m(0x5a,10,510.439) ; break ; case 0x67 : WDT_RFSHs_m(0x5a,10,510.439) ; break ; case 0x48 : WDT_RFSHs_m(0x5a,30,1531.318) ; break ; case 0x68 : WDT_RFSHs_m(0x59,30,1531.318) ; NAR-2 2 0 0U s e r s Manual 30

break ; case 0x49 : WDT_RFSHs_m(0x5a,60,3060.000) ; break ; case 0x69 : WDT_RFSHs_m(0x5a,60,3060.000) ; break ; case 0x30 : resetpc(); break; } showtitle_THG(cnt); printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1); }else { printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1); } rst=getchar(); }while(rst != 0x1b); exit_W627(); return 0; } unsigned int WDT_test_ED(void) { unsigned char rst=0x00; W627_Init(); showtitle_THG(0x00); do{ if(((rst>=0x30)&&(rst<=0x39))||((rst>=0x41)&&(rst<=0x49))||((rst>=0x61)&&(rst<=0x69))) { switch(rst) { case 0x31 : WDT_RFSHms_1K(8,290) ; break ; case 0x32 : WDT_RFSHms_1K(32,1645) ; break ; case 0x33 : WDT_RFSHms_1K(96,5250) ; break ; case 0x34 : WDT_RFSHms_1K(128,7050) ; break ; case 0x35 : WDT_RFSHms_1K(146,8100) ; break ; case 0x36 : WDT_RFSHms_1K(186,10780) ; break ; case 0x37 : WDT_RFSHms_1K(226,13520) ; break ; case 0x38 : WDT_RFSHms_1K(246,15520) ; break ; case 0x39 : WDT_RFSHms_1K(255,15800) ; break ; // ------------------ A~ G , 1 second unit , CFR5_bit4P0 -----case 0x41 : WDT_RFSHs_m(0x69 ,2,0.385) ; break ; case 0x61 : WDT_RFSHs_m(0x69,2,0.385) ; break ; case 0x42 : WDT_RFSHs_m(0x69, 8,5.604) ; break ; case 0x62 : WDT_RFSHs_m(0x69,8,5.604) ; break ; case 0x43 : WDT_RFSHs_m(0x69,16,13.736) ; break ; case 0x63 : WDT_RFSHs_m(0x69,16,13.736) ; break ; case 0x44 : WDT_RFSHs_m(0x69,32,27.198) ; break ; case 0x64 : WDT_RFSHs_m(0x69,32,27.198) ; NAR-2 2 0 0U s e r s Manual 31

break ; case 0x45 : WDT_RFSHs_m(0x69,48,40.824) ; break ; case 0x65 : WDT_RFSHs_m(0x69,48,40.824) ; break ; case 0x46 : WDT_RFSHs_m(0x69,60,51.044) ; break ; case 0x66 : WDT_RFSHs_m(0x69,60,51.044) ; break ; case 0x47 : WDT_RFSHs_m(0x69,120,102.088) ; break ; case 0x67 : WDT_RFSHs_m(0x69,120,102.088) ; break ; // H,I Minute unit ------------------------------case 0x48 : WDT_RFSHs_m(0x5a,4,204.176) ; break ; case 0x68 : WDT_RFSHs_m(0x59,4,204.176) ; break ; case 0x49 : WDT_RFSHs_m(0x5a,30,1531.318) ; break ; case 0x69 : WDT_RFSHs_m(0x5a,30,1531.318) ; break ; case 0x30 : resetpc(); break; } showtitle_THG(cnt); printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1); }else { printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1); } rst=getchar(); }while(rst != 0x1b); exit_W627(); return 0; }

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/application/test_all/main.c #include <stdio.h> extern void showprocitem(int fn); extern unsigned int WDT_test_T(void); /*------------------------------------------------------------------------*/ int main(void) { char rst=0x30; showprocitem(rst); do{ if(rst == 0x31){ WDT_test_T(); showprocitem(rst); } printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",9,0,33,1); rst=getchar(); }while(rst != 0x1b); return 0; }

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