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Session Overview
Digital Systems What is VHDL Why VHDL? (Advantages, Disadvantages) General Structure of VHDL Entity (Declaration / Architecture) PORT statement IEEE Standard 1164 Entity Architectures
Digital Systems
Input from Real World Switches, TTL. RS-232 Analog (sound, video,)
Digital Processing
Data Paths Registers, ALU, Memory (muscle) Control Path FSMs (brain)
Output to the Real World Switches, TTL. RS-232 Analog (sound, video,)
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We need a higher level language such as VHDL or Verilog to specify the programming of PALs, CPLDs, and FPGAs.
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For ASICs, verification and fitting phases are usually much longer, as a fraction of overall project time.
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VHDL
Developed in the mid-1980s under DoD sponsorship
Mandated for federally-sponsored VLSI designs
VHDL
VHSIC Hardware Description Language
A double acronym Structural Behavioral Timing
Rich and powerful language Basic standard environment Supports both Hardware and Software concepts
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VHDL
Advantages:
Documentation Shorter design cycle Improved design quality Vendor and technology independence Lower design cost Design management
Disadvantages:
A change of culture
Away from Schematic-based Design towards Language-based Design Selecting and paying for tools
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Control Logic
Things to Remember
VHDL is a programming language.
Many good and bad programs have been (will be) written. Style is important. Clarity is important.
Synthesis is hard.
Fitter programs take clues from your VHDL code.
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Synthesis Result
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Terminologies
VHDL is case Insensitive Comments are represented by -- Each statement is terminated with a semicolon ; Each component is described in two parts:
Entity Declaration (Interface to the outside world) Entity Architecture (Under the hood)
Port
Each I/O signal in an entity declaration is called a PORT (Analogous to a pin in schematic) with following attributes:
Name Mode : Direction of data flow
IN OUT BUFFER INOUT boolean bit bit_vector std_logic
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Port
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eqcomp4
equals
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Entity Architecture
An Architecture describes the content of an entity. VHDL allows various styles of architecture:
Behavioral Description Dataflow Description Structural Descriptions
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Architecture (Behavioral)
ARCHITECTURE behavioral OF eqcomp4 IS BEGIN comp : PROCESS (a,b) BEGIN IF a = b THEN equals <= 1; ELSE equals <= 0; END IF; END PROCESS comp; END behavioral;
ARCHITECTURE behavioral OF eqcomp4 IS BEGIN comp : PROCESS (a,b) BEGIN equals <= 0; IF a = b THEN equals <= 1; END IF; END PROCESS comp; END behavioral;
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Architecture (Behavioral)
Behavioral architecture deals with high level set of statements rather than the structure or netlist. PROCESS ( sensitivity list) Statement
When any of the signals in the list change value the process is executed Statements are executed sequentially within a process All signals are updated at the end of the process
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Architecture (Dataflow)
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Architecture (Dataflow )
Dataflow architecture specifies how data is transferred from signal to signal and input to output without use of sequential statements. Note that there is no PROCESS( ) statement. Concurrent signal assignment.
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VHDL Hierarchy
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Architecture (Structural)
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Architecture (Structural)
Structural designs are hierarchical Note COMPONENT (When an entity is used inside of another entity) Each PORT MAP instantiates a component. Note use of SIGNAL to interconnect components
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Summary
Digital Systems What is VHDL Why VHDL? (Advantages, Disadvantages) General Structure of VHDL Entity (Declaration / Architecture) PORT statement IEEE Standard 1164 Entity Architectures
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