IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO.
7, JULY 2007 777
A BIST TPG for Low Power Dissipation
and High Fault Coverage
Seongmoon Wang
Abstract—This paper presents a low hardware overhead test
pattern generator (TPG) for scan-based built-in self-test (BIST)
that can reduce switching activity in circuits under test (CUTs)
during BIST and also achieve very high fault coverage with
reasonable lengths of test sequences. The proposed BIST TPG
decreases transitions that occur at scan inputs during scan shift
operations and hence reduces switching activity in the CUT. The
proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight
WRBIST. Test patterns generated by the LT-RTPG detect
easy-to-detect faults and test patterns generated by the 3-weight
WRBIST detect faults that remain undetected after LT-RTPG
patterns are applied. The proposed BIST TPG does not require
modification of mission logics, which can lead to performance
degradation. Experimental results for ISCAS’89 benchmark
circuits demonstrate that the proposed BIST can significantly
reduce switching activity during BIST while achieving 100% fault
coverage for all ISCAS’89 benchmark circuits. Larger reduction
in switching activity is achieved in large circuits. Experimental
results also show that the proposed BIST can be implemented with
low area overhead.
Index Terms—Built-in self-test (BIST), heat dissipation during
test application, low power testing, power dissipation during test
application, random pattern testing.
I. INTRODUCTION
INCE in built-in self-test (BIST), test patterns are gener-
S ated and applied to the circuit-under-test (CUT) by on-chip
hardware, minimizing hardware overhead is a major concern
of BIST implementation. Unlike stored pattern BIST, which
requires high hardware overhead due to memory devices re-
quired to store precomputed test patterns, pseudorandom BIST,
where test patterns are generated by pseudorandom pattern
generators such as linear feedback shift registers (LFSRs) and
cellular automata (CA), requires very little hardware overhead.
However, achieving high fault coverage for CUTs that con-
tain many random pattern resistant faults (RPRFs) only with
(pseudo) random patterns generated by an LFSR or CA often
requires unacceptably long test sequences thereby resulting in
prohibitively long test time. The random pattern test length
required to achieve high fault coverage is often determined by
only a few RPRFs [1].
Several techniques have been proposed to address this
problem. Reseedable and/or reconfigurable LFSRs are pro-
posed in [2]–[4]. In [5] and [6], random patterns that do not
detect any new faults are mapped into deterministic tests for
RPRFs. In test point insertion (TPI) techniques [7], [8], control
and observation points are inserted at selected gates to improve
detection probabilities of RPRFs. In weighted random pattern
Manuscript received May 24, 2006; revised December 22, 2006.
The author is with NEC Laboratories, America, Princeton, NJ 08540 USA.
Digital Object Identifier 10.1109/TVLSI.2007.899234
1063-8210/$25.00 © 2007 IEEE
testing [1], [9]–[11], the outputs of test pattern generator (TPG)
are biased to generate test sequences that have nonuniform
signal probabilities to increase detection probabilities of RPRFs
that escape pseudorandom test sequences, which have a uni-
form signal probability of 0.5. Random pattern generators
proposed in [12] and [13] use Markov sources to exploit spatial
correlation between state inputs that are consecutively located
in the scan chain. A 3-weight weighted random BIST (3-weight
WRBIST) can be classified as an extreme case of conventional
weighted random pattern testing BIST. However, in contrast
to conventional weighted random pattern testing BIST where
various weights, e.g., 0, 0.25, 0.5, 0.75, 1.0, can be assigned
to outputs of TPGs, in 3-weight WRBIST, only three weights,
0, 0.5, and 1, are assigned. Since only three weights are used,
circuitry to generate weights is simple; weight 1 (0) is obtained
by fixing a signal to a 1 (0) and weight 0.5 by driving a signal
by an output of a pseudorandom pattern generator, such as an
LFSR. Weight sets are calculated from test cubes for RPRFs.
Though the attainment of high fault coverage with practical
lengths of test sequences is still one major concern of BIST
techniques, reducing switching activity has become another im-
portant objective. It has been observed that switching activity
during test application is often significantly higher than that
during normal operation [14]. The correlation between consec-
utive random patterns generated by an LFSR is low—this is a
well-known property of LFSR generated patterns [1], [15]. On
the other hand, significant correlation exists between consecu-
tive patterns during the normal operation of a circuit. Hence,
switching activity in a circuit can be significantly higher during
BIST than that during its normal operation. Finite-state ma-
chines are often implemented in such a manner that vectors
representing successive states are highly correlated to reduce
power dissipation [16]. However, use of design-for-testability
(DFT) techniques such as scan significantly decreases the cor-
relation between consecutive state vectors. Use of scan allows to
apply patterns that cannot appear during normal operation to the
state inputs of the CUT during test application. Furthermore, the
values applied at the state inputs of the CUT during scan shift
operations represent shifted values of test vectors and circuit re-
sponses and have no particular temporal correlation. Excessive
switching activity due to low correlation between consecutive
test patterns can cause several problems [14], [17]–[19].
Since heat dissipation in a CMOS circuit is proportional to
switching activity, a CUT can be permanently damaged due
to excessive heat dissipation if switching activity in the circuit
during test application is much higher than that during its normal
operation. Heat dissipated during test application is already in-
fluencing the design of test methodologies for practical circuits
[14], [19], [20].
778 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007

Metal migration (electromigration) causes erosion of conduc- activity during BIST are illustrated in Section III. The architec-
tors and subsequent failure of circuits [21]. Since temperature and ture of the proposed TPG and the outline of algorithm used to
current density are major factors that determine electromigration design the proposed BIST TPG are described in Section IV. A
rate, elevated temperature, and current density caused by exces- technique to minimize hardware overhead for implementing the
sive switching activity during test application will severely de- proposed BIST TPG for circuits with multiple scan chains is
crease reliability of CUTs. This is even more severe in circuits presented in Section V. Section VI reports experimental results.
equipped with BIST since such circuits are tested frequently. Finally, Section VII presents the conclusions.
To test a bare die, power must be supplied during the period
of test through probes, which typically have higher inductances II. 3-WEIGHT WRBIST
than power and ground pins of the circuit package. Hence, the bare
A. Generator
die under test will experience higher power/ground noise which is
given by , where is the inductance of power and ground In this paper, we assume that the sequential CUT has pri-
line and is the rate of change of current flowing in power mary and state inputs, and employs full-scan. Even though the
and ground lines. Excessive power/ground noise can erroneously proposed BIST TPG is applicable to scan designs with multiple
change the logic state of circuit lines causing some good dies to scan chains, we assume that all primary and state inputs are
fail the test, leading to unnecessary loss of yield. driven by a single scan chain unless stated otherwise (applica-
In this paper, we propose a low hardware overhead scan- tion to multiple scan chains is discussed separately in Section V)
based BIST technique that can achieve very high fault coverage only for clarity and convenience of illustration. A test cube is
without the risk of damaging CUTs due to excessive switching a test pattern that has unspecified inputs. The detection proba-
activity during BIST. Recently, techniques to reduce switching bility of a fault is defined as the probability that a randomly gen-
activity during BIST have been proposed in [17] and [22]–[25]. erated test pattern detects the fault [1]. In the 3-weight WRBIST
A straightforward solution is to reduce the speed of the test scheme, fault coverage for a random pattern resistant circuit is
clock during scan shift operations. However, since most test ap- enhanced by improving detection probabilities of RPRFs; the
plication time of scan-based BIST is spent for scan shift op- detection probability of an RPRF is improved by fixing some
erations (typically , where is the number of scan inputs of the CUT to the values specified in a deterministic test
flip-flops in the longest scan chain), this will increase test appli- cube for the RPRF. A generator or weight set is a vector that rep-
cation time by about a factor of if scan flip-flops are clocked at resents weights that are assigned to inputs of the circuit during
speed during scan shift operations. Furthermore, reducing 3-weight WRBIST. Inputs that are assigned weight 1 (0) are
the clock speed does not solve high power/ground noise that fixed to 1 (0) and inputs that are assigned weight 0.5 are driven
is caused by a large number of simultaneous transitions in the by outputs of the pseudorandom pattern generator, such as an
circuit. A technique that uses enhanced flip-flops to isolate mis- LFSR and a CA. A generator is calculated from a set of deter-
sion logics of the CUT from scan chains is proposed [17]. Major ministic test cubes for RPRFs.
disadvantages of this technique are performance degradation Consider a sequential circuit that has primary and state
and area overhead entailed by adding extra logics to isolate inputs. denotes a set of test cubes for
mission logics from scan chains. Techniques to schedule tests RPRFs in the CUT, where is an -bit
under power constraints are proposed in [14], [19], and [20]. test cube, where , where is a don’t care.
Test scheduling techniques can reduce overall chip power dis- Fig. 1 shows test cube set , which consists of four test cubes,
sipation. However, these techniques cannot solve the hot spot and . Generator for
problem that is caused by temperature being excessively ele- the circuit with inputs is denoted as an -bit tuple, where
vated at a small area of the chip. and .
Though techniques to reduce switching activity during scan If input is assigned only a 1 (0) or an in every test cube
BIST have been extensively studied, very few papers simul- and assigned a 1 (0) at least in one test cube in , then input
taneously address both excessive switching activity and fault is assigned a 1 (0) in the generator, i.e., (0). If input
coverage. A BIST TPG that can achieve high fault coverage is assigned a 1 in a test cube , i.e., , and assigned a 0
and also reduce switching activity during BIST is proposed for in another test cube , i.e., , then input is assigned
single scan chain designs in [26], which augments the LT-RTPG a in the generator, i.e., . Otherwise ( is always
[23] with the serial fixing 3-weight WRBIST [27]. It is shown assigned an in every generator), input is assigned an
that the 3-weight WRBIST can achieve very high fault coverage in the generator, i.e., . In summary, is defined as
with low hardware overhead [27]. The LT-RTPG proposed in follows:
[23] generates correlated test patterns that can reduce transitions
at state inputs during scan shift operations. The serial fixing if or in and at least one
3-weight WRBIST can also generate test patterns that cause less if or in and at least one
switching activity during BIST. This paper is a significant ex- if and where
tension of [26], especially, a technique to optimize TPGs for otherwise
multiple scan chain designs is proposed. (1)
The rest of this paper is organized as follows. Section II
briefly introduces the serial fixing 3-weight WRBIST [27]. Inputs that are assigned ’s in a generator are called conflicting
The techniques that are used in this paper to reduce switching inputs of the generator.
WANG: BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE 779

Fig. 2. Example generators (weight sets).

Fig. 1. Example test cube sets. (a) Testcube set C . (b) Testcube subsets C ;C .

In the test cube shown in Fig. 1, input is always assigned

only a 0 or an in every test cube in (0 in and and
in and ). Therefore, is assigned 0 in generator .
On the other hand, is assigned a 1 in generator since
input is always assigned only a 1 or an in every test cube
Fig. 3. Exemplary 3-weight WRBIST.
(1 in and and in and ). In contrast, since input ,
which is assigned both 0 and 1 (0 in and 1 in and ),
in . first subsession, inputs and are fixed to 0, 0,
Assume that test cubes, , and , are only test cubes 1, 0, and 1, respectively, to generate test patterns by using
that detect faults and , respectively. Under this as- . In the second subsession, inputs and are
sumption, the detection probability of fault is simply given by fixed to 1, 0, 0, and 0, respectively, to generate test patterns
. If , then input by using . In this paper, the same patterns are gener-
can be fixed to a 1 (0) without making any fault in untestable ated by using every generator , where to
since input is never assigned a 0 (1) in any test cube. Note that simplify hardware for the BIST controller. However, different
fixing input to a 1 (0) increases the number of binary values numbers of test patterns can also be generated to reduce test ap-
by 1 in all test cubes. Hence, fixing to a 1 (0) improves de- plication time at the expense of higher hardware overhead. Ad-
tection probabilities of faults that require a 1 (0) at input for equate numbers of test patterns should be generated by using
their detection by a factor of 2. When , e.g., and each generator to detect all faults targeted by the generator. A
of Fig. 1(a), there are test cubes in that conflict at input , probability-based procedure to compute a suitable time interval
so that fixing input to a binary value , where , for generator is described in [28].
may make faults for which test cubes are assigned at un-
detectable.
B. Architecture of 3-Weight WRBIST
If a circuit contains a large number of RPRFs, then test cubes
for RPRFs may be assigned conflicting values in many inputs Fig. 2 shows a set of generators and Fig. 3 shows an imple-
resulting in a generator where large number of inputs are as- mentation of the 3-weight WRBIST for the generators shown
signed ’s. Hence, only a few inputs can be fixed in such gen- in Fig. 2. The shift counter is an -modulo counter,
erators without making any fault untestable. If a circuit has a where is the number of scan elements in the scan chain (since
large number of RPRFs, then multiple generators, each of which the generators are 9 bits wide, the shift counter has
is calculated from test cubes for a subset of RPRFs in the circuit, 4 stages). When the content of the shift counter is ,
may be required to achieve high fault coverage with a reason- where , a value for input is scanned into the
able length of random pattern sequence. input of scan chain. The generator counter selects appropriate
In this paper, the generator for subset is denoted by generators; when the content of the generator counter is , test
, where is the number of patterns are generated by using , where .
inputs of the CUT. If we partition the four test cubes Pseudo-random pattern sequences generated by an LFSR and
and shown in Fig. 1(a) into two groups a CA are modified (fixed) by controlling the AND and OR gates
and , then inputs , and can, with overriding signals and ; fixing a random value to a 0
respectively, be fixed to 0, 0, 1, 0, and 1 in and inputs is achieved by setting to a 1 and to a 0 and fixing a random
, and to 1, 0, 0, and 0 in without any con- value to a 1 is achieved by setting to a 1 (since a random value
flict. As a consequence, and can be fixed to a 1 by setting to a 1 independent of the state
. Note that numbers of conflicting of , the state of is a don’t care). Overriding signals and
inputs, i.e., ’s, of both and are reduced to are driven by the outputs of flip-flops, and . The
1 and detection probabilities of all four faults , and inputs of and are in turn driven by the outputs of the
increase to . decoding logic and , respectively, which are generated
Since test cubes are grouped into two subsets and , the by the outputs of the shift counter and the generator counter as
entire test session is also divided into two subsessions. In the inputs.
780 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007

The shift counter is required by all scan-based BIST tech-

niques and not particular to the proposed 3-weight WRBIST
scheme. All BIST controllers need a pattern counter that counts
the number of test patterns applied. The generator counter
can be implemented from MSB (most significant bit)
stages of the existing pattern counter, where is the number
of generators, and no additional hardware is required for the
generator counter. Hence, hardware overhead for implementing
a 3-weight WRBIST is incurred only by the decoding logic
and the fixing logic, which includes two toggle flip-flops (
flip-flops), an AND and an OR gate. Since the fixing logic can
be implemented with very little hardware, overall hardware
overhead for implementing the serial fixing 3-weight WRBIST
is determined by hardware overhead for the decoding logic.
Consider generating test patterns by the TPG shown in Fig. 3.
Assume that if ( , and ),
both and are set to 0’s and hence the flip-flops hold
their previous states in cycles when a scan value for input is Fig. 4. D and D values: (a) with toggle flip-flops TF and TF and (b)
scanned in. Also assume that flip-flop is initialized to a without toggle flip-flops.
1 and flip-flop is initialized to a 0 before each scan shift
operation starts. As shown in Fig. 3, scan flip-flops are placed in
the scan chain in a descending order of their subscript numbers. scheme with the flip-flops. Fig. 4(a) shows ,
Hence, the value for input is scanned in first and the value and values for the scheme with flip-flops that is imple-
for input is scanned in last. mented for the three generators and
Test patterns are generated by using generator shown in Fig. 2. The column under the label shows the initial
first. Since states of and . is assigned 1’s at five locations (
(see Fig. 2) when a value for scan input is scanned in, in , and in , and and in )
(the output of ) should be set to a 1 to set the output of and is assigned 1’s at four locations ( in in
the AND gate to a 0 (to fix the value for scan input to a 0) , and and in ). Hence, the on-set of the
and (the output of ) should be set to a 0 to propagate function for has five minterms and the on-set of the function
the 0 at the output of the AND gate to the output of the OR for has four minterms. Hardware overhead required to im-
gate. Since the initial state of is a 1 and the initial state plement a decoding logic is in general determined by the number
of is a 0, both and are set to 0’s and and of minterms in the on-set (or off-set) of the function of the de-
hold their initial states. At the next scan shift cycle coding logic.
, since , both and are Now consider a version of 3-weight WRBIST that is imple-
assigned a 0 to make and hold their previous states mented without the flip-flops between the outputs of the de-
and . Since , both and should coding logic and the inputs of the AND and OR gate. and
be set to a 0 to scan in a random value, which is generated by values for all three generators , and
the LFSR, for . Hence, is set to a 1 to toggle the state are shown in Fig. 4(b) for comparisons with the scheme with
of to a 0 when . The next three flip-flops. For every input that is assigned a 0 in a generator
inputs , and are assigned in generator , , i.e., , its corresponding value should be a 1
i.e., . Hence, and hold their and value be a 0. If is assigned a 1 in a generator ,
previous states, i.e., , for the next three cycles i.e., , then the corresponding value should be a 1
, and 5. Since , both and (the value is a don’t care). The on-set (off-set) of the func-
hold their previous states when . tion for has eight (five) minterms and the on-set (off-set) of
Next, since is set to a 1 to fix the value for scan the function for has six (13) minterms. Hence, the function
input to a 1. This requires to be set to a 1 to toggle the for the decoding logic of this scheme requires more minterms
state of to a 1. Finally, when , since in its on-set and off-set than that for the decoding logic of the
, both and are assigned a 0 and both and scheme with flip-flops. Significant reduction in the number
hold their previous states. This sequence is repeatedly of minterms can be achieved by inserting flip-flops for large
generated at and until all test patterns are applied designs.
to the scan inputs. and values for generators
and can be determined in similar manners. C. ATPG to Generate Suitable Test Cubes
Random patterns generated by the LFSR can be fixed by con- Each generator is computed from a set of deterministic test
trolling the AND/OR gates directly by the decoding logic without cubes for RPRFs. A test cube set is dynamically constructed
the two flip-flops. However, this scheme will incur larger by continuously adding test cubes into the test cube set. The
hardware overhead for the decoding logic and also cause more test cube set , which is currently under construction, i.e., into
transitions in the CUT during BIST (see Section III) than the which test cubes are currently added, are called the current test
WANG: BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE
cube set. Test cubes are added into the current test cube set until
placing any more test cube into makes the number of con-
flicting inputs, i.e., ’s, in the generator greater than a prede-
fined threshold. Whenever a test cube is placed into , gener-
ator is updated according to (1). Upon the completion
of generating a test cube set , a new current test cube set
is created and the test cubes generated later are placed into the
new test cube set . puts), whenever there is a choice of several paths to backtrace
Since each generator requires a different sequence of control
bits at the output of the decoding logic, hardware overhead for
the decoding logic is determined also by the number of genera-
tors. A special automatic test pattern generation (ATPG) is used
to generate deterministic test cubes for RPRFs that are suitable
to minimize the number of generators. In order to minimize the
number of generators (placing more test cubes into each test
cube set will result in smaller number of generators), the pro-
posed ATPG generates each test cube taking all test cubes ex-
isting in the current test cube set into consideration. At the heart
of the ATPG technique are three cost functions: controllability,
observability, and test generation cost function, which are ob-
tained by modifying the traditional SCOAP-like [29] cost func-
tions. The test generation process of the ATPG, which is based
on PODEM [30], is guided by the cost functions to generate
suitable test cubes.
The controllability cost of input , is defined by
considering the generator of the current test cube set
as follows:
if
if
where (2)
if
if
where is a binary value 0 or 1.
The purpose of the controllability cost is to estimate the
number of conflicting inputs that would be caused by adding
into the current test cube set a test cube where input is
assigned a binary value . If , the current test cube set
already contains test cubes that conflict at input (at least
one test cube in the current test cube is assigned a 1 at and
another test cube is assigned a 0 at ). Hence, assigning any
binary value to does not cause any more adverse effect.
Hence, . When , adding a test cube
whose input is assigned a 1 (0) causes no conflict with any
test cube in the current test cube set. Hence, . If
(0), all test cubes existing in the current test cube set
are assigned only 1 (0) or at input . Hence, adding a test
cube whose input is assigned the opposite value 0 (1) causes
a conflict at input with other test cubes in the current test
cube set. Hence, high cost is given. Finally, if
(input is not specified in any test cube in the current
test cube set), adding a test cube that is assigned at input
may increase one minterm in the on-set for the function of . of the fault given by the estimate test generation cost function
Hence, a small cost 1 is given.
The controllability costs for internal circuit line in the cir-
cuit, which are computed in a similar manner to the testability
measures used in [29], are given by
if
(3)
otherwise
781
where and are, respectively, the inputs and the output of
a gate with controlling value and inversion . The controlling
value of a gate is the binary value that, when applied to any input
of a gate, determines the output value of that gate independent
of the values applied at the other inputs of the gate. The control-
lability cost functions guide the ATPG to select the backtrace
paths that require the minimum cost (number of conflicting in-
from the target line to the inputs.
The observability cost functions are recursively computed
from primary outputs to primary inputs. The observability cost
of line is given by
if is a stem with branches
otherwise
(4)
where in the latter case is the output of gate with input and
are all inputs of other than . The observability cost functions
are used to guide the objective selection.
The proposed ATPG will now be described for the stuck-at
fault model. In order to generate a test cube to detect a
stuck-at- at line , first the fault should be activated
by setting line to . The cost to activate l - - is . Then,
the activated fault effect should be propagated to one or more
outputs. The cost to propagate the activated fault effect at line
is . Hence, the test generation cost to generate a test cube
for l - - is defined as the sum of two cost functions
(5)
The test generation cost is used to select a best target fault from
the fault list.
Since test cubes generated by the proposed ATPG are often
over-specified, a few bits that are assigned binary values by the
proposed ATPG can be relaxed to don’t cares while ensuring
the detection of targeted faults. Test cubes with fewer specified
inputs have fewer conflicting inputs with test cubes already in
the current test cube set so that more test cubes can be placed
in the current test cube set. Whenever a test cube is generated,
inputs that are assigned binary values are ordered according to
the cost incurred by assigning each input to its binary value. The
binary value assigned to each of these inputs is flipped in this
order. If all the targeted faults can still be detected even after an
input is flipped to its opposite value, the value assigned to the
input is relaxed to a don’t care.
If a circuit has any reconvergent fanout, an input assignment
required to satisfy some objectives may conflict with that re-
quired to satisfy other objectives, causing the proposed ATPG
to select an objective or backtrace path with a high cost. Hence,
in circuits with reconvergent fanouts, the actual cost of the test
cube generated for a fault may be much higher than the cost
shown in (5). To prevent adding such test cubes to the current
test cube set, if the actual cost of a generated test cube is higher
by a certain number (say, 100) than the estimate test generation
cost of the fault, the generated test cube is discarded. Test gen-
eration is then carried out for alternative target faults until a test
cube is found for a fault whose actual cost is close to the es-
timate test generation cost of the fault or all faults in the fault
782 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007
list are tried. Even in the worst case where all faults in the fault
list need to be tried, generating test cubes is required only for a
few faults. The estimate test generation cost of a fault is always
an optimistic approximate of the actual cost for the fault in the
sense that the actual cost of any test cube for the fault cannot be
less than the estimate test generation cost. Hence, if the estimate
test generation cost of a fault is greater than the actual cost of
the test cube that has the minimum actual cost among the test
cubes that have been generated but discarded due to high actual
cost, then the actual cost of any test cube for the fault cannot
be smaller than the current minimum actual cost. Hence, we do
not need to generate a test cube for the fault. If test cubes for
all faults in the fault list have very high actual cost, then the test
cube that has the minimum actual cost is chosen to be a new
member of the current test cube set.
III. MINIMIZING SWITCHING ACTIVITY DURING BIST
The BIST TPG proposed in this paper reduces switching ac-
tivity in the CUT during BIST by reducing the number of tran-
sitions at scan inputs during scan shift cycles. In this paper,
we assume that the sequential CUT is implemented in CMOS,
and employs full-scan. If scan input is assigned , where
, at time and assigned the opposite value at
time , then a transition occurs at at time . The transition that
occurs at scan input can propagate into internal circuit lines
causing more transitions. During scan shift cycles, the response
to the previous scan test pattern is also scanned out of the scan
chain. Hence, transitions at scan inputs can be caused by both
test patterns and responses. Since it is very difficult to generate
test patterns by a random pattern generator that cause minimal
number of transitions while they are scanned into the scan chain
and whose responses also cause minimal number of transitions
while they are scanned out of the scan chain, we focus on min-
imizing the number of transitions caused only by test patterns
that are scanned in. Even though we focus on minimizing the
number of transitions caused only by test patterns, our exten-
sive experiments show that the proposed TPG can still reduce
switching activity significantly during BIST (see Section VI).
Since circuit responses typically have higher correlation among
neighborhood scan outputs than test patterns, responses cause
fewer transitions than test patterns while being scanned out.
A transition at the input of the scan chain at scan shift cycle
, which is caused by scanning in a value that is opposite to
the value that was scanned in at the previous scan shift cycle
, continuously causes transitions at scan inputs while the
value travels through the scan chain for the following scan shift
cycles. Fig. 5 describes scanning a scan test pattern 01100 into a
scan chain that has five scan flip-flops. Since a 0 is scanned into
the scan chain at time , the 1 that is scanned into the scan
chain at time causes a transition at the input of the scan
chain and continuously causes transitions at the scan flip-flops
it passes through until it arrives at its final destination at time
. In contrast, the 1 that is scanned into the scan chain at
the next cycle causes no transition at the input of the scan
chain and arrives at its final destination at time without
causing any transition at the scan flip-flops it passes through.
This shows that transitions that occur in the entire scan chain
can be reduced by reducing transitions at the input of the scan
Fig. 5. Transitions at scan chain input.
Fig. 6. LT-RTPG.
chain. Since transitions at scan inputs propagate into internal
circuit lines causing more transitions, reducing transitions at the
input of scan chain can eventually reduce switching activity in
the entire circuit.
A. LT-RTPG
The LT-RTPG proposed in [23] reduces switching activity
during BIST by reducing transitions at scan inputs during scan
shift operations. An example LT-RTPG is shown in Fig. 6. The
LT-RTPG is comprised of an -stage LFSR, a -input AND
gate, and a toggle flip-flop (T flip-flop). Hence, it can be imple-
mented with very little hardware. Each of inputs of the AND
gate is connected to either a normal or an inverting output of
the LFSR stages. If large is used, large sets of neighboring
state inputs will be assigned identical values in most test pat-
terns, resulting in the decrease fault coverage or the increase in
test sequence length. Hence, like [23], in this paper, LT-RTPGs
with only or 3 are used. Since a flip-flop holds pre-
vious values until the input of the flip-flop is assigned a 1,
the same value , where , is repeatedly scanned into
the scan chain until the value at the output of the AND gate be-
comes 1. Hence, adjacent scan flip-flops are assigned identical
values in most test patterns and scan inputs have fewer transi-
tions during scan shift operations. Since most switching activity
during scan BIST occurs during scan shift operations (a capture
cycle occurs at every cycles), the LT-RTPG can reduce
heat dissipation during overall scan testing. Various properties
of the LT-RTPG are studied and a detailed methodology for its
design is presented in [23].
It has been observed that many faults that escape random pat-
terns are highly correlated with each other and can be detected
by continuously complementing values of a few inputs from a
parent test vector. This observation is exploited in [26][27], [31],
and [32] to improve fault coverage for circuits that have large
numbers of RPRFs. We have also observed that tests for faults
that escape LT-RTPG test sequences share many common input
WANG: BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE 783

assignments. This implies that RPRFs that escape LT-RTPG test value 0 or 1 in , then both and for are as-
sequences can be effectively detected by fixing selected inputs signed 0 to minimize the number of minterms in the on-sets of
to binary values specified in deterministic test cubes for these the decoding logic function. Note that this minimizes also the
RPRFs and applying random patterns to the rest of inputs. This number of transitions since when either or is set to
technique is used in the 3-weight WRBIST to achieve high fault 1 for scan shift cycles for inputs , no transi-
coverage for random pattern resistant circuits. In this paper we tions occur during the scan shift cycles for these scan inputs.
demonstrate that augmenting the LT-RTPG with the serial fixing On the other hand, if both and are
3-weight WRBIST proposed in [27] can attain high fault cov- 0, i.e., , then we check , i.e., the value assigned
erage without excessive switching activity or large area over- at in , to determine the values of and for
head even for circuits that have large numbers of RPRFs. scan input (recall that both and values for scan in-
puts are always assigned 0). If ,
B. Property of 3-Weight WRBIST to Reduce Switching Activity then we assign for input to 1 to make
If a large set of scan inputs that are consecutively located in and ( and ). This adds
the scan chain are assigned identical values ( is identical to one minterm in the on-set of for all the scan inputs,
any binary value 0 or 1) in a generator, then the flip-flops . In this case, a transition can occur at the
and of 3-Weight WRBIST (see Fig. 3) stay at the input of the scan chain only in the scan shift cycles when a value
same state for many scan shift cycles. While holds a 1, for scan input is scanned in among all scan shift cycles for in-
the output of the OR gate in the fixing logic is set to a 1 and 1’s puts . As the last case, if both and
are continuously scanned into the scan chain and no transitions , i.e., both inputs that flank the consecutive scan inputs
occur at the input of the scan chain. Likewise, while holds are assigned in , then we determine
a 1, random pattern values generated by the LFSR are blocked at the values of and for scan input based on the number
the AND gate and no transition occurs at the input of scan chain of scan inputs between and , i.e., . If , where
provided that the other flip-flop does not toggle. Hence, is a predefined natural number, then we arbitrarily select ei-
in order to significantly reduce the number of transitions at the ther or and assign it to a 1 for input to suppress tran-
input of scan chain, either or should be assigned a 1 sitions at the input of scan chains. Otherwise, we assign both
and stays at the 1 for long periods of scan shift cycles. and for scan input to 0 to minimize the number of
Typically, the majority of scan inputs are assigned ’s (don’t minterms in the on-sets of functions for and . If is
cares) in every generator. Since all the faults that are targeted large, then transitions can occur at the input of the scan chain
by a generator can be detected independent of the scan values in many scan shift cycles. Hence adding one more minterm in
applied to the scan inputs that are assigned ’s in the gener- the on-set of functions for the decoding logic to suppress large
ator, the values of and for those scan inputs are assigned number of transitions is worthy.
such that the number of minterms in the on-sets of the functions For example, consider the set of generators shown in Fig. 4(a).
for and is minimized (to minimize hardware overhead Consecutive scan inputs and are assigned ’s and
for the decoding logic) and either or stays at 1 for input , which precedes in the scan chain, is assigned a
long periods of scan shift cycles (to minimize the number of in . Since is assigned a and hence both
transitions at the input of the scan chain). In order to minimize , we check input , which is the first scan input
the number of minterms in the on-sets of functions for and that is assigned a care bit (0, 1, or ) in after the con-
and for the scan inputs that are assigned ’s in a secutive scan inputs , and , which are assigned ’s in
generator should be assigned 0. Note that does not . Since is assigned a 0 in for is as-
toggle (holds its previous state) when the state of is 0. signed a 1 to toggle the state of in the scan shift cycles
Assume that test patterns are currently generated by gener- for input . On the other hand, in generator , consec-
ator . Also, assume that scan input is assigned an utive inputs , and are assigned ’s and inputs and
while its predecessor is assigned a care bit (0, 1, or , which flank the inputs , and , are assigned both .
) in . Let be the first scan input in the scan chain Hence, the and values for the scan input are deter-
that is assigned a care bit in after , i.e., , In mined by considering the predefined number and the number
other words, consecutive scan inputs , which of consecutive scan inputs that are assigned ’s between and
are located between and , are assigned ’s in . , i.e., 3. If is used, then for input is assigned a 1
and , respectively, denote the states of and to toggle the state of to 1 to suppress transitions. If
in a scan shift cycle when a value for scan input is is used, then both and for input are assigned 0’s to
scanned into the scan chain. In this paper, the decoding logic minimize the number of minterms in the on-sets of functions
is designed such that the states of and for the scan for the decoding logic.
inputs are always the same as those of
and for input , i.e., and values for the inputs IV. PROPOSED TEST PATTERN GENERATOR
are always 0 to minimize the number of The proposed BIST is comprised of two TPGs: an LT-RTPG
minterms in the on-sets of the function for the decoding logic. [23] and a 3-weight WRBIST [27] (see Fig. 7). The multiplexer,
and values for input are determined by consid- which drives the input of scan chain, selects a test pattern source
ering values assigned at and in generator . If either between the LT-RTPG and the 3-weight WRBIST. In the first
or is 1, i.e., is assigned a binary test session, test patterns generated by the LT-RTPG are selected
784 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007

Fig. 7. Proposed BIST TPG.

Fig. 8. BIST TPG for scan design with multiple scan chains.

and scanned into the scan chain to detect easy-to-detect faults.

In the second session, test patterns that are generated by the
3-weight WRBIST are selected to detect the faults that remain
undetected after the first session. Considering the fact that an
LT-RTPG can be implemented with very little hardware over-
head (only one flip-flop and one AND gate in addition to an
LFSR), overall hardware overhead to implement the proposed
TPG is determined by hardware overhead for the decoding logic
of the 3-weight WRBIST.
An outline of the overall procedure to design an optimized
BIST TPG by the proposed method is described in the fol-
lowing.
1) Apply a sequence of test patterns generated by the
LT-RTPG to the circuit and drop all detected faults.
2) .
3) Initialize the current test cube set, , and generator
Fig. 9. Splitting a scan chain. (a) Single scan chain. (b) Two scan chains.
. and unmark all faults
in the fault list.
4) If there are no more faults in the fault list, then exit. Select pairs of outputs, .
an unmarked fault that has the minimum test generation Output , where , drives the input of
cost and generate a test cube for the fault by the proposed toggle flip-flop of the corresponding fixing logic.
ATPG. Since scan chain length, which is defined as the number
5) Add the test cube to the current test cube set, of the scan flip-flops in the longest scan chain, is one of the
. . factors that determine test application time and in turn test cost,
6) Update generator according to the definition de- long scan chains are often split into several shorter scan chains
scribed in Section II-A. If the number of conflicting inputs to reduce test application time. Splitting a long scan chain
is smaller than or equal to is a positive integer, into several shorter scan chains does not change the number of
then mark all faults detected by test cube and go to Step minterms in the on-sets of functions for the decoding logic if the
4). order of scan flip-flops in the original scan chain is preserved
7) . Update generator and generate in every split scan chain. Fig. 9(a) shows a generator and its
3-weight WRBIST patterns by using . Run corresponding , and values for a circuit with
fault simulation to drop the faults that are detected by the 13 scan flip-flops that are connected into a single scan chain.
generated 3-weight WRBIST patterns. and go to If we assume that and are initialized to 1 and 0,
Step 3). respectively, (the initial values of and are given in the
columns in Fig. 9) before each scan shift operation starts,
V. EXTENSION TO CIRCUIT WITH MULTIPLE SCAN CHAINS then the function of the decoding logic for the generator has
The proposed TPG can be extended for circuits with multiple four minterms in its on-set ( is assigned a 1 only for one scan
scan chains by constructing STUMPS-like scan-path archi- input and is assigned 1’s for three scan inputs ,
tecture [1]. Fig. 8 illustrates a straightforward implementation and ). Now assume that the scan chain is split into two scan
of the proposed TPG for a scan design with scan chains, chains and between scan inputs and so that chain
, where the fixing logic of each scan chain is composed of and chain is composed
is controlled by a separate decoding logic output pair of as shown in Fig. 9(b). denotes th scan
and . Hence the decoding logic of 3-weight WRBIST has input of scan chain , where 1 and 2. Note that we simply
WANG: BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE 785

split the longer scan chain into two shorter scan chains keeping
the order of scan flip-flops in the original scan chain. The values
required at , and , where 1 and 2, for the two scan
chain version of the circuit are shown in Fig. 9(b) (assume that
the two pairs of flip-flops / and
are initialized both to 1 and 0, respectively, before a scan shift
operation starts). The function of the decoding logic for the
two scan chain version also has four minterms on its on-set.
(However, the two scan chain version will require one more
fixing logic, which can however be implemented with very little
hardware.) As this example shows, the number of minterms in
the on-sets of functions for the decoding logic does not change
substantially unless there are drastic changes in the order of
scan flip-flops, even if long scan chains are split into shorter
scan chains.
In the previous paragraph, we assume that the decoding logic
is designed such that a separate pair of outputs and are
assigned for each scan chain , where . How-
ever, it is not necessary to assign a separate pair of outputs to
each scan chain. In the following, we present a method, which
is based on compatibility analysis, to reduce the number of out-
puts of the decoding logic for circuits with multiple scan chains
to reduce hardware overhead.
If the value assigned at every scan input of scan chain
, where , is identical to the value assigned at the
corresponding scan input of another scan chain in every
generator , where , where is the
number of generators, then scan chain is said to be compat- Fig. 10. Merging compatible scan chains. (a) Generators before merging. (b)
ible with scan chain (don’t care is identical to any value Graph representation of compatible scan chains. (c) Generators after merging.
, and ). Otherwise, scan chains and are not com- (d) Decoding logic for merged scan chains.
patible. For example, in Fig. 10(a), which shows a set of gen-
erators computed for a circuit with four scan chains ,
and , the value assigned at every scan input in scan chain compatible scan chains. Reducing the number of outputs of the
, where , is identical to the value assigned at decoding logic by merging compatible scan chains can reduce
in every generator and . Scan hardware overhead for the decoding logic. In this paper, mini-
inputs and , where , are also assigned mizing the number of outputs of the decoding logic is achieved
identical values in every generator. Hence, scan chains and by finding maximal numbers of compatible scan chains, which
and also and are compatible pairwise. In Fig. 10(b), can be formulated as the clique problem [33]. If a set of com-
the nodes represent the scan chains and the arcs depict compat- patible scan chains are merged to be driven by the same pair
ibility relationships between scan chains (if scan chain and of decoding logic outputs, then generators for the merged scan
scan chain are compatible with each other, then the node for chains are also updated accordingly as follows. If input
scan chain and the node for scan chain are connected by is assigned a care value , where , in generator
an arc). denotes the value assigned at th scan input of scan , then values for all th scan inputs of the scan
chains that are merged together are updated to in the new gen-
chain in generator . denotes that is
erator. Fig. 10(c) shows the new generators after generators of
identical to while denotes that is not iden-
compatible scan chains are updated. Fig. 10(d) shows an im-
tical to . Scan chains and are not compatible because
plementation of 3-weight WRBIST for the merged generators
while input of scan chain is assigned a 0 in ,
shown in Fig. 10(c). Since the circuit has four scan chains, the
i.e., of is assigned a 1 in the same generator,
3-weight WRBIST has four fixing logics. However, since the
i.e., . and are assigned nonidentical values at
two pairs of compatible scan chains and , and and
other inputs too;
are merged, the decoding logic has only two pairs of outputs,
, and .
, and .
If scan chain is compatible with scan chain , then the
fixing logics for scan chains and can share a common de-
coding logic output pair. Note that in Fig. 10(d), the inputs of VI. EXPERIMENTAL RESULTS
flip-flops for compatible scan chains and ( and ) are Table I compares results obtained by applying test sequences
driven by the same output pair and ( and generated by regular LFSRs (LFSR sequences, for short)
) of the decoding logic. If a circuit has a large number and results obtained by applying test sequences generated
of scan chains, then typically there are also a large number of by the proposed TPGs (the proposed TPG sequences, for
786 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007
TABLE I
COMPARISONS WITH LFSR GENERATED PATTERNS (SINGLE SCAN CHAIN)
short). Columns under the heading LFSR give results of LFSR
sequences while columns under the heading proposed give
results of proposed TPG sequences. The column # pat under
the heading LFSR shows the number of test patterns generated
by the LFSR and the column % shows fault efficiency
achieved by the LFSR sequence. Fault efficiency is defined
as the number of detected faults / the number of total
faults the number of untestable faults . The average number
of transitions per cycle is given in the column # Aver. Trans..
This number includes the number of transitions caused not
only by test patterns being scanned in but also by responses
being scanned out. The number of transitions at signal lines
are weighted by the number of fanouts in each stem. Hence, if
a fanout stem that drives branches has a transition, then the
transition is counted as rather than 1. Total CPU time spent
to synthesize the proposed TPG is shown in the columns run
time (sec) in seconds. All experiments were run on a 1.6-Ghz
Sunfire V 440 workstation with 8 GB of RAM.
For each circuit, we implemented two different proposed
TPGs each of which is comprised of a different LT-RTPGs:
one comprised of 2-input AND gate and the other comprised of
3-input AND gate (see Fig. 7). Results obtained by the proposed
TPG with a 2-input (3-input) AND gate LT-RTPG are shown
in the columns under the heading . The same
number of test patterns were generated by both 2-input AND
gate LT-RTPG and 3-input AND gate LT-RTPG for each circuit
(to drop easy-to-detect faults). The number of test patterns
generated by the LT-RTPG is given in the column LT-RTG
# pat. Fault efficiency achieved by the LT-RTPG sequence is
shown in the columns LT-RTG FE%.
100% single stuck-at fault efficiency was achieved by the pro-
posed TPG sequence for every benchmark circuit. In addition
to stuck-at fault efficiency, we computed transition delay fault
efficiency achieved by the same sequence of test patterns. Tran-
sition delay fault efficiency is given in the columns Trans dly
FE%. To compute transition delay fault efficiency, test patterns
generated by the proposed TPG were applied to scan chains
by the skewed-load approach [34] (or the launch-off-shift). It
is interesting to see that even though the proposed ATPG is
not designed for transition delay fault model, transition delay
fault efficiency achieved by the proposed TPG is very close
to 100% for every circuit. Columns tot. # pat. give the total
number of test patterns, which includes both LT-RTPG patterns
and 3-weight WRBIST patterns, generated by the proposed
TPG to achieve 100% stuck-at fault efficiency. The columns #
gen show the number of generators that were generated by the
proposed ATPG (see Section II-C). The results on the number
of test patterns clearly demonstrate that the proposed TPG
can achieve high fault coverage with significantly fewer test
patterns than the LFSR. The average number of transitions per
test cycle is shown in the columns Switching as a fraction of
average number of transitions caused by LFSR sequences. Both
LT-RTPG and 3-weight WRBIST test sequences significantly
reduced switching activity in every circuit. Test sequences
that are generated by the 2-input (3-input) AND gate LT-RTPG
caused on average 33% (54%) fewer transitions than LFSR
generated test sequences. The 3-weight WRBIST generated
sequences also significantly reduced the number of transitions
(by average 47%). Note that larger reduction in the number of
transitions is achieved for large circuits. These results clearly
demonstrate that the proposed TPG can achieve high fault
coverage and also efficiently reduce excessive switching ac-
tivity that may occur during BIST. Hardware overhead for the
proposed TPG is presented in Table II.
For the experiments shown in Table II, we made three dif-
ferent versions of circuit for each benchmark circuit each of
which has a different scan chain length: one with only single
scan chain, one with scan chain length of 128, and finally one
with scan chain length of 64. Unlike [26] where scan flip-flops
are reordered to minimize hardware overhead, in this paper
scan flip-flops are routed in the original order (the order scan
flip-flops appear in the circuit). Columns # chains give numbers
of scan chains in the versions that have multiple scan chains.
Numbers of scan flip-flops in scan chains are balanced in all
multiple scan chain circuits. Compatible scan chains were
merged together to minimize hardware overhead as described
in Section V. Columns # Dec output give the number of output
pairs of the decoding logic. The results for the proposed TPG
with 2-input (3-input) AND gate LT-RTPG are shown in the
rows (3). The decoding logic circuits were obtained by
running SIS [35] for two-level circuit implementations. Area
overhead of the synthesized decoding logic is reported in gate
equivalents (columns labeled GE). Only NAND gates, NOR gates,
and inverters were used to synthesize the decoding logics. The
gate equivalents are computed in the manner suggested in [9]:
0.5 for an -input NAND or NOR gate and 0.5 for an inverter.
If a circuit has large number of scan chains, then typically
there are many compatible scan chains that can be merged
WANG: BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE 787

TABLE II
EXPERIMENTAL RESULTS FOR PROPOSED TPG WITH MULTIPLE SCAN CHAINS

TABLE III
COMPARISONS WITH PRIOR WORK

together (see Section V). Note that numbers of output pairs
of decoding logics (columns # Dec output) for multiple scan
chain versions of large benchmark circuits such as s38417 and
s38584 are much smaller than numbers of scan chains in these
circuits (versions) since many scan chains are compatible and
thus merged together. Even if there are no merged scan chains
(the number of scan chains is the same as that of decoding
logic output pairs), gate equivalents of the decoding logic
for versions that have shorter scan chains are slightly smaller
than those of decoding logics for versions with longer scan
chains. For example, even though no scan chains are merged in
either 128 or 64 scan chain length version of s5378 and s9234,
gate equivalents of decoding logics for single scan chains are
slightly larger than those of decoding logics for 128 scan chain
length versions and gate equivalents of decoding logics for 128
scan chain length versions are in turn slightly larger than those
of decoding logics for 64 scan chain length versions. Average
numbers of transitions are shown in the columns under the
headings #Trans.; columns LT-(3W-) give average numbers of
transitions per test clock cycle caused by LT-RTPG test se-
quences (3-weight WRBIST sequences). In general, LT-RTPG
sequences cause smaller numbers of transitions for versions
that have shorter scan chains.
Table III compares the proposed method with recent prior
work [12], [36]–[38]. Like the proposed TPG, the TPGs pro-
posed in [12] and [36] also achieve 100% fault efficiency for
every ISCAS’89 benchmark circuit. Unlike the proposed TPG,
since either [12] or [36] does not consider power dissipation
during BIST. Hence direct comparisons of the proposed TPG
with [12] and [36] may not be fair. For s9234, s15850, and
s38417, the gate equivalents of the proposed TPG are signifi-
cantly smaller than those of [12] while the gate equivalent of
[12] is much smaller than that of the proposed TPG for s13207
and s38584. Note that the gate equivalent of the proposed TPG
for s38417, the largest circuit, is smaller than half the gate equiv-
alent of [12] while the number of patterns to achieve 100% is
even smaller than that of [12]. The gate equivalents of [36] are
a little smaller than those of the proposed TPG for most circuits
except s9234 and s15850. The gate equivalent of [36] for s9234
is significantly smaller than that of the proposed TPG while the
gate equivalent of [36] for s15850 is even larger than that of the
proposed TPG.
The TPGs proposed in [37] and [38] can reduce switching
activity during BIST. The columns % AP reduction show re-
duction in the average number of transitions against regular
LFSRs. Fault efficiency and coverage achieved are shown in the
columns FE% and FC%. Even though more test patterns were
applied than the proposed TPG, fault efficiencies (coverages)
achieved by the TPGs proposed in [37] and [38] are much lower
than 100%. The proposed TPG (with LT-RTPG with )
achieves even larger reduction in the average number of transi-
tions than [36]. The TPG [37] achieves larger reduction in the
average number of transitions than the proposed TPG.
Table IV shows experimental results for three industrial de-
signs. The column grid cnt gives the size of each design in the
number of grids (the grid count does not include area occu-
pied by embedded memories) and the column # FFs gives the
number of scan flip-flops in the design. The column # Init pat
788 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007
TABLE IV
EXPERIMENTAL RESULTS ON INDUSTRIAL DESIGNS (3-WEIGHT BIST)
gives the number of test patterns that were generated to detect
easy-to-detect faults and the column Init FC % gives fault cov-
erage achieved by the initial test sequence. The number of test
patterns generated by the 3-weight BIST to detect the faults re-
maining undetected by the initial test sequence is reported in the
column # 3W pat and final fault coverage achieved is reported in
the column Final FC%. The column is the maximum number
of conflicting bits allowed in each test pattern. The column 3-W
Area reports area overhead for the 3-weight BIST in grid count
and also in percentage to the grind count of benchmark circuit
(shown in the parenthesis in the same column). Area overhead
for 3-weight WRBIST for large designs such as and is
only about 2% or even less. Note that the grid count reported
in the column grid cnt does not include area occupied by em-
bedded memories. Hence real area overhead for 3-weight WR-
BIST will be even less. The experimental results clearly show
that the proposed TPG can be implemented for large industrial
designs with low hardware overhead. Since a simulation tool
that can calculate the number of transitions during scan testing
for large industrial designs is currently not available to us, the
number of transitions is not reported.
VII. CONCLUSION
This paper presents a low hardware overhead TPG for scan-
based BIST that can reduce switching activity in CUTs during
BIST and also achieve very high fault coverage with a reason-
able length of test sequence. Unacceptably long test sequences
are often required to attain high fault coverage with pseudo-
random test patterns for circuits that have many random pattern
resistant faults. The main objective of most recent BIST tech-
niques has been the design of TPGs that achieve high fault cov-
erage at acceptable test lengths for such circuits. While this ob-
jective still remains important, reducing heat dissipation during
test application is also becoming an important objective. Since
the correlation between consecutive patterns applied to a circuit
during BIST is significantly lower, switching activity in the cir-
cuit can be significantly higher during BIST than that during its
normal operation. Excessive switching activity during test ap-
plication can cause several problems.
The proposed TPG reduces the number of transitions that
occur at scan inputs during scan shifting by scanning in the test
patterns where neighboring bits are highly correlated.
The proposed BIST is comprised of two TPGs: LT-RTPG
[23] and 3-weight WRBIST [27]. Test sequences generated by
the LT-RTPG detect easy-to-detect faults. Faults that escape
LT-RTPG test sequences are detected by test patterns generated
by the 3-weight WRBIST. The number of weight sets (gener-
ators) is minimized by guiding the proposed ATPG with cost
functions that reflect the number of conflicting inputs to be in-
curred by setting an input to a binary value. An algorithm to
design the 3-weight WRBIST that requires minimal hardware
overhead and whose patterns cause minimal number of transi-
tions during scan shift cycles is presented. Hardware overhead
for the proposed TPG is further reduced by identifying compat-
ible scan chains in multiple scan chain designs. Experimental re-
sults for ISCAS’89 benchmark circuits demonstrate that the pro-
posed BIST can significantly reduce switching activity during
BIST while achieving 100% fault coverage for all benchmark
circuits. Larger reduction in switching activity is achieved for
large circuits, which have long scan chains. The proposed BIST
structure does not require modification of mission logic which
can cause performance degradation. Experimental results for
large industrial circuits demonstrate that the proposed TPG can
significantly improve fault coverage of LFSR generated test se-
quences with low hardware overhead.
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Seongmoon Wang received the B.S. degree in elec-
trical engineering from Chungbuk National Univer-
sity, Chungbuk, Korea, in 1988, the M.S. degree in
electrical engineering from Korea Advanced Institute
of Science and Technology, Daejeon, Korea, in 1991,
and the Ph.D. degree in electrical engineering from
University of Southern California, Los Angeles, in
1998.
He is currently a Senior Research staff member at
NEC Laboratories America, Princeton, NJ. He was
previously a Design Engineer at GoldStar Electron,
Korea, and a DFT Engineer at Syntest Technologies, Sunnyvale, CA, and 3Dfx
Interactive San Jose, CA. His main research interests include design for testa-
bility and computer-aided design.