a

OVERVIEW

SigmaDSP Evaluation Board EVAL-AD1954EB

The signal processing used in the AD1954 is comparable to that found in high end studio equipment. Most of the processing is done in full 48-bit double-precision mode, resulting in very good low level signal performance and the absence of limit cycles or idle tones. The compressor/limiter uses a sophisticated two-band algorithm often found in high end broadcast compressors. An extensive SPI port allows click-free parameter updates, along with readback capability from any point in the algorithm flow. The AD1954 also includes ADIs patented multibit sigma-delta DAC architecture that provides 112 dB SNR and dynamic range, and THD+N of 100 dB. These specifications allow the AD1954 to be used in applications ranging from low end boom boxes to high end professional mixing/editing systems. The AD1954 also has a digital output that allows it to be used purely as a DSP. This digital output can be used to drive an external DAC to extend the number of channels beyond the three that are provided on the chip. The AD1954 operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in either a 44-lead MQFP or a 48-lead LQFP package for operation over the temperature range 40C to +105C.

The AD1954 (EVAL-AD1954EB) evaluation board permits testing and demonstration of the AD1954 3-channel, 24-bit SigmaDSP audio processor. An input signal is required in either optical or coaxial S/PDIF format, or directly via one of three 10-pin headers in I2S, left-justified, right-justified, or DSP modes. The internal signal processing program and parameters of the AD1954 can be controlled by a 25-lead SPI interface to a computers parallel port. Power requirements are a 9 V to +12 V DC source for both the analog and digital sections. On-board regulators drive separate clean 5 V DC supplies for the digital and analog sections. Three analog RCA phone jacks provide analog audio output. Digital output comes from optical and RCA jacks in S/PDIF format.
AD1954 OVERVIEW

The AD1954 is a complete 26-bit, single-chip, 3-channel digital audio playback system with built-in DSP functionality for speaker equalization, dual-band dynamics processing (compressor/expander/limiter/noise gate), delay compensation, and spatial enhancement. These algorithms can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality.

FUNCTIONAL BLOCK DIAGRAM

D1 VERF D2 EMP EXT. INPUTS J14 J15 J16 D3 ZERO

U3 74HC04 INPUT J1 U2 S/PDIF RECEIVER U2 TORX173 OUTPUT J2 U6 U4 S/PDIF TRANSMITTER U13 M4A5-128/64 INTERFACE PLD

U3 74HC04 MCLK0 MCLK1

S2 MUTE

S3 DE-EMPHASIS

U8A OP275 U7

604

LEFT J3

MCLK2

AD1954
SIGMA-DSP

U8B OP275

604

RIGHT J4

U12 ADM811 SW1 RESET SW2 SW3 J12-SPI INTERFACE J13

U9A OP275

604

SUB J5

U5 TOTX173

U15 74AC244 DATA OUTPUT

SigmaDSP is a trademark of Analog Devices, Inc. Protected by U.S. Patent No. 5,969,657; other patents pending.

J17 CODEC INTERFACE

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002

EVAL-AD1954EB
PERFORMANCE SPECIFICATIONS

The typical evaluation board performance is tabulated below. 1. SNR 2. DR, A-Weighted 3. THD + N 4. Frequency Response 5. Noise Floor 112 dB 1 dB 112 dB 1 dB 100 dB 2 dB 0.2 dB, 20 Hz to 20 kHz (0 dBFS) 145 dB

Twenty-lead header J17 is for interfacing to an Analog Devices codec evaluation board. This connection can be used to supply two serial data lines from external ADCs and all of the necessary clocks to the AD1954 evaluation board, as well as to send the serial data to the external DACs. Headers J6 and J7 are for future expansion and functionality of the evaluation board.
EXTERNAL SPI CONTROL PORT

6. Full-Scale Audio Output 2.0 VRMS

FUNCTIONAL DESCRIPTION

The AD1954 evaluation board presents a reference design that can be used as a suggested layout and circuit implementation that will deliver optimal performance from the SigmaDSP audio processor. As far as is possible, current assembly methods and components are used on the evaluation board. Most components are surface-mount devices, although there is a version of the evaluation board that uses through-hole components in the output filters, and a four-layer printed circuit board is used with full internal power and ground planes for superior noise performance. A schematic, bill of materials, and PCB plots are included for guidance.
POWER SUPPLIES

The AD1954 evaluation board includes a 25-lead header that interfaces the chips SPI input with a computers parallel port. This port is capable of full read/write operation for all of the memories (program and parameter) and some of the SPI registers. Most signal processing parameters are controlled by writing new values to the parameter RAM using the SPI port. Other functions, such as volume and de-emphasis filtering, are programmed by writing to SPI control registers. Details of signal format and timing can be found in the AD1954 data sheet.
AUDIO SIGNAL OUTPUTS

The board is divided into analog and digital sections, with common power supplies. The power supply is input via binding posts J8, J9, and J10. The recommended supply settings are +12 V DC with a maximum current of 350 mA and 12 V DC with a maximum current of 50 mA. An on-board, low noise voltage regulator (U11) provides 5 V DC, 5% to the evaluation board circuit.
DIGITAL SIGNAL INPUTS AND OUTPUTS

RCA jacks J3, J4, and J5 provide left, right, and subs outputs, respectively. The output is low pass filtered with an anti-image filter, and converted from a differential voltage output to singleended voltage by op amps U8 and U9. The left and right channel filters 3 dB cutoff frequency is 100 kHz and has an approximate third order Bessel (linear phase) response. The subwoofer channel uses the same filter but with a 3 dB cutoff at 10 kHz. The output impedance is approximately 600 . The full-scale output signal is 2.0 Vrms for all channels.
SWITCH AND JUMPER FUNCTIONS

RCA phone jack J1 and optical TOSLINK input U1 may be used for standard consumer mode S/PDIF input signals. J1 is terminated with a 75 resistor. Switch S1 selects between J1 and U1 inputs and feeds the selected signal to the digital interface receiver (U2). The EXT DATA INTF 1/2/3 (J14, J15, and J16) inputs permit access, buffered via U13, to the BCLK, LRCLK, SDATA, and MCLK inputs of the AD1954. This permits testing with leftjustified, I2S, or right-justified serial input modes. Note that switch SW3 must be set to correspond to the input data format. When using the direct input header, it is necessary to provide all four signals: MCLK, BCLK, LRCLK, and SDATA. A termination network consisting of a series-connected 100 resistor and a 47 pF capacitor is shunted across each signal line to reduce line reflections. Digital audio signals are output through the RCA phone jack J2 or TOSLINK output U5. Both output jacks are always on, so no switch is needed to select between the two. The transformer (U6) on the output buffers the external connection from the rest of the evaluation board to prevent a ground loop. Header J13 is for the serial data output from the input MUX and the data capture serial output. Either of these two signals, coupled with the left/right clock and bit clock signals, form a valid 3-wire output. This header can be used to connect an external DAC to the AD1954 evaluation board.

A quick reference for the default switch and jumper positions is shown in Table I. These settings should be used for a first-time use of the evaluation board. All directional references assume that the board is facing, with the digital connections on the left and the analog connections on the right. A more detailed description of each switch and jumper follows.
Table I. Default Switch/Jumper Positions

Jumper/Switch Position S1 S2 S3 S4 S5 SW2 SW3 LK2 LK5 LK6 LK9 LK10 LK11 Down Right Right Dont Care Dont Care 0 0 B (Right) On (Down) Off (Up) C (Bottom) B (Right) B (Right)

Setting RCA Input Mute Off De-Emphasis Off For Future Functionality For Future Functionality See Tables II and III See Table IV 5V AVDD Reference XREF Off DIR_MCLK MCLK1_INTF MCLK2_INTF

Slide switch S1 selects between the RCA S/PDIF input and the TOSLINK input.

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Push button switch SW1 provides a RESET function via reset generator U12 (ADM811) and a clean 240 ms delay after release. U12 also provides a 240 ms reset pulse at power-up. A 16-position rotary switch (SW2) controls the signal routing on the evaluation board. The source of the SDATA, BCLK, and LRCLK signals for each of the three MUXes is indicated in Table II. Table III shows the source of signals driving the CS8404A (U4, S/PDIF digital output transmitter). In each of these two tables, the column entries are the signal sources and the headings are the signal destinations for a given switch position. Note: Switch positions BF are not used.
Table II. SW2 SettingsSignal Sources

Switch S2 enables the AD1954 mute function. Switch S3 is used to turn on the AD1954 de-emphasis filter. Push-button switch SW4 and switches S4 and S5 are not currently functional but will be used in future evaluation board revisions. Jumper LK2 selects between an external supply (Position A) or a 5 V input (Position B) to the AD1954s ODVDD pin. ODVDD is the supply for the digital output pins. Using an external supply at 3 V allows the outputs to be 3.3 V compatible. The switch should be left in the 5 V position if no external power supply is connected to the EXT side of the jumper. Jumper LK9, LK10, and LK11 select between internal and external MCLK inputs to the MCLK MUX for MCLK0, MCLK1, and MCLK2, respectively. For LK9, Position A selects the MCLK0_INTF from External Data Interface 0 (J14), Position B selects the MCLK from the codec interface header (J17), and Position C selects the recovered DIR_MCLK from the S/PDIF receiver (U2). For LK10 and LK11, in the left Position (A), the DIR_MCLK signal from U2 is selected. Position B selects the MCLKx_INTF signal from external data header J15 and J16. Jumpers LK5 and LK6 connect the reference voltage to the VREF_IN pin. If LK5 is on, then the voltage will come from AVDD. With LK6 on, the reference voltage will be taken from the external reference Test Point 1 (TP1).
INDICATOR DISPLAY LEDS

SW2 Pos. 0 1 2 3 4 5 6 7 8 9 A

MUX 0 CS8414 (U2) Ext. port 0 Ext. port 0 Ext. port 0 CS8414 (U2) Ext. port 0 Ext. port 0 Ext. port 0 CS8414 (U2) Ext. port 0 Ext. port 0

MUX 1 Ext. port 1 CS8414 (U2) Ext. port 1 Ext. port 1 Ext. port 1 CS8414 (U2) Ext. port 1 Ext. port 1 Ext. port 1 CS8414 (U2) Ext. port 1

MUX 2 Ext. port 2 Ext. port 2 CS8414 (U2) Ext. port 2 Ext. port 2 Ext. port 2 CS8414 (U2) Ext. port 2 Ext. port 2 Ext. port 2 CS8414 (U2)

Five LED indicators are provided for status indication. Display LED D1, VERF, indicates that the S/PDIF digital interface receiver has detected an error condition in the received signal. When not illuminated, this LED is a good indicator that there is a signal present on the S/PDIF input. Display LED D2, EMP, indicates that the incoming signal has had pre-emphasis added. Display LED D3, ZERO, is provided to show that the AD1954 is detecting a zero input in one of the two input channels. Display LEDs D6 and D11, DVDD and AVDD, show the presence of 5 V DC on the digital and analog 5 V power supplies, respectively.

Table III. SW2 SettingsCS8404A Signal Sources

SW2 Pos. CS8404 SDI 0 1 2 3 4 5 6 7 8 9 A DCSOUT DCSOUT DCSOUT DCSOUT SDATAOUT SDATAOUT SDATAOUT SDATAOUT DCSOUT DCSOUT DCSOUT

CS8404 CS8404 LRCLK/BCLK MCLK (128 Fs)* 8414 8414 8414 MUX OUT MUX OUT MUX OUT MUX OUT MUX OUT MUX OUT MUX OUT MUX OUT CS8414 (U2) CS8414 (U2) CS8414 (U2) MCLKOUT CS8414 (U2) CS8414 (U2) CS8414 (U2) CS8414 (U2) MCLKOUT MCLKOUT MCLKOUT

INTEGRATED CIRCUIT FUNCTIONS

There are 16 active devices on the AD1954 evaluation board. Following is a brief description of the function of each part. U1 (TORX173) is the Toshiba digital audio optical receiver. It accepts the visible red S/PDIF modulated signal and converts it to a standard TTL digital signal suitable for input to the digital audio receiver (U2). U2 (CS8414-CS) receives the serial S/PDIF digital audio encoded signal and decodes the audio information. The CS8414 decodes four digital signals from the serial input stream: the serial data SDATA, the master clock MCLK, the left/right frame clock LRCLK, and the serial bit clock BCLK at 64 Fs. The output interface mode of U2 must be compatible with the input to the AD1954 (U7). This mode is selected at the same time for both U2 and U7 via switch SW3. U3 (74HC04) is a quad input logic inverter that provides miscellaneous buffering and interface functions.

*MCLK input signals to the CS8404 are divided by two in the PLD because this part runs on 128 Fs, while the rest of the board runs on a 256 Fs MCLK.

Rotary switch SW3 determines what serial interface format is selected. Table IV shows the different modes. Note: Switch positions 6F are not used.
Table IV. SW3 Settings

SW3 Position 0 1 2 3 4 5 REV. 0

Serial Data Format I2 S Right Justified 24-bit DSP Left Justified Right Justified 20-bit Right Justified 16-bit 3

EVAL-AD1954EB
U4 (CS8404A-CS) is the S/PDIF transmitter that takes in the serial data SDATA, master clock MCLK, the left/right frame clock LRCLK, and the serial bit clock BCLK, and outputs the S/PDIF signal to the TOSLINK transmitter and the RCA output jack. U5 (TOTX173) is the Toshiba digital audio optical transmitter. It creates a visible red S/PDIF modulated signal from the standard TTL digital signal output of the digital audio transmitter (U4). U6 (SC937-02) is a digital audio transformer with low jitter and high CMRR that provides buffering between the evaluation board and the external circuit, preventing ground loops. U7 (AD1954) is the SigmaDSP digital audio processor and converter. U8 and U9 (OP275) are low noise and distortion audio op amps. U8 provides differential-to-single-ended conversion for the left and right channel outputs, while U9 does the same for the subchannel. A third order low pass Bessel filter response is implemented with a 3 dB corner frequency of 100 kHz on the left and right channels, 10 kHz on the subchannel, and a 60 dB/decade (18 dB/octave) roll-off. This type of filter is characterized by a linear phase response and fast transient response without overshoot. U10 (LM317) provides 5 V DC low voltage regulation for the digital section of the evaluation board. U11 (ADP3303-5) is a low noise 5 V DC regulator for the analog section of the AD1954. U12 (ADM811) is a RESET generator that provides a debounced reset signal from the push button (SW1) or a 240 ms reset pulse on power-up. U13 (M4A5-128/64) provides decoding, buffering, and selection functions between the different modes of operation. U14 (74HC243) is a quad three-state noninverting buffer. U15 (74AC244) is an octal noninverting buffer/line driver with three-state outputs. U16 (NC7S14) is a high performance inverter with Schmitt trigger input.

SOFTWARE

The AD1954 evaluation board comes with software that can be used to control all of the parts functions. The evaluation board interfaces with this software via the 25-lead header (J12), which connects to a computers parallel port. Custom programming tools are available for the AD1954. A Graphical Compiler, in conjunction with OrCAD, can be used to design custom signal processing algorithms using any of the AD1954s processing blocks. All settings can be programmed with this Graphical Compiler, which writes to the program and parameter RAMs through the SPI port of the AD1954. More in-depth documentation is available for all software.
FURTHER INFORMATION

Ordering information: order number is EVAL-AD1954EB. For application questions, please contact our Central Applications Department at 1-781-937-1428.

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Figure 1. Silkscreen Top Overlay

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Figure 2. Component Top Layer

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Figure 3. Internal Plane 2 Ground Planes

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Figure 4. Internal Plane 3 Power Planes

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Figure 5. Bottom Layer Solder Side

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EVAL-AD1954EB
Bill of Materials

Qty. Used 27

Designator C1, C5C11, C13, C51C54, C56, C58, C61, C64, C66C71, C87C90 C2, C3, C63, C91 C4 C12, C57 C14, C59, C65 C15, C27, C39 C16, C28, C40 C17, C29 C18, C30 C19, C31 C20, C32 C21, C33 C22, C34 C23, C35 C24, C36 C25, C37 C26, C38 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C55, C60, C62 C72C86, C92C96 D1, D6 D2, D3 D11 D7D8 D5, D9D10 J1J5 J8 J9 J10 J7, J11, J13J16 J12 J17 L1L4, L8L9 L5 L6, L7 LK5LK6

Description Multilayer Ceramic 50 V X7R

Part Decal SMD 0805 Case

Value 0.1 F

4 1 2 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 20 2 2 1 2 3 5 1 1 1 6 1 6 1 2 2

Multilayer Ceramic 50 V X7R Multilayer Ceramic 50 V X7R SMD Aluminium Electrolytic Capacitor (Case B) 16 V SMD Aluminium Electrolytic Capacitor (Case D) 16 V Ceramic Chip Capacitor, 5%, 50 V, NPO P-Series Polypropylene Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO Film Chip Capacitor, 5%, 50 V, PPS P-Series Polypropylene Capacitor P-Series Polypropylene Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO P-Series Polypropylene Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO P-Series Polypropylene Capacitor Film Chip Capacitor, 5%, 50 V, PPS P-Series Polypropylene Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO Panasonic PPS (ECHS) Series Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO Panasonic PPS (ECHS) Series Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO Panasonic PPS (ECHS) Series Capacitor Ceramic Chip Capacitor, 5%, 50 V, NPO Panasonic PPS (ECHS) Series Capacitor Film Chip Capacitor, 5%, 50 V, PPS Panasonic PPS (ECHS) Series Capacitor SMD Aluminium Electrolytic Capacitor (Case D) 25 V Ceramic Chip Capacitor, 5%, 50 V, NPO Red Light Emitting Diode Yellow Light Emitting Diode Green Light Emitting Diode SMD Rectifier Diode, 50 V, 1 A, SOD-87 15 V Zener Diode Audio ConnectorRCA Female Right Angle Connector, Binding Post (Uninsulated Base) Connector, Binding Post (Uninsulated Base) Connector, Binding Post (Uninsulated Base) 10-Way (5 2) IDC HeaderShrouded CON\DB25HM 20-Way (10 2) IDC HeaderShrouded Chip Ferrite Bead 600 @ 100 MHz Chip Ferrite Bead 600 @ 100 MHz Do Not Insert Jumper Block, 2 PINS 0.1" SPACING

SMD 0805 Case SMD 0805 Case CAP\ELEK_SMD_B CAP\ELEK_SMD_D SMD 0805 Case CAP-5 mm SMD 0805 Case SMD 0805 Case CAP-5 mm CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm SMD 0805 Case CAP-5 mm CAP\ELEK_SMD_E SMD 0805 Case LED_SMT LED_SMT LED_SMT MELF1 DIODE-SMB PHONO BINDING-POST BINDING-POST BINDING-POST HEADER10-POL DB25-HM SMD 0805 Case SMD 0805 Case SMD 0805 Case SIP-2P

10 nF 68 nF 10 F 47 F 100 pF 100 pF 1 nF 2 n7F 1 nF 2 n7F 270 pF 270 pF 820 pF 820 pF 2n2F 2n2F 270 pF 27 nF 560 pF 56 nF 68 pF 6n8F 150 pF 15 nF 2n2F 220 nF 47 F 47 pF Red Yellow Green 15 V Yellow Green Blue

10

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Bill of Materials (continued)

Qty. Used Designator 7 6 1 1 27 LK1, LK3LK4, LK7 LK8, LK12LK13 LK2, LK10LK11, S2, S4, S5 LK9 S3 R1, R9, R12R14, R43, R47, R49R51, R56R59, R64R67, R72R75, R81, R82, R83, R85, R86 R10 R2 R3 R4R5, R11, R41R42 R6 R7 R8 R15, R23 R16, R24 R17, R25, R34 R18, R26, R36 R19, R27 R20, R28 R21, R29 R22, R30, R38 R31, R33 R32, R35 R37 R39 R40 R44R46, R52R55, R60R63, R68R71, R87R91 R48, R7680 R84 RP1 S1 SW1, SW4 SW23 TP117 U1 U2 U3 U4 U5 U6 U7 U89

Description Do Not Insert Jumper Changeover 1 6-Pin Square Pin Header (3 2) 0.1" Pitch Jumper Changeover 1 Chip Resistor 1% 100 mW Thick Film

Part Decal SIP-2P LINK-3P

Value

LINK-3P SMD 0805 Case

10.0 k

1 1 1 5 1 1 1 2 2 3 3 2 2 2 3 2 2 1 1 1 20

Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Resistor Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film

SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case SMD 0805 Case

10.0 k 75 475 649 374 90.9 k 8.25 k 2.80 k 806 3.01 k 1.50 k 1.00 k 499 549 OPEN 11.0 k 5.62 k 604 243 715 100 22.1 100 k 10 k

6 1 1 1 2 2 17 1 1 1 1 1 1 1 2

Chip Resistor 1% 100 mW Thick Film Chip Resistor 1% 100 mW Thick Film RES-PACK8 DPDT PCB Switch (Top Actuator) SMD Push Button Switch (Sealed 6 mm 6 mm) HEX Rotary Switch Testpoint Fiber Optic Receiving Module for Digital Audio 96 kHz Digital Audio Receiver HEX INV 96 kHz Digital Audio Transmitter Fiber Optic Transmitting Module for Digital Audio Digital Audio Signal Transformer (AES/EBU) AD1954 SigmaDSP Dual Bipolar/JFET Audio Op Amp 11

SMD 0805 Case SMD 0805 Case SIP-9P SW-DPDT-SLIDE SW\PB-SMALL SW-ROTARY-HEX TESTPOINT TORX173 SO28WB SO14NB SO24WB TORX173 TRAFFO-SC937-02 LQFP48 SO8NB

TORX173 DIR-CS8414-CS 74HC04 CS8404A-CS TOTX173 TRAFFOSC937-02 AD1954YST OP275GP

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Bill of Materials (continued)

Qty. Used 1 1 1 1 1 1 1 4

Designator U10 U11 U12 U13 U14 U15 U16

Description Three Terminal Adjustable Regulator Precision Low Dropout Voltage Regulator Voltage Monitor CPLD Quad Bus Transciever Three-State Noninverting Octal Buffer/Line Driver Three-State Outputs NC7S14 PCB Standoffs

Part Decal D-PAK SO8NB SOT143 QFP100-3 SO14NB SO20WB SOT23-5

Value LM317 ADP3303AR-5 ADM811R-ART CPLD-M4A5128/64-10YC 74HC243 74AC244 NC7S14

12

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DVDD DVDD LK1 R4 649 600Z L2 C5 0.1F 2
22 7

DVDD

600Z L1 R5 649 D1 RED VERF D2 P/EMP YELLOW 4 U3-B 74HC04 1 3 C7 0.1F 8 DVDD DVDD 19 VD+
6 SCK 7 LRCK 8

C1 0.1F 600Z L3 C6 0.1F

R1 10.0k

DVDD U1 SHLD1 TORX173 SHLD2 OUT 2 DGND1 4 DGND2 U3-A 74HC04

26

S1 C2 10nF VA+
9

VD+ DVDD

J1 C3 10nF
10

RXP

Figure 6. Evaluation Board, S/PDIF Interfaces

RXN
23 24 18 17

13
20

R2 75

SDATA 11 FSYNC 12 SCK 19 MCK

8414_SDO 8414_LRCLK 8414_BCLK 8414_MCLK

C8 0.1F

600Z L4
3

FILT 9

M0 M1 M2 M3 8414_M0 8414_M1 8414_M2 8414_M3 U3-D 74HC04

R3 475 C U CBL VERF ERF

8404_BCLK 8404_LRCLK 8404_SDI

SDATA
15 CBL 16

DVDD 5 CASE1 U5 6 TOTX173 CASE2 RESETB DIT_MCLK RST

4 5

R8 8.25k INPUT MCLK

9 10 V C 11

1 14 15 28 25

C4 68nF

PR0 C7/C3 C1/FC0 C6/C2 CRE/FC1 C9/C15 EM1/C8 EM0/C9 U U4 CS8404

2 1 3 4 24 12 13 14

RLIMIT DGND 1
20

TXP

21

TXN 17 8404_M0 8404_M1 8404_M2

21 M0 22 M1 23

AGND DGND U2 DIR-CS8414

CO/E0 CA/E1 CB/E2 CC/F0 CD/F1 CE/F2 SEL CS12/FCK

6 5 4 3 2 27 16 13

R6 374 M2 GND 18 R7 90.9

2 U6 1 4 5 HI J2 8 LO 6 TRAFFO-SC937-02

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DVDD LK2 ODVDD_EXT
A B

AVDD

EXT 5V ODVDD LK3 C9 0.1F C10 0.1F

LK4

600Z L8

C11 0.1F

44

32

22

30

0DVDD MCLK2 MCLK1 MCLK0 SDATA2_DUT BCLK2_DUT LRCLK2_DUT DVDD R11 649 D3 ZERO YELLOW U3-C 74HC04 DVDD S2 5 SDATA1_DUT BCLK1_DUT LRCLK1_DUT SDATA0_DUT BCLK0_DUT LRCLK0_DUT SDATAOUT BCLKOUT LRCLKOUT SCOUT_TRAP MCLKOUT CDATA_DUT CCLK_DUT CLATCH_DUT COUT_DUT RESETB AUXDATA DVDD S3 R10 10.0k
2 3 4 8 9 10 11 12 14 15 16 17 41 42 43 45 47 18 19 20 46 40 21 6 5

DVDD

AVDD

AVDD

AVDD VOUTL+ 33 VOUTL 34 VOUTR+ 29 VOUTL+

MCLK2 MCLK1 MCLK0 SDATA2 BCLK2 LRCLK2 SDATA1 BCLK1 LRCLK1 SDATA0 BCLK0 LRCLK0 DMUXO BMUXO LRMUXO DCSOUT MCLKOUT CDATA CCLK CLATCH COUT ZEROFLAG RESETB MUTE DEEMP/AUXDATA

VOUTL

VOUTR+ AVDD TP1 XREF

U7

AD1954

VOUTR 28 VOUTS+ 26 VOUTS 25 VREF_IN 38 FILTCAP 39

VOUTR

VOUTS+ VOUTS

LK5 R12 10.0k

LK6 R14 10.0k

R13 10.0k

+ C14 47F

R9 10.0k

C12 10F

C13 0.1F

MUTE

DGND DGND AGND AGND AGND AGND

13 48 23 27 31 35

DEMP

600Z L5 600Z L6

Figure 7. Evaluation Board, DUT

14

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R17 3.01k R18 1.50k
+12V +12V C51 0.1F 6 5 LK13 12V 12V C53 0.1F

VOUTL TP12 6 7 5 OP275 C25 2n2F PPS R22 OPEN C26 2n2F PP-MF J3 C18 2n7F PPS R20 499 C23 820pF NPO VOUTS R31 11.0k R33 11.0k R34 3.01k C24 820pF PP-MF C45 68pF NPO C20 2n7F PP-MF
C52 0.1F C54 0.1F

R15 2.80k

C21 2n7F NPO

LK12

C22 270pF PP-MF

C17 1nF NPO U8-B R21 549 LOUT

8 V+ U8-C OP275 V 4 8 V+ U9-C OP275 V 4

C19 1nF PP-MF

U9-B OP275

C15 100pF NPO

C16 100pF PP-MF

VOUTL+ R19 1.00k C46 6.8nF ECHS

R16 806

TP14 2 3 U9-A 1 R37 604 SUB J5 OP275

C39 100pF NPO R25 3.01k R26 1.50k VOUTS+ R32 5.62k TP13 2 1 3 OP275 C37 2n2F PPS C30 2n7F PPS R28 499 C35 820pF NPO C36 820pF PP-MF C32 2n7F PP-MF C38 2n2F PP-MF U8-A R29 549 ROUT J4 R30 OPEN C33 270pF NPO C34 270pF PP-MF C43 560pF NPO

C40 100pF PP-MF

C41 270pF NPO

C42 27nF ECHS

Figure 8. Evaluation Board, Analog Output Section

C44 56nF ECHS R36 1.50k R35 5.62k C29 1nF NPO C31 1nF PP-MF C47 150pF NPO C48 15nF ECHS R27 1.00k

15

VOUTR

R23 2.80k

C49 2n2F PPS

C50 220nF ECHS

R38 OPEN

C27 100pF NPO

C28 100pF PP-MF

VOUTR+

R24 806

EVAL-AD1954EB

EVAL-AD1954EB
U10 LM317 3 + D5
1SMB15AT3 15V

DVDD DVDD 2 R39 243 C59 47F C58 0.1F U11 ADP3303-5 + TP3 DGND LK7 R41 649 D6 RED DVDD C66 0.1F DVDD 4 VCC 3 MR RESET GND 2 1 LK8 R43 10.0k RESETB

C55 47F 25V

C56 0.1F

IN OUT ADJ/GND 1

SW1

C57 + 10F

R40 715

TP4 J8 YELLOW

L9 600Z VIN+ D7

L7 600Z

AVDD

+12V

+ TP5 COM J9 GREEN TP6 J10 VIN BLUE D8 D10

1SMB15AT3 15V

D9

1SMB15AT3 15V

C60 47F 25V

1 OUT1 2 8 IN1 OUT2 7 6 IN2 ERROR 5 3 C61 SD GND NR 0.1F TP7 4 AGND + C62 47F

C63 10nF

C64 0.1F C65 + 47F

R42 649 D11 GREEN AVDD

12V

Figure 9. Evaluation Board, Power Supply Section

16

REV. 0

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56

BCK0

SDO

LRCK0

I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39

Figure 10. Evaluation Board, CPLD Section

DVDD RP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

REV. 0
LRCLK2_INTF DVDD CDATA-UC CCLK-UC
C67 0.1F

BCLK2_INTF SDATA2_INTF SDATA1_INTF BCLK1_INTF LRCLK1_INTF SDATA0_INTF BCLK0_INTF LRCLK0_INTF TP2 AUXDATA PIN-84 PIN-83 CLATCH-UC RESETB TDO DVDD TP15 TP16 TP17 TCK

DVDD J11-1 J11-2 TMS J11-3 J11-4 TDI J11-5 J11-6 TDO DVDD J11-7 J11-8

COUT-UC UCSEL4

DVDD

TDI ASDATA2 UCSEL1 8414_SDO 8414_LRCLK 8414_BCLK 8414_M3 8414_M2 8414_M1 8414_M0 DIR_MCLK

LRCLK0_DUT BCLK0_DUT SDATA0_DUT LRCLK1_DUT BCLK1_DUT SDATA1_DUT ABCLK C68 0.1F

U13 CPLD-M4A5-128/64

J11-9 MCLKOUT BCLKOUT SDATAOUT SCOUT_TRAP LRCLKOUT LRCLK2_DUT BCLK2_DUT SDATA2_DUT UCSEL3 ASDATA1 DVDD U3-E 74HC04
11 10

17
C70 0.1F LK9 INT
A B

ALRCLK DIT_MCLK 8404_BCLK 8404_LRCLK 8404_M2 8404_M1 8404_M0 8404_SDI UCSEL2 TMS TCK MCLK0

MCLK0_INTF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND GND TDI I5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND GND GND GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 ENABLE GND GND

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

J11-10

TDM_MCLK DIR
INT B C

C71 0.1F

DIR_MCLK

MCLK1_INTF MCLK1
DIR 2 COM 5 COM 2 COM 5 COM SW2 SW-ROTARY-HEX

U3-F 74HC04
13 12

MCLK1 LK10
A

CLATCH_DUT CDATA_DUT COUT_DUT CCLK_DUT CLATCH_INTF CDATA_INTF COUT_INTF CCLK_INTF DVDD

DIR_MCLK
INT 1 B1 4 B2 3 B4 6 B8

MCLK2_INTF
B A DIR

1 B1 4 B2 3 B4 6 B8

C69 0.1F

MCLK2 LK11

MCLK2

SW2 SW-ROTARY-HEX

EVAL-AD1954EB

DIR_MCLK

SPI INTERFACE (25 WAYD SHELL) DVDD C89 0.1F LRCLK0_INTF BCLK0_INTF MCLK0_INTF R52 100 C75 47pF DVDD R72 10.0 R73 10.0 R53 100 C76 47pF R54 100 C77 47pF R55 100 C78 47pF SDATA0_INTF DVDD R56 10.0 R57 10.0 R58 10.0 R59 10.0

DVDD

EVAL-AD1954EB

R49 10.0k TP8 TP9 TP10

8 B3 9 B2 10 B1 11 B0

R50 10.0k

R51 10.0k

R48 22.1 CDATA_INTF CLATCH_INTF CCLK_INTF TP11

6 A3 5 A2 4 A1 3 A0 13 OEB 1 OEA

J14-1 J14-2 J14-3 J14-4 J14-5 J14-6 J14-7 J14-8 J14-9 J14-10

R74 10.0

R75 10.0 SDATA2_INTF LRCLK2_INTF BCLK2_INTF MCLK2_INTF

U14 74HC243 COUT_INTF R45 100 C73 47pF DVDD R64 10.0 R65 10.0 R66 10.0 R67 10.0 SDATA1_INTF LRCLK1_INTF BCLK1_INTF MCLK1_INTF R60 100 C79 47pF R61 100 C80 47pF R62 100 C81 47pF R63 100 C82 47pF C74 47pF R46 100 R47 10.0k

R44 100

C72 47pF

J12-1 J12-2 J12-3 J12-4 J12-5 J12-6 J12-7 J12-8 J12-9 J12-10 J12-11 J12-12 J12-13 J12-14 J12-15 J12-16 J12-17 J12-18 J12-19 J12-20 J12-21 J12-22 J12-23 J12-24 J12-25 J16-1 J16-2 J16-3 J16-4 J16-5 J16-6 J16-7 J16-8 J16-9 J16-10 R68 100 C83 47pF J15-1 J15-2 J15-3 J15-4 J15-5 J15-6 J15-7 J15-8 J15-9 J15-10 C87 0.1F R68 100 C84 47pF R70 100 C85 47pF R71 100 C86 47pF

Figure 11. Evaluation Board, External Digital Interface

18
ODVDD_EXT R76 R77 R78 22.1 R79 22.1
OE 1

J13-1 22.1 22.1 U15-A 74AC244

J13-2

DSCOUT

J13-3
12 Y3 14 Y2 16 Y1 18 Y0 8 A3 5 A2 4 A1 2 A0

TDMSDATA/SDATAOUT

J13-4

J13-5

TDMFS/LRCLKOUT

J13-6 R80 22.1

3 Y3 5 Y2 7 Y1 9 Y0 17 A3 15 A2 13 A1 11 A0 19 OE

SCOUT_TRAP SDATAOUT LRCLKOUT BCLKOUT

J13-7 U15-B 74AC244

TDMBCLK/BCLKOUT

J13-8

J13-9

J13-10

MCLKOUT ODVDD
20

C88 U15 0.1F

10

REV. 0

EVAL-AD1954EB
C90 0.1F

DVDD J6-13 J6-28 J6-29 J6-1 J6-14 J6-15 J6-18 J6-6 J6-7 J6-8 J6-9 J6-10 J6-22 J6-23 J6-26 J6-27 4 U16 NC7S14 UCSEL1 UCSEL2 UCSEL3 UCSEL4 RESETB COUT-UC CLATCH-UC CCLK-UC CDATA-UC 2 C91 10nF R84 100

PROGRAM SELECT

RESET

SPI CONTROL

INTERRUPT REQUEST DVDD SW4

J17-1 J17-2 J17-3 J17-4 J17-5 J17-6 J17-7 J17-8 J17-9 J17-10 J17-11 J17-12 J17-13 J17-14 J17-15 J17-16 J17-17 J17-18 J17-19 J17-20

ODVDD_EXT BCLKOUT_HEADER SDATAOUT_HEADER DSCOUT DVDD

LRCLKOUT_HEADER

R81 10.0k

R82 10.0k

R83 10.0k

R85 10.0k

R86 10.0k CODEC_MCLK ASDATA2 ASDATA1 ALRCLK ABCLK

J6-5

R87 100 C92 47pF

R88 100 C93 47pF

R89 100 C94 47pF

R90 100 C95 47pF

R91 100 C96 47pF

PIN-83 PIN-84 J6-11 ADC0

S4

TO CPLD

J6-12 J6-21 J6-19 J6-20 J6-24 J6-16 J6-17

ADC1
S5

J7-1 J7-2 J7-3 J7-4 J7-5 J7-6 J7-7 J7-8 DVDD J7-9 J7-10 TO VOLUME/ TONE CONTROL BOARD

ADC2 ADC3 ADC4 ADC5 CREF VREF

Figure 12. Evaluation Board, ADuC812S Interface

REV. 0

19

 20
C0283506/02(0)

PRINTED IN U.S.A.