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Accurate Current Estimation for Interconnect Reliability Analysis

Palkesh Jain, Member, IEEE, and Ankit Jain
AbstractAn improved and efcient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Signicantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily congured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the nets lumped capacitance or the nets effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective EM slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the rst time, we present a method for incorporating the drivers dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure. Index TermsAging, degradation, electromigration, interconnects, reliability, variability.

Fig. 1. Problem space: (a) current source modeling for signal-EM analysis and (b) load abstraction for cell-internal EM analysis.

I. INTRODUCTION VER the past two decades, wire widths of interconnects have reduced by two orders of magnitude and at the same time the device density on the chips has increased by more than ve orders of magnitude. Consequently, the current density in signal wires has increased, thereby making them extremely vulnerable to electro-migration (EM) failures [1]. EM is a process in which mass transport takes place as a result of interaction between the moving electrons and the metal ions at high current densities. Migration of metal ions results in metal build-up or depletion resulting in catastrophic disconnections in the form of hillocks and voids. The classic Blacks equation relates the mean time to failure (MTF, time to a denitive failure) to the average DC current density (AVG) and the absolute temperature of the wire [2]. Additionally, the wire temperature has an inherent squared dependency on the root-mean-square (RMS) current of the signal wire, famously known as Joule heating (JH), [3].

Manuscript received August 11, 2010; revised January 11, 2011; accepted May 28, 2011. Date of publication August 01, 2011; date of current version July 05, 2012. P. Jain is with the External Design and Manufacturing (EDM) Group, Texas Instruments India, Bangalore 560093, India (e-mail: palkesh@ti.com). A. Jain is with the University of Maryland, College Park, MD 20742 USA (e-mail: ankj89@gmail.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2011.2160882

Pioneering work by Hunter, [4], combines AVG, RMS currents and temperature to create self-consistent formulations for EM checking, thus making the analysis independent of peak currents for regular signal interconnects. It can be further noted that while AVG current limits are a strong function of the choice of a designs lifetime and junction temperature requirement, there are no knobs to inuence the RMS current limit, which are set based on a constraint of a nets heating up to 5 C, for example. This, in turn, makes JH an instantaneous problem as well. Past decade has additionally challenged designers to innovatively design the power grid and contain the switching activities to reduce the dynamic and static voltage drop along the grid. Unfortunately, the voltage drop also gets aggravated by EM. Foregoing arguments underline the importance of containing the current densities in modern integrated circuits, and furthermore, the need of an accurate estimation of RMS current and AVG current in assessing a designs EM reliability. EM containment of a design typically relies on ensuring current densities in interconnectsnamely signals, power network and cell-internal, remain within the technology limits, as shown in Fig. 1. The EM limits of interconnect are a complex function of interconnect geometry and surroundings, details of which are shared elsewhere [5]. In this work, we will focus on the automation and computational aspects of the problem. Given the technology limits, EM analysis involves extracting the currents in interconnects when a circuit operates at certain conditions, typically the worst. Thus, for an IP, the driving point admittance (DPA) is often approximated by a lumped capacitance model which is the total capacitance of the RC Intercon-

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nect. However, for heavily loaded nets, it has been established that there are indeed shielding effects and, a new capacitance metric: C-effective is used to compute the IPs delay. Contrary to popular belief, in this work, we present results which suggest either of them being inaccurate, when used for EM assessment. We nd that C-lumped becomes pessimistic for a variety of nets (e.g., multidriven) and C-effective predicts optimistic current ow on several nets. On the other hand, while analyzing signal interconnects for EM, typically, the driver-cells current is modeled which can be either injected into the RC-net structure, or, used for statically estimating the current ow by matrix or related calculations [16]. The parameters of the current model can be determined from the characterization data of the corresponding cell and the RC interconnect in picture. Subsequently, the currents in the signal wires can be estimated by measuring the signal transferred to the impedances [6]. Several models such as the triangular and the rectangular waveforms have been proposed in this context. We nd that these models offer a fairly good picture at low frequencies, but fail for highly resistive nets at high frequencies. To solve above problems, we propose a double exponential waveform [7], [20] based on the properties of RC interconnect and rise-fall times of the driver, and, validate against SPICE simulations for several RC nets. Additionally, we develop closed-form equations for AVG and root-mean-square currents in terms of the nets timing properties for static estimation. This model, thus, enables extremely fast EM checking. Finally, we also report the impact of IR drop on electromigration checking. Poorly designed power-grid and heavy localized switching, while result in the dynamic IR drop, naturally will also degrade the transistor performance, thus reducing the peak current. Our results indicate this reduction could be up to 30% in RMS current computations. In this paper the model implemented has been designed to take care of the changes in power supply by xing the input slew. It should be noted that the accurate waveform-shape and RMS current prediction are of special import for signals, as compared to power-network, since power grid currents are established average currents in longer periods of time, which can be effectively computed through other means [21], [22]. The rest of this paper is organized as follows: in Section two, we do a brief recap of the existing methods and associated shortcomings in the static and dynamic EM computation. Next, in Section III, we rst nd it apt to describe in detail, the implementation for the double exponential waveform model. Section IV outlines the several production design experiments performed and validation with full SPICE Simulations, followed by the practical implementation with existing methods in Section V. Section VI gives an overview on cell internal EM checking. Finally we conclude the paper in Section VII with ongoing and future work.

route tools use a rectangular current waveform with timing specic slew to estimate the current ow, [14]. Triangular waveform assumptions with an effective capacitance approach were proposed in [11]. On the contrary, in [12] and [13] authors use higher order moment matching approximations for current-estimation. The estimation in [10], additionally, is based on the assumption of the current waveform being log-normal in nature. While above work bridges a signicant gap, we note that most of the existing formulations for static current estimation assume that the current ow in a cycle due to a single transition can be approximated by the current ow over an innite period [10], [12], i.e., it assumes that the current in a resistive branch returns to zero after the switching event is over. As we will see later in the paper, this assumption does not hold true for highly resistive nets at very high frequencies. Such nets, while can be identied and xed through a rigorous timing analysis and slew constraints, intentional use of them in certain design styles, e.g., differential or non-rail-rail switching warrants careful analysis. Additionally, an important aspect in either dominant-pole or moment-computation based current estimation is the choice of the driver input waveform. Reference [10], for example, have used a choice of saturated ramp input with a single rise time [10] to approximate the driver output waveform. However, we note up to 10% inaccuracy in practical cases, due to tail effects arising in resistive nets. Consequently, our work bridges this gap and makes the model easily congurable to any driver input waveform. Specically, we share results with several combinations of a ramp and an exponential waveform. On the other hand, [13] propose the static current estimation formulation independent of the current-waveform shape. However, the drawback of such methods remains that the closed form expressions for the currents cannot be derived. It can also be noted that many of above methods either require rst pass DC simulation or typically have problems in handling non-tree topologies. Recursive moment based method, used in this work, along with the concepts of obtaining Thevenin equivalent of meshes allow its application to such circuits [23]. Finally, all of the methods, to our best knowledge, overlook the asymmetrical waveform effects due to different rise and fall times of the driver voltage waveform. In this work, we extend our formulation to naturally account for this asymmetric nature of voltage waveform, which is important for AVG current as well as RMS current perspective. While in majority of the cases, AVG current remains independent of the waveform shape, the asymmetric nature of the voltage waveform have implications on the AVG current due to the asymmetric recovery. Further none of the papers in the extended literature focus on the inaccuracies arising in the computation of RMS currents due to dynamic IR drop. Keeping in mind the importance of accurate RMS current estimation, the errors due to IR Drop can be considerable. In this paper, an attempt has been made to model the input slew as a function of supply voltage drop thereby minimizing the error in current computation. III. IMPLEMENTATION In this work, we choose to capture the fundamental properties of any RC circuit by using an exponential model having two different rise and fall times. The current components arising due to drift and diffusion of electrons give way to a double exponential

II. PRIOR ART Owning to extravagant runtimes of full-blown SPICE simulations for reliability analysis, [8], many static and pseudo-dynamic analysis methods [9][13] for current computations have been proposed in literature. Starting from ab-initio, place-and-

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waveform as described in (1), [7], and [20]. The double exponential waveform depends on three parameters: rise time , fall time and calibration constant (1) Generally, the calibration constant relates to the total charge transferred through this current function as (1a) where is the total charge transferred. The parameters for the exponential waveform will be obtained through the method of moments in this work. A. Method of Moments For an RC tree with an impulse excitation, the voltage at any node can be represented in the form of moments [16]. Let be the Laplace Transform of the impulse response matrix for different nodes in an RC tree. The voltage matrix can be represented as (2) where (3) is the th-order nodal moment matrix for Here coefcient the RC tree. Various methods such as the path-tracing algorithm [15] and the recursive DC analysis have been proposed for calculating the nodal moments. Simple matrix manipulations [16], [17] can also be used to obtain the nodal moment matrix. For any generalized RC circuit system, the state-space equations for a single impulse function excitation can be represented as (4) The solution of (4) on comparing with (3) gives the nodal voltage moments matrix as below (5) where is the th-order moment matrix for the RC tree. The nodal voltage moments obtained through (5) are then converted into current moments for each resistor in the RC network using the concepts of current moments [10]. The current through any arbitrary resistor between nodes and in the RC net can be easily expressed using the following formation: (6) and are impulse response transfer functions where as expressed in (3). The transfer functions for nodes and can be obtained from (3), and, on substituting in (6), we get

saturated ramp and exponential waveforms. We cover the discussion on the driver output waveform in the next section. In Laplace domain, is represented as (8) where a and b are exponential and ramp weights in the waveform, and being a timing parameter. Using the denition of transfer function in (3), it can be noted that current moment in (6) can be expressed as a polynomial in Laplace Domain (9) On comparing (7) and (9), we get the rst three current moments through the resistive element in terms of nodal voltage moments and driver output waveform characteristics (10)

(10) The current moments thus obtained are used to model the current waveform. The parameters for the double exponential waveform model expressed in (1) can be obtained by using the basic denitions of Laplace Transform

(11) Using (10) and (11) and comparing with current waveform in (1), we get

(12) The above are the nal parameters used to construct the current waveform which gives a closed form expression for AVG and RMS currents. It can be noted that above methodology is very general and can be easily extended to other current waveform shapes. 1) Discussion on Driver Output Waveform: , the driver output waveform employed in (8) is assumed to be a combination of saturated ramp and exponential waveform, [13]. It is represented in time domain as (13) Here and are the weights of exponential and saturated ramp waveform, respectively. Fig. 2 shows the modeling of the wave-

(7) It can be shown that for an RC tree with no resistive path to ground, the zero order circuit moment is equal to one. in (7) is the driver output waveform which is a combination of

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Fig. 2. Driver point waveform modelingExponential and ramp.

form for variable values of and . The rise time used in (13) is modeled using rise-time obtained from the production timing data through PrimeTime or other such tool, which could be typically 10% to 90%, and correspondingly for the fall-time. The effects of asymmetrical rise and fall on the current waveform are covered in subsequent sections. Taking Laplace Transform of (13), we get (14)

Fig. 3. Detailed modeling ow as proposed in this work.

(14) The rise time variability as shown in Fig. 2 is used to model the sluggish response arising due to the excessive loading of the net. 2) Fixing of Current Waveform: The waveform parameters as derived in (12) are used to model the double exponential waveform. For each resistor in the net, the closed form for AVG and RMS currents can be derived from the double exponential expression of (1), as follows: The static current ow in a single switching cycle is estimated by current ow in one time period, i.e., integrating (15) and (16) from to . The problems arising by assuming that the current in a resistive branch returns to zero after the switching event is over [10], [12], i.e., integrating from to have been further elaborated in Section III-C. The overall ow for modeling the current waveform is summarized in Fig. 3. B. Asymmetric Rise and Fall Inconsistencies in the estimation of RMS current have been observed due to the variations in rise and fall of the driver output voltage waveform. Fig. 4 shows the change in RMS current with
Fig. 4. RMS current variation showing asymmetrical effects.

the ratio of rise and fall times. One of the ways to resolve the problem is by nding the equivalent slew of the waveform such that it matches the RMS current of the original, combined waveform. Assuming the waveform shape can be approximated by a triangle, it is easy to see that the equivalent slew relates to the rise and fall slews ( , , respectively) in following manner, also reported earlier by [5]: (17) However, we nd that above formulation does not work well, since it has been derived with the triangular waveform approximation, which breaks for many nets. Accordingly, we propose a new slew derivation that is dependent on the net characteristics in the form of moments and also on rise and fall times of the driver output waveform. The moments used are obtained

(15)

(16)

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Fig. 5. Current waveform for a highly resistive net.

for the driving point node (please see derivation in Appendix I). The equivalent slew can thus be expressed as
Fig. 6. Charge transfer variation with frequency; resistivity of nets.

(18) It is clear from the above equation that the equivalent slew is dependent on the nets RC characteristic. If the net is highly resistive, the voltage response will be sluggish and vice versa. This fact is highlighted in the above equation due to its dependency on moments. Another approach that we have adopted is using two different rise and fall times for estimating the RMS current, and thus repeating the moment computation method twice. While the method incurs the penalty of double calculation, we do observe very accurate results by using the above approach, when compared to SPICE. The production results obtained from the above three approaches have been further discussed in Section IV-B. C. Incorporating Resistive Effects The AVG and RMS currents predicted by other models [10][12] at high frequencies for highly resistive nets incurs inaccuracies when compared with the actual SPICE simulations. Fig. 5 highlights the problem. It is evident for a highly resistive net that the current does not return to zero as the switching event is over, contradictory to the current predictions in [10] and [12]. Next, we have also compared the charge transferred and the RMS current plots at different frequencies for heavily loaded nets. Fig. 6 shows the amount of charge transferred to the net with change in cells frequency and the change in nets electrical properties (resistivity of the net). For non-resistive nets (very low resistive shielding) the charge transferred remains constant even at high frequencies but for heavily loaded nets, total charge transferred becomes nearly half due to excessive resistive shielding. This change in charge transfer directly affects the computation of AVG current which is nothing but the total charge transferred in a single switching cycle. Fig. 7 gives a prediction of RMS current.

Fig. 7. RMS current variation with frequency and resistivity of nets.

According to (21), the RMS current does have a strong dependence on frequency, slew and total charge transferred which is evident from the graph. For non-resistive nets, RMS current increases with frequency. For heavily loaded nets, two effects operate together. First the charge transferred has reduced and at the same time the slew has increased due to the sluggish response of the RC net. Both the above effects act together to reduce the RMS current at high frequencies. Hence we note that not only RMS but AVG current is also a strong function of the nets electrical properties. Based on the nets properties, the double exponential waveform model gives a very accurate prediction of current at high frequencies for highly resistive nets. D. Incorporating IR Drop Effects As noted in previous sections, the two fundamental effects against which, interconnects needs to be safeguarded are, electromigration (EM), and Joule Heating (JH). As also noted previously, while EM is a long term problem, aggravated with temperature rise due to JH, Joule heating in itself is an instantaneous problem. Thus, for example, while a design with only two year

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Fig. 9. Impact of IR Drop on the waveforms at the output.

Fig. 8. Duty Cycle distribution for a 45-nm ASIC design, highlighting dominance of RMS effects.

lifetime requirement might have very relaxed EM rules, the constraints on RMS currents for the design will not be very different from a design with either two months lifetime or even 10 years. Additionally, the fundamental EM, or average current rules, can also be inuenced by a designs choice of junction (or ambient) temperature and system complexity [18], no such knob exists for RMS currents. In light of the previous argument, it is also important to note the recent design trendsin terms of dominance of either EM mechanism or Joule Heating. As an example, it is easy to observe that interconnects within the SoC power network will have more DC like nature with intermittent surge in currents due to switching activities. On the other hand, interconnects in clock network will have extreme AC nature and the average current of such interconnects will be, on the contrary, very small. Above characteristics of the interconnect can be nicely parameterized through an effective duty cycle , which is dened as squared ratio of average and RMS current densities. Thus, a signal which is pure DC will have an value close to and a signal with very high RMS component is expected to have a very small value of . Accordingly, an -map of the entire design can quickly help characterize the nature of the design. A design having a majority of signals with high value is expected to be EM-limited, whereas the design with dominating low values will be RMS limited. We have collected such data from several production designs on 65 and 40 nm nodes, summarized for one of the designs in Fig. 8. As can be seen, the design is indeed RMS limited. In light of above discussion, it is extremely critical to compute the RMS current accurately, since that being the only knob to contain RMS currents. Consequently, we noted that uctuations in power supply voltage while switching [19] result in an imprecise prediction of RMS current. The change in current waveform shape due to changes in power supply (Vdd) in Fig. 9 restates the above fact. It is not unusual to see IR drops up to 0.3 V in todays designs. Clearly, it will lead to an error of 30% in RMS current estimation as shown in Fig. 10.

Fig. 10. Change in RMS current due to power supply voltage uctuations.

On comparing the V(Vdd) and V(out) voltage waveforms in Fig. 9, it becomes clear that changes in voltage supply is marked by changes in the input slew. Thus a relation between the input slew and the change in power supply can be fruitful in developing a model which will augment our existing exponential model in accurately predicting the currents. It can be deduced that slew changes linearly with voltage drop, in following manner. RMS currents and the peak drive current relate to the operating headroom in a nonlinear fashion as

(19) Also by assuming the driver output current to be a triangular waveform, it can be stated that [11]

(20) Here, alpha and beta are constants in the range of 12. From (19) and (20), it is apparent that change in power supply voltage has a linear dependence on change in slew of the driving point voltage waveform. Accurate results in the prediction of RMS current have been obtained by modeling the output slew.

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Fig. 11. Current waveforms for different input waveforms. Fig. 13. Error in RMS estimation w.r.t. SPICE simulations.

Fig. 12. AVG current comparison w.r.t. actual SPICE simulations. Fig. 14. Variation of RMS current with asymmetric waveform.

IV. RESULTS AND DISCUSSIONS A. AVG and RMS Current Comparisons The above implementation was validated on approximately 150 cells and EM/speed critical nets with a high resistive shielding, i.e., cells having a clumped to c-effective ratio (greater than 3). The cells and nets were tested with different driver output waveforms and the results for both AVG and RMS current were compared. Fig. 11 shows the driver point current comparison of the modeled current waveforms with different mix of exponential and ramp (variable values of and ) driver output waveforms against actual SPICE simulations. It is clear that our model matches with the SPICE simulations with a good degree of accuracy. Moreover it can be concluded from the above gure that our model can be readily used with different kinds of driver output waveforms, be it fully ramp, exponential or a mixture of both. Also on further experimentation with several nets, it was seen that the waveform with equal fractions of saturated ramp and exponential waveforms gives a very good estimation of AVG and RMS currents. This fact is again validated with the aid of Figs. 12 and 13. Fig. 12 compares the AVG current with the actual SPICE simulations. The error plotted is the AVG current obtained from waveform with equal fractions of saturated ramp and exponential waveforms versus actual simulations. It can be seen that the error is within 5% of the SPICE simulations. At the same time, we see that the results from different waveforms overlap. It again restates the fact that AVG current is independent of waveform shape, to a large extent. Fig. 13 compares the error in RMS current measurement. The sluggish response of an exponential waveform gives an optimistic prediction of RMS current when compared to the prediction from saturated ramp waveform. This fact can be easily validated from the graph which shows more positive error for (saturated ramp) waveform. The error for graph is within 5% of the actual SPICE prediction thereby making it an obvious choice for current estimation. B. Implementing Asymmetric Waveform Effects The comparison for the methods proposed in Section III-B with the actual SPICE simulations is shown in Fig. 14. It is clear that by using asymmetric modied waveforms for RMS computation, i.e., computing RMS current using different rise and fall times, very accurate computations of RMS current can be made. Although this method involves double computations, it overweighs the ineffectiveness of the other methods thus making it a better choice. Still there are some tools which can only work with a single slew metric. From Fig. 14, it can be seen that the equivalent slew proposed in (18) due to its dependency on moments gives a better prediction of RMS current than the one proposed in (17), i.e., the harmonic mean slew. Hence for such tools the proposed equivalent slew can be the preferred choice.

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Fig. 15. Comparison of AVG current with the previous models. Fig. 17. Comparison of RMS current with Vdrop.

current estimation was reduced by more than 30%. This fact is validated in Fig. 17 which shows that the error in RMS current by using the old modied slew rises with increase in voltage drop, while the new modied slew restricts the error within 5%. V. PRODUCTION IMPLEMENTATIONEFFECTIVE SLEW COMPUTATION While noting that many production tools and place-and-route EM avoidance methods still rely on triangular waveform assumptions for EM assessment, we propose a new EM specic slew derivation in this section. Using the model proposed in previous sections, the EM specic slew can be easily calculated for the triangular waveform, which can be used in constructing the waveform. Making use of the the RC network and the timing data, we can statically arrive at the accurate prediction of RMS current. It can, then, be noted that the RMS current due to a triangular waveform depends inversely with squarerooted slew. Using this relationship, we can easily derive the new slew, which when used along with the nets lumped capacitance will predict the same RMS current as obtained through the moment based computations. In other words, using the RMS current formulation for triangular waveform [11] (21) where is the frequency of operation of the signal. Fig. 18 compares the triangular waveform, thus obtained with modied slew, with the actual SPICE simulated current waveform. Next, we used the proposed method on several production signals from a 40 nm design and Fig. 19 shows the error in RMS current computation validated against exact SPICE simulations. As can be seen, the old slew-based RMS current (directly obtained from timing data) could be inaccurate up to 40%, whereas the new slew is much more accurate. The entire production-use model is as depicted in Fig. 20. While the traditional signal EM analysis ows directly consume the timers outputs along with the interconnect database, in this work, we propose to use that rst to compute the current moments, which are thereafter used to correct the original slew. This modied slew can then be fed into existing commercial Signal EM analysis tools.

Fig. 16. Comparison of RMS current with the previous models.

C. Incorporating Resistive Effects As pointed in Section III-C, the problems arising for heavily loaded nets can be taken care of by using the static values obtained in (15) and (16). Fig. 15 shows the error in AVG current computations with respect to frequency for resistive nets validated against actual SPICE simulations. It compares the values obtained from using the model for calculating current ow in a cycle referred in [10] with our model . It is evident from the graph that our model gives an error up to 5% for heavily loaded nets as compared to the 30% error in computations by using the referred model [10]. Fig. 16 compares the estimation of RMS currents for heavily loaded nets at high frequencies. It can be seen that for heavily loaded nets the model gives a pessimistic prediction when validated against actual SPICE simulations whereas our model matches with the SPICE simulations even at high frequencies. From the above discussion, it can be acknowledged that the discrepancies arising in the computation of AVG and RMS currents as explained via 3-D plots can, up to a great extent, be taken care of by using the proposed model which takes into considerations the properties of the net and by simply calculating the current ow in one complete cycle. D. IR Drop Implementation As discussed in Section III-D, a linear relation was obtained for change in input slew with respect to power supply uctuations. Linear dependency model was implemented for further computations. By adopting the above methodology, the error in

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Fig. 18. Triangular current source using new slew.

Fig. 21. Library level characterization of standard cell from EM reliability perspective.

Fig. 19. Error in RMS prediction with modied slew.

Fig. 20. Production moment-based ow for computing modied slew and associated RMS current.

VI. STANDARD-CELL EM ANALYSIS AND MODELLING While in previous sections, we have discussed in great details on the reliability of SoC level signal interconnects, robust design of standard cells itself is at the crux of an SoCs design integrity. The standard cells needs to be reliably operating at the guaranteed conditions, including the timing and leakage constraints. Thus, during the process of library design, utmost care needs to be taken to set the correct EM targets for different cells. These targets could be in term of the maximum operating loads, frequencies, voltages, input-output slews or temperature, and lifetimes. Additionally, while the cells are designed robust to meet a particular target, it is also important to ensure that the designer gets benet when the cell does not operate at its full specication, or, on the contrary, gets an error when the cells are operating beyond the specication.

To enable exactly thisperforming standard-cell-internal-EM checks at chip level, based on chip level operating conditions of cells, method of modeling the safe frequency of the cell at different operating points is used. This data, as represented graphically in Fig. 21, actually characterizes the EM properties of the cell and can be readily used at chip level to gure out the safe operating frequency at any operating condition (namely, load). This information can be used to identify EM-critical cell instances and take corresponding design xes. Good timing constraints are very effective in limiting the EM-critical cells, which are usually instances operating at high loads, frequencies or bad slews (typically less than few hundreds). However, with advancing technology and complicated circuit effects, the safe frequency versus operating condition data in itself is not accurate to predict the EM safety of standard cells. To accomplish this, several models for approximating the driving point admittance such as lumped capacitance and c-effective have been proposed in literature. Here we show that none of the above two models have been accurate enough to predict the actual behavior of interconnect, i.e., they fail when approximated for highly resistive nets. Shown in Figs. 22 and 23 are the current waveforms and Charge Transferred waveforms for a highly resistive net. The current waveforms of actual SPICE simulations show that the current does not return to zero as the switching event is over whereas the lumped capacitance or c-effective approximation blurs the above fact. Also, clear from the charge transferred graph that the lumped capacitance model gives a pessimistic prediction of AVG current and c-effective an optimistic prediction for a highly resistive net, thereby making both of them inaccurate. Further SPICE simulations were performed on approximately 150 nets having very high resistive shielding. Fig. 24 shows the RMS current prediction for resistive nets at high frequency. It can be seen that neither lumped capacitance nor c-effective models give an accurate estimation of RMS current. This is credited to the fact that the current waveform shapes for the actual SPICE simulation is different from that of the two

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Fig. 22. Comparison of current waveforms for different models.

Fig. 25. AVG current comparison (cell level).

initial ltering of non-EM-critical cells is done properly, as discussed before, through library characterized data. Moreover, the interconnect network for the signal is already present in the extracted databases, so no new extraction needs to be done. Additionally, such a procedure also allows for accurate accounting of the exact vias dropped on cells output ports at chip-level. It can also be noted that commercial fast solvers like Ultrasim can be employed for solving the system efciently and quickly, once dened correctly as above. VII. CONCLUSION
Fig. 23. Comparison of charge transferred for different models.

Fig. 24. RMS current comparison (cell level).

models thereby asserting that RMS current is a strong function of waveform shape. Next the AVG current for both the referred models was compared with the currents from actual SPICE simulations. It can be seen from Fig. 25 that lumped capacitance model gives a good estimate of AVG current but again the c-effective model fails completely. From the above discussion, it can be said that c-effective is inaccurate in estimating RMS and AVG current. On the other hand, though the lumped capacitance model gives a good estimate of AVG current it fails in predicting RMS currents accurately. Correspondingly, one of the suggested solutions is to go for full SPICE simulation of the entire cell with the interconnect. This method is very accurate, and, can also be efcient if the

The implementation of an improved and efcient method to compute electromigration reliability of interconnects was presented in this work. Unlike prior art, we use matrix-based circuit-moment computations and a double exponential waveform model. We presented comparative results with respect to traditional techniques, which highlighted upto 40% improvement in accuracy. The model is made easily congurable for various choice of driver waveform type, and also accounts for the asymmetric nature of the waveform. We provide closed-form expressions for AVG and root-mean-square currents to enable fast and accurate EM currents estimation. Unlike conventional wisdom, we note that not just the RMS current, but even the total charge transfer, and therefore the AVG current can also be dependent on the current waveform type and nets electrical properties. We proposed formulations to account for this behavior of AVG current. Additionally, as a correction to prevalent current-estimation techniques, and, an application of proposed method, we provide formulations for deriving the effective EM slew, which can be used with conventional static approaches to accurately compute the currents, which are otherwise off by as much as 40%. Impact of dynamic voltage drop was studied on interconnect reliability for the rst time, and we noted that while AVG current remains invariant of the voltage drop, RMS current can be reduced by as much as 30%, based on the drop and this information needs to be modeled in any EM computation ow. Lastly, we also lay out recommendation on usage of the loadeither effective or lumped load, for simulating an IP. Our results indicate both of them to be inefcient in capturing nets properties. Finally, we shared model validation results with respect to actual SPICE simulations from a production 40 nm design. The method enabled still higher performance of a

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design, which was otherwise optimized for an originally lower frequency target using conventional approaches. APPENDIX The combined slew in (18) can be derived by using the relations below. For the current waveform (A1) RMS current can be calculated from the relation

(A2) Using the moments in (10), can be expressed as (A3) Using the expressions from (10) and equating the RMS currents obtained from two different rise and fall times with that obtained from a combined slew , we get

[9] N. S. Nagaraj, F. Cano, H. Haznedar, and D. Young, A practical approach to static signal electromigration analysis, in Proc. DAC, 1998, pp. 572577. [10] K. Agarwal and F. Liu, Efcient computation of current ow in signal wires for reliability analysis, in Proc. ICCAD, 2007, pp. 741746. [11] D. Blaauw, O. Chanhee, V. Zolotov, and A. Dasgupta, Static electromigration analysis for on-ship signal interconnects, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 1, pp. 3948, Jan. 2003. [12] M. Shao, D.F. Wong, Y. Gao, H. Cao, and L.-P. Yuan, A fast and accurate method for interconnect current calculation, in Proc. ASPDAC, 2003, pp. 3742. [13] M. Shao, Y. Gao, L.-P. Yuan, H.-M. Chen, and M. D. F. Wong, Current calculation on VLSI signal interconnects, in Proc. ISQED, 2005, pp. 580585. [14] Magma Design Automation, Magma user guide, 2010. [Online]. Available: http://www.magma-da.com [15] C. L. Ratzlaff, N. Gopal, and L. T. Pillage, RICE: Rapid interconnect circuit evaluator, in Proc. DAC, 1991, pp. 555560. [16] L. T. Pillage and R.A Rohrer, Asymptotic waveform evaluation for timing analysis, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9, no. 4, pp. 352366, Apr. 1990. [17] L. Pillage, Electronic Circuit & System Simulation Methods. New York: McGraw-Hill, 1998. [18] P. Jain, Y. J. Park, S. Krishnan, and C. Prasad, Budgeting EM related reliability in interconnects, US20090187869. [19] H. Hanzi, R. Haussler, M. Olbrich, and E. Barke, Efcient modeling techniques for dynamic voltage drop analysis, in Proc. DAC, 2007, pp. 706711. [20] P. Dodd and L. Massengill, Basic mechanism and modeling of SEU in digital electronics, IEEE Trans. Nuclear Sci., vol. 50, no. 3, pp. 583602, Jun. 2003. [21] Apache Design Automation, Apache-Redhawk tool manual, 2010. [Online]. Available: http://www.apache-da.com [22] Wu and Y.-W. Chang, Efcient power/ground network analysis for power integrity-driven design methodology, in Proc. DAC, 2004, pp. 177180. [23] Z. Hao and G. Shi, A fast symbolic computation approach to statistical analysis of mesh with multiple sources, in Proc. ASPDAC, 2010, pp. 383388. Palkesh Jain (M11) received the Bachelors and Masters degrees in electrical engineering, under the Dual Degree Program, from the Indian Institute of Technology (IIT), Bombay, India, in 2004. His Masters research was on soft errors and radiation reliability. He joined the Reliability CAD Group, Texas Instruments, Bangalore, India, in July 2004. Since then, he has contributed signicantly to the CAD and methodology development for 65, 45, and 28 nm reliability verication, currently leading the CAD efforts for reliability and power integrity. His current research interests include power-performance-reliability tradeoffs and SoC integrity. He holds over 10 U.S. patents, granted or pending, and over 10 publications in refereed international conferences and journals.

(A4) Here and are as described in (8). REFERENCES

[1] B. K. Liew and C. Hu, Circuit reliability simulator for interconnect, via, and contact electromigration, IEEE Trans. Electron. Devices, vol. 39, no. 11, pp. 24722479, Nov. 1992. [2] J. R. Black, Electromigration failure modes in aluminium metallization for semiconductor devices, Proc. IEEE, vol. 57, no. 9, pp. 15871594, Sep. 1969. [3] K. Banerjee and A. Mehrotra, Global interconnect warming, IEEE Circuits Devices Mag., vol. 17, no. 5, pp. 1632, Sep. 2001. [4] H. Bill, Self-consistent solutions for allowed interconnect current density, IEEE Trans. Electron. Devices, vol. 44, no. 2, pp. 304309, Feb. 1997. [5] Y. J. Park and P. Jain, Via-node-vector EM checking methodologyNew paradigm, in Proc. IEEE IRPS, 2010, pp. 698704. [6] G. Jason and D. Balhiser, Process and system for identifying wires at electromigration risk, USPTO 6857113B2, Feb. 2005. [7] P. Jain and V. Zhu, Judicious choice of waveform parameters and accurate estimation of critical charge for logic SER, in Proc. DSN, 2007. [8] R. H. Tu, , E. Rosenbaum, W. Y. Chan, C. C. Li, E. Minami, K. Quader, P. K. Ko, and C. Hu, BERT, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 10, pp. 15241534, Oct. 1993.

Ankit Jain received the Bachelors degree in electronics from the Birla Institute of Technology and Science, Pilani, India, in 2010. He will be pursuing the Masters degree in electrical and computer engineering from University of Maryland, College Park, in Fall 2011. He was a project trainee with Texas Instruments, India, where he worked on the CAD methodology for reliability. He is currently an Engineer with BHEL-ED, Bangalore, India.