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2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,

Kharagpur, INDIA December 8 -10, 2008.


17
978-1-4244-2806-9/08/$25.00 2008 IEEE



Abstract This paper describes on how to formulate a self-
balancing space vector modulator for the three-level neutral
point clamp topology typically used for high power induction
motor drives. Dependence of the DC link capacitor voltage
deviation on DC-link current and inverter switching states is
established for proposed three-level inverter. Pulse pattern
rearrangements for space vector PWM (SVPWM) using degree
of freedom available in choice of redundant space vectors,
sequencing of vectors, and splitting of duty cycles of vector are
best exploited. Self neutral-point voltage deviation control in feed
forward is proposed in this paper. The effectiveness of proposed
scheme is verified by experimental results. The modulator was
successfully implemented using DSP-TMS320F2811 with a 45-
kW (60 HP) motor drive. Lab test results are given for
effectiveness of the modulator.
Index TermsNeutral point clamped (NPC) inverter, self
balancing space vector modulation (SVM), three-level
inverter, VSI.
I. INTRODUCTION
HE Three-Level neutral point clamped topology has
attracted attention in high power medium voltage drive
applications. Fig. 1 shows main circuit of NPC voltage source
inverter. Other interesting applications of this technology
include static VAR compensation systems, HVDC
transmission systems, active filtering applications, as well as
applications in power conditioning systems for
superconductive magnetic energy storage (SMES).
Three-level topology is advantageous in constructing
medium voltage high power drives by using highest voltage
devices because the voltage across the switch is half that of
the conventional inverter. They can reduce harmonics in the
output voltage and current due to the multilevel output voltage

This work was supported by Amtech Electronics (I) Ltd., Gandhinagar,
India.
IEEE Kharagpur Section & IEEE Sri Lanka Section


[1], [2]. The effect of capacitor voltage unbalance during
steady state condition is analyzed in this paper. In the worst
case of unbalance one capacitor is fully charged to full DC-
link voltage that results in double stress on the capacitor and
the switching devices, reducing output waveforms to two level
from normal three-level. The effect of the zero sequence
voltage on the neutral point variation and the dependence of
DC-link voltage unbalance on the system parameters like load
currents, load power factor, value of capacitance of capacitor,
and modulation index have been extensively analyzed for
three-level NPC inverter [3]- [5]. The neutral point balancing
schemes, for the three-level neutral point clamped inverter, are
based on the effective use of the redundant switching states of
the inverter voltage vectors. The redundant switching states
are used alternately such that the neutral point voltage
unbalance caused by the first switching state combination is
compensated by another state; thus, bringing the total
unbalance in one switching cycle to zero [6]. Detailed study of
NPC inverter, space vectors, dwell timings, and pulse pattern
arrangement with division of middle regions for neutral point
balance and even harmonic elimination scheme are addressed
[7]. Neutral point voltage control is achieved by utilizing the
phase current polarity and distribution of the redundant
voltage vectors. A control strategy is proposed to maintain
average current drawn from neutral-point to the minimum [8],
[9]. Hysteresis control for DC-link variation control and
common mode voltage elimination in an open end winding
induction motor fed from two three-level inverters from either
side is investigated [10]. ANN based neutral-point self-voltage
balancing SVPWM is discussed for NPC inverter [11].
Mathematical modeling and open loop and closed loop
neutral-point control is proposed for three-level voltage source
inverter [12]. The space vector PWM signal generation for
multi-level inverters using only the sampled amplitudes of
reference phase voltages is discussed in detail [13]. The
experimental studies are carried out on a 45-kW induction
motor drive and the experimental results are presented.
Pinkal J. Patel, Rakesh A. Patel,
Electrical Department, R & D Department,
Sankalchand Patel College of Engineering, Hirel Electronics (I) Ltd.,
Visnagar, India. Gandhinagar, India.
pinkal_ldce@yahoo.com rakeshpatel555@yahoo.com

Vinod Patel P. N. Tekwani
R & D Department, Electrical Department,
Amtech Electronics (I) Ltd., Nirma Institute of Technology,
Gandhinagar, India. Ahmedabad, India.
vinodp@amtechelectonics.com pntek@rediffmail.com
Implementation of Self Balancing Space Vector
Switching Modulator for Three-Level Inverter
T
2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,
Kharagpur, INDIA December 8 -10, 2008.
17
978-1-4244-2806-9/08/$25.00 2008 IEEE


II. THREE-LEVEL INVERTER SCHEME WITH SELF-BALANCING
SVM FOR AN INDUCTION MOTOR DRIVE
Fig. 1 shows the simplified circuit diagram of a popular
three-level neutral point clamped (NPC) inverter. The inverter
leg 'a' is composed of four IGBT switches S
1
to S
4
with four
antiparallel diodes D
1
to D
4
. On the DC side of the inverter,
the DC bus capacitor is split into two sources, providing a
neutral point 'n'. When switches S
2
and S
3
are turned on, the
inverter output terminal a is connected to the neutral point
through one of the clamping diodes D
n1
and D
n2
. Ideally, the
voltage across each of the DC capacitors is V
dc
/2 which is half
of the total DC-link voltage V
dc
,. With a finite value for C
1
and C
2
, the capacitors can be charged or discharged by neutral
current i
n
, causing neutral-point voltage deviation. The
important problem of voltage unbalance between upper and
lower capacitors in three-level NPC inverter is discussed
further.
As indicated earlier, the neutral-point voltage V
n
= V
c1

varies with the operating condition of the NPC inverter. If the
neutral point voltage deviates too far, an uneven voltage
distribution takes place, which may lead to failure of the
switching devices and cause an increase in the harmonic of the
inverter output voltage [1].
The switches S
1
and S
3
operate in a complementary manner
similar to switches S
2
and S
4
.The operating status of the
switches in the NPC inverter can be represented by the
switching states shown in Table 1. Switching state + denotes
that the upper two switches in leg 'a' are on and the inverter
pole voltage Va, which is ideally +Vdc/2, whereas '-' indicates
that the lower two switches conduct, leading to Va = -V
dc
/2.
Switching state '0' signifies that the inner two switches S
2
and
S
3
are on and Va is clamped to zero through the clamping
diodes. Depending on the direction of the load current ia, one
of the two claming diodes is turned on. For instance, a
positive load current (ia > 0) forces D
n1
to turn on, and the
terminal 'a' is connected to the neutral point 'n' through the
conduction of D
n1
and S
2
.
The space-vector PWM method is an advanced,
computation-intensive PWM method and is possibly the best
among all the PWM techniques for variable-frequency drive
applications still known.

In case of a two-level inverter there are total of 8-vectors
(6-non zero vectors and 2-zero vectors). The number of
vectors for n-level inverter is given by,
No. of space (stationary) vector = n
3
(1)

Hence in case of a three-level inverter there are 27 vectors
and among them, there are 3-zero vectors and 24-non zero
vectors. Similarly, five-level inverter shall have 125 vectors.
Each switching state, or combination of phase-leg switches,
produces a defined set of three-phase voltages, which can be
represented in a hexagon form as shown in fig.2.

III. ANALYSIS OF DC LINK CAPACITOR VOLTAGE
UNBALANCE FOR THREE-LEVEL INVERTER SCHEME
In the NPC three-level inverter, the current drawn through
the mid-point of dc link will result in the unbalance of the
capacitor voltage [3]. This section presents the analysis to
determine the unbalance in the dc link capacitor voltages for
the three level inverter schemes for induction motor drive.
A. System Model
The system model of the proposed inverter scheme is
shown in Fig. 3. The voltage across the bottom and top dc link
capacitors is referred as Vc1 and Vc2. Under the balanced
condition, V
c1
= V
c2
= V
dc
/2. Each leg of individual three-level
+
-
Vdc Induction
Motor
T
h
r
e
e
P
h
a
s
e
A
C
M
a
i
n
s
S1
S2
S3
S4
D1
D2
D3
D4
n
Dn1
Dn2
a
b
c
Uncontrolled
Rectifier
C1
C2

Fig. 1. Three level neutral point clamped inverter fed induction motor drive
TABLE I
SWITCH STATUS AND DEFINITION OF STATE
Switching
States

Device Switching Status
(Phase a)

Pole
Voltage
V
a


S
1
S
2
S
3
S
4

+ ON ON OFF OFF + V
dc
/2
O OFF ON ON OFF 0
- OFF OFF ON ON -V
dc
/2
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
+oo
o-- ooo
+++
--- +--
++o
oo-
+o-
++-
o+o
-o-
o++
-oo
oo+
--o
+o+
o-o
o+-
-+-
-+o
-++
-o+
--+ o-+ +-+
+-o
V*
1
2
3
4
0n

Fig. 2. Space vector diagram for three-level inverter
2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,
Kharagpur, INDIA December 8 -10, 2008.
17
978-1-4244-2806-9/08/$25.00 2008 IEEE


inverter can be modeled as a switch, with the three output
levels 1, 2, 3, (this is used instead of - , 0, + for the ease of
mathematical analysis in the following section) when the pole
is connected to negative, mid-point and positive bus of the dc
link, respectively, as shown in Fig. 3. The load currents are
deoted as ia, ib and ic while the total current drawn by the
inverter from the bottom, middle, and top rails of the dc link
are denoted as i1, i2 and i3 respectively.
B. Determination of Capacitor Voltage Unbalance
In general the inverter pole voltage with respect to the
negative DC bus can be written in terms of capacitor voltages
and the switching functions as,
v
a1
(S
a
) = (S
a
1 )v
c1
+ (S
a
2 )(v
c1
+ v
c2
)
v
b1
(S
b
) = (S
b
1 )v
c1
+ (S
b
2 )(v
c1
+ v
c2
) (2)
v
c1
(S
c
) = (S
c
1 )v
c1
+ (S
c
2 )(v
c1
+ v
c2
)
In (2) (.) is the Dirac delta function, v
c1
and v
c2
are the
voltage across lower and upper capacitors. The currents drawn
from the DC-link nodes can be represented in terms of the
motor currents as shown in (3)
(
(
(

(
(
(




=
(
(
(

c
b
a
c b a
c b a
c b a
i
i
i
S S S
S S S
S S S
i
i
i
) 3 ( ) 3 ( ) 3 (
) 2 ( ) 2 ( ) 2 (
) 1 ( ) 1 ( ) 1 (
3
2
1



(3)
For the three wire load,
i
a
+ i
b
+ i
c
= 0
i
1
+ i
2
+ i
3
= 0 (4)
Substituting i
c
= -i
a
-i
b
and removing the dependent variable i
3
,
(2) gets reduced to
| |
| |
(



=
(

b
a
c a
c a
i
i
S S
S S
i
i
) 2 ( ) 2 (
) 1 ( ) 1 (
2
1


(5)
The current flowing through capacitor is given by
i
c2
= i
s
i
3
= i
s
( i
2
i
1
) = i
s
+ i
2
+ i
1

i
c1
= i
s
+ i
1
(6)
(
(
(

=
(

1
2
1
2
1 0 1
1 1 1
i
i
i
i
i
s
c
c
(7)
Thus, the currents flowing through capacitors is directly
related to the voltage across the capacitors and the relationship
is given by


)

(
(
(

=
)
`

=
(

dt
i
i
i
C
dt
i
i
C v
v
s
c
c
c
c
1
2
1
2
1
2
1 0 1
1 1 1
1
1 0
0 1
1
(8)

Let v
c
be the change in the capacitor voltage, Substituting
value from (5) into (7), results in
v
c
= v
c1
- v
c2
(9)

= dt i
C
vc
2
1
(10)

Thus the load current drawn from the middle node of the
DC-link is responsible for the variation in the capacitor
voltages. Whenever switching functions S
a
, S
b
, and S
c
, assume
value equal to 2, there exists a tendency of capacitor voltage
unbalancing.
IV. SWITCHING COMBINATIONS AND THEIR
EFFECT ON DC LINK CAPACITOR VOLTAGES

Fig. 3. Three-level inverter and load system model
L
O
A
D
Vdc
n
Vn
C1
C2
a
b
c
+
-
(a) Zero voltage vector
+ + +
L
O
A
D
Vdc
n
Vn
C1
C2
a
b
c
+
-
(b) P-type small vector
+ O O
in
L
O
A
D
Vdc
n
Vn
C1
C2
a
b
c
+
-
(c) N-type small vector
O - -
in
L
O
A
D
n
Vn
C1
C2
a
b
c
+
-
(d) Medium voltage vector
+ O -
Vdc
L
O
A
D
n
Vn
C1
C2
a
b
c
+
-
(e) Large voltage vector
+ - -
Vdc

Fig. 4. Effect of switching states on Neutral point voltage deviation
2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,
Kharagpur, INDIA December 8 -10, 2008.
17
978-1-4244-2806-9/08/$25.00 2008 IEEE


The effect of switching states on neutral voltage deviation
is illustrated in fig.4 When the inverter is operated with
switching state [+++] of zero vector, the upper two switches in
each of the three inverter legs are turned on, connecting the
inverter terminals a, b, and c to the positive DC bus as shown
in fig.4(a). Since the neutral point 'n' is left unconnected, this
switching state does not affect V
n
. Similarly, the other zero
switching states [000] and [---] do not cause V
n
to shift either.
Fig 4(b) shows the inverter operation with P-type switching
state [+OO] of small vector. Since the three phase load is
connected between the positive DC bus and neutral point 'n',
the neutral current in1 flows in 'n', causing V
n
to increase. On
the contrary, the N-type switching state [O--] of small vector
makes V
n
to decrease as shown in fig. 4(c). For medium
vector with switching state [+O-] in fig. 4(d), load terminals a,
b, and c are connected to the positive bus, the neutral point,
and the negative bus, respectively. Depending on the inverter
operating conditions, the neutral-point voltage V
n
may rise or
drop. Considering a large vector with switching state [+--] as
shown in fig. 4(e), the load terminals are connected between
the positive and negative DC buses. The neutral point 'n' is left
unconnected and thus the neutral voltage is not affected.
It is summarized that zero and large vectors do not affect
the neutral point voltage. Medium vectors affect V
n
, but the
direction of voltage deviation is undefined so, redundant small
vectors having dominant influence on V
n
are used for neutral
point voltage control. Above discussion is made under the
assumption that the inverter is in motoring mode.
In addition to the influence of switching states, the neutral-
point voltage may also be affected by a number of other
factors like unbalanced DC capacitors due to manufacturing
tolerances, inconsistency in switching device characteristics,
unbalanced three-phase operation, motoring/regenerative
mode of operation etc. As compared to motoring mode, an
opposite capacitor voltage charging-discharging action takes
place in the regenerative mode due to the reversal of current.

V. DC-LINK CAPACITOR VOLTAGE BALANCING
SCHEME
Various space vector modulation (SVM) schemes have
been proposed for the three-level NPC inverter using either
open loop scheme or closed loop scheme [7]. This paper

Fig. 6. Photograph of hardware prototype
(a)
(b)
(c)
(d)
Ts Ts
o
-
o o + + + + + +
+ + + +
- - - -
+ +
- - - - - -
o o o
o o
o o o o
o o o
o o o
-
a
b
c
o o o o + + + + + +
o o o + +
o o o
- -
- - - - - -
a
b
c
o o o o
o o + + + + + +
-
- - - o o o o
- - - - - - o o
o o + + + + + +
a
b
c
a
b
c
o o o o + + + +
- - - - - - o o

Fig. 5. Switching Signals of Sector 1 for (a) Region-1, (b) Region-2,
(c) Region-3, (d) Region-4
TABLE II
EFFECT OF DIFFERENT VECTOR GROUPS ON CAPACITOR
VOLTAGES
Group Capacitor C1 Capacitor C2
ZV No effect No effect
PSV Charging Discharging
NSV Discharging Charging
MV
Less Charging or
Discharging effect
Less Charging or
Discharging effect
LV No effect No effect
2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,
Kharagpur, INDIA December 8 -10, 2008.
17
978-1-4244-2806-9/08/$25.00 2008 IEEE


presents ability of open loop (self-balancing) SVPWM
scheme.
Open loop capacitor voltage (self balancing) SVPWM
scheme is described below. This section proposes modified
SVM scheme for better neutral point stabilization. To reduce
neutral-point voltage deviation, the dwell time of a given
small vector can be equally distributed between the P-type and
N-type switching states over a sampling period. For nearest
three vectors (NTV) selection SVM either one small vector or
two small vectors among the three selected vectors are
available according to the triangular regions in which the
reference vector V
*
lies. When the reference vector V
*
is in
region 2 or 4, only one small vector is in NTV where as in
region 1 or 3 two small vectors are in NTV. In conventional
SVM seven segments pulse pattern is chosen for all regions.
Seven segments SVM divide dwell time of only one small
vector in P-type and N-type out of two small sectors available
in region 1 and 3. So, neutral point deviation is not minimized
in these regions. To reduce neutral-point voltage deviation
according to location of region, optimized pulse pattern
arrangement is proposed here. Switching sequences of
modified SVM pulse pattern arrangement for regions l, 2, 3,
and 4 of sector 1 are shown in fig.5. Here, two redundant
positive and negative small vectors are used for neutral point
voltage control. Switching sequence in opposite sectors (1-4,
2-5 and 3-6) is selected to be of a complimentary nature for
neutral point balancing.

VI. EXPERIMENTAL RESULTS AND DISCUSSION

The photograph of hardware prototype of three-level
inverter is shown in fig.6. The proposed scheme is tested on a
45 kW three-phase induction motor drive with open loop V/f
control for different modulation indices covering the entire
speed range. The dc link voltage of around 600 V is used, thus
the individual dc link capacitor voltages are kept around 300
V. The carrier frequency used for PWM generation is limited
to 2 kHz. The open loop dc link capacitor voltage-balancing
scheme is implemented using DSP-TMS320F2811 control
card. The 3-level SVPWM scheme is used for the PWM
signal generation, based on the sampled amplitudes of
reference phase voltages. The line voltage and line current

Fig. 8. Line Voltage & Line Current Waveforms at 20 Hz, mi = 0.69,
(X- axis: 1 div = 10 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)

Fig. 9. Line Voltage & Line Current Waveforms at 30 Hz, mi = 1.03,
(X- axis: 1 div = 10 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)

Fig. 10. Line Voltage & Line Current Waveforms at 40 Hz, mi =1.38,
(X- axis: 1 div = 5 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)

Fig. 7. Line Voltage & Line Current Waveforms at 10 Hz, mi = 0.34,
(X- axis: 1 div = 20 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)
2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,
Kharagpur, INDIA December 8 -10, 2008.
17
978-1-4244-2806-9/08/$25.00 2008 IEEE


waveforms for inverter operation in inner layer (two-level) are
presented in Figs. 7 and 8. The line voltage and line current
waveforms for inverter operation in outer layer (three-level)
operation are presented in Figs. 9,10 and 11. The switching
combinations from Positive Small Vector or Negative Small
Vector groups to bring back the capacitor voltages to their
balanced condition as shown in Fig.12. This proves the
operation of the dc link capacitor voltage-balancing scheme.
The Results includes Output Line Voltage, Output Line
Current, DC Link voltages for no load condition of Induction
motor.
The difference between capacitors voltage is observed less
than 5 Volt as shown in fig.12. This proves the ability of open
loop (self balancing) SVPWM scheme.
VII. CONCLUSION
In this paper a self-balancing space vector pulse width
modulator is proposed to generate switching patterns for a
three-level neutral point clamp inverter from an input
command voltage vector. The geometry of the voltage
complex plane is utilized to define sectors, triangles and
regions such that minimum on time violation belts can be
avoided naturally. The switching patterns available from the
three level inverter is arranged such that no direct switching
between positive and negative half buses is violated all times
and minimum switching is assured. The feasibility of the
proposed method has been proven via laboratory experiments.
Furthermore, a low-cost implementation of the control
technique has been shown to provide satisfactory
performance. Therefore, the economical feasibility of the
general-purpose NPC three-level inverter in low voltage drive
applications has been strengthened and its application range
widened.
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[10] R. S. Kanchan, P. N. Tekwani and K. Gopakumar, Three-Level Inverter
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Drive, IEEE transactions on power electronics, vol. 21, no. 6, pp.1976-
1683 November 2006
[11] J. 0. P. Pinto, B. K. Bose, L. E. B. Da Silva and M. P. Kazmierkowski,
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[12] Kalpesh H. Bhalodi, and Pramod Agrawal, Space Vector Modulation
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voltages, in Proc. Inst. Elect. Eng., Mar. 2005, vol. 152, no. 2, pp. 297
309.

Fig. 11. Line Voltage & Line Current Waveforms at 50 Hz, mi = 1.73,
(X- axis: 1 div = 20 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)

Fig. 12. DC Link Capacitors Voltages Vc1 and Vc2
(X- axis: 1 div = 1 ms, Y- axis: 1 div= 50 V)

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