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Technical Guide

COLOUR TELEVISION GP 3 Chassis Circuit Explanations

Panasonic

Panasonic AVC Networks Kuala Lumpur Malaysia Sdn. Bhd.

Contents
Location of Control & Circuit Boards GP-3 Chassis Block Diagram 1. Ultimate One Chip IC601 1.1 Features 1.2 IIC Bus 1.3 Memory IC 1.4 Reset Circuit 1.5 IC601 Pin Configuration 2. Tuning 2.1 AFT Tuning Operation 3. VIF and Demodulation 4. Deflection Circuit 4a. Horizontal Output Circuit 4b. Vertical Output Circuit 4c. Geomagnetic Circuit 5. Audio Circuit 6. Protection Circuit 7. Power Circuit 7.1 Start-up Circuit 7.2 Output Voltage Control 7.3 Over Voltage Protection Circuit 7.4 Over Current Protection Circuit 7.5 Overload Protection Circuit 7.6 Standby Operation 3 4 7 7 8 9 10 10 13 13 15 16 18 22 24 26 27 30 30 31 31 31 31 31

Location of Control & Circuit Boards


EW- Board L- Board

YUV- Board

A- Board

K- Board

YC- Board

Board Name A-Board YC-Board L-Board K-Board YUV-Board EW-Board

Function Main Board Y/C Separation Board CRT Board Front AV Board Rear YUV Board East-West Drive Board

GP-3 Chassis Block Diagram

UOC IC601

UOC IC601

1.

Ultimate One Chip IC601

Outline
The IC TDA9590N combines the functions of a video processor together with a micro-controller. This IC also has a Teletext Decoder on board. It is simple, efficient instruction set helps making it both economical and fast. The video processor contains VIF, SIF, Video, Chroma and Deflection blocks. It can be applied for PAL/ NTSC/ SECAM system colour TV. TDA9590N incorporates a high performance picture quality compensation circuit in the video section. A crystal oscillator that externally generates 12MHz clock signal for colour demodulation and micro-controller. It also has a built in IC Bus line to set or control various functions. Micro-controller output switching and control signals for the circuit equipped with GP-3 chassis which depends on the commands from remote control transmitter or the circuit equipped with.

1.1

Features

a. Video Processor 1. IF Section Integrated VIF VCO, alignment-free SIF demodulator 2. Video Section Chroma band-pass and trap Y internal base-band delay line Pre / over shoot control White, Blue, black stretch VM signal output 3. Chroma Section PAL/ NTSC/ SECAM decoder TINT control Automatic Colour Limiting (ACL) 4. RGB Section RGB control circuit with Continuous Cathode Calibration RGB cut-off/ drive control by bus 5. Sync./ DEF Section EW output V sawtooth output

b. Micro-controller 80C51 CPU 128 Kbytes program ROM 12Kbytes Data RAM A minimum instruction execution time of 1 s machine cycle Storage of 100 positions / channels On Screen Display (OSD) Output of RGB signal for ON-Screen Display message to be displayed on CRT Data Back-up Storage of tuning, switching, control and adjustment data to the memory (IC1103) and reading out the data Switching and Control Output of the control signal for picture and sound, etc., and switching signal for TV/AV mode and so on Adjustment Output of adjustment levels for OUC (IC601) through IC bus. c. Teletext Decoder Internal RAM memory for 10 page text. Automatic detection of FASTEXT transmission

1.2

IC bus

Fig 1.0 The IC bus is a two bus system consisting of a data line and a clock line. 5V is set for SDA / SCL. [Fig 1.0] Allow a large number of switching and control functions of GP-3 chassis.

The UOC IC601 generates bus signals which control the following hardware configuration. 1. EEPROM IC1103 (C3EBFC000021) These memories are 8k-bit, non-volatile memories of microchips, and bit pattern of 1024 x 8 bits.

2. Sound Processor IC2101 (MSP3460GAB83) The sound processor IC will cover the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. 3. YC Separation IC5550 (MN82362) The YC IC will produce Y and C output for UOC IC601

1.3

Memory IC

Fig 1.1 The memory IC1103 receives the data listed below as supplied from the UOC IC601 through IC bus [Fig 1.1]. It is input or output whenever it is necessary. This memory IC is a non-volatile type, which data is maintained permanently although the power is cut off.

Last Memory Location


These memory locations will contain the following information that must be stored inside even if power to the EEPROM is interrupted. 1. 100 channels of BT voltage and band (VL, VH, U) information. 2. 100 channels of AFC, SKIP, COLOR SYSTEM and SIF information. 3. Last position for each switching mode. 4. Volume data. 5. TV/ AV1/ AV2 mode. 6. Recall ON/ OFF. 7. Power and auto off timer setting. 8. Service mode setting. 9. The COLOUR, NTSC TINT, BRIGHT, CONTRAST and SHARPNESS DAC data, and each SUB-DAC data, CUT-OFF, RGB-DRIVE etc. 10. PICTURE MENU & SOUND MENU. 11. AVL

Pin No. 1 2 3 4 5 6 7 8

Name A0 A1 A2 GND SDA SCL WP VCC

Function GROUND GROUND GROUND GROUND Serial Data In/Out Serial Clock Input GROUND 5V

1.4

Reset circuit

1. Power on reset is generated internally to the UOC IC601; hence no external reset is required. (The TV processor generates the master reset in the system, which in turn will reset the micro-controller.) 2. During power on/off operation, or during a momentary drop in the +B voltage, insufficient voltage supply to UOC IC601 may will occur. Thus, there is a possibility that incorrect operation of the UOC occur. 3. In order to prevent incorrect operation, a resetting pulse is activated until the voltage fed to the UOC is normalized. 4. When the power switch is turned on, if the VDD of the UOC is less than 3.3V then UOC starts to reset. 5. UOC start to function again when VDD becomes more than 3.3V.

1.5
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

IC601 Pin Configuration


Name KEYSCAN AUTO / MANUAL MSP RESET GND (D) AV/TV 4.5V / OTHERS GND (D) SECPLL +8V DECDIG PH2LF PH1LF GND3 DECBG AVL / EWD VDRB VDRA Description Panel key Geomagnetic controlling H: Auto L: Manual H: Normal L: Reset (During power ON) Digital ground for -Controller core and periphery TV / AV search H: AV / Auto Search L: TV H: 4.5MHz L: Other / AV Digital ground of TV-processor SECAM PLL decoupling 2nd supply voltage TV-processor Supply voltage decoupling of digital circuit of TVprocessor Phase-2 filter Phase-1 filter Ground 3 for TV-processor Bandgap decoupling East-West drive output Vertical drive B output Vertical drive A output

10

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

IFIN1 IFIN2 IFREF VSC AGCOUT SIFIN1 SIFIN2 GND2 SNDPLL FSC AUDIO2 AUDIO3 HOUT FBISO DESCDEM QSS / DEAMP EHT / PROTECT PLLIF SIFAGC INTCO IFVO/SVO +8V CVBS1 GND CVBS2 GND CVBS3/Y C WHSTR CVBSO AUDOUT / AMOUT SVM INSSW2 R2/VIN G2/YIN B2/UIN BCLIN BLKIN RO GO BO +3.3V VPE VDDC OSCGND XTALIN XTALOUT RESET +3.3V LED

IF input 1 IF input 2 Reference current input Vertical sawtooth capacitor Tuner AGC output SIF input 1 SIF input 2 Ground 2 for TV-processor Narrow band PLL filter Sub-carrier reference output Audio 2 input Audio 3 input Horizontal output Flyback input / Sandcastle output Decoupling sound demodulator QSS intercarrier output / AM output in stereo applications or deemphasis (front-end audio out) / AM output in mono applications EHT / overvoltage protection input IF-PLL loop filter AGC sound IF Not used IF video output / selected CVBS output Main supply voltage for TV-processor Internal CVBS input Ground for TV-processor External CVBS2 input Ground for TV-processor CVBS3/Y input Chroma input White stretch capacitor CVBS output Audio output / AM audio output (volume controlled) Scan velocity modulation output 2nd RGB / YUV insertion input 2nd R input / V (R-Y) input / PR input 2nd G input / Y input 2nd B input / U (B-Y) input / PB input Beam current limiter input Black current input / V-guard input Red output Green output Blue output Analog supply of Teletext decoder and digital supply of TV-processor (3.3V) OTP Programming Voltage Digital supply to core (3.3V) Oscillator ground supply Crystal oscillator input Crystal oscillator output Not used Digital supply to periphery (+3.3V) Red LED (Wake up timer) [Normal] H: STDBY L: Power off

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68 69 70 71 72 73 74 75 76 77 78 79 80

YUV-L (SW) REM-IN STDBY / ON SCL SDA VOLUME GEO-X GEO-Y AV-SW1 AV-SW2 REG / RELAY SYNC_FILTER MUTE

[Wake up] H: ON (1 sec) L: OFF (1 sec) [Protect Mode] 0.5 sec : ON 4 sec : OFF Input for YUV H: YUV Input L: Manual Input for the remote control signal Power ON/OFF switching signal for main power circuit H: ON L: Standby IC-bus clock line (+5V) IC-bus data line (+5V) Tuning PWM output (0 ~ 3.3V) PWM control PWM control AV switch 1 H: AV1/DVD L: TV/AV2 AV switch 2 H: AV2/DVD L: TV/AV1 H: Relay ON L: Relay OFF Sync filter input Monitor defeat controlling H: Monitor defeat L: Defeat OFF

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2.

Tuning

Fig 2.0

1. The purpose of the tuner is to convert the VHF/ UHF TV broadcast signal (RF) into intermediate frequency signal, IF (38.0MHz) [Fig 2.0]. 2. The aerial intercepts the TV signal and amplified by the RF amplifier. 3. The local oscillator generates basic frequency to convert RF signal into IF signal (intermediate signal) in the mixer. 4. GP-3 chassis tuners is a Frequency Synthesizer type. A Frequency Synthesizer is a circuit that generates precise frequency signal by means of a single crystal oscillator in conjunction with frequency dividers and multipliers. Frequency Synthesizer is digital device and it is characterized by discrete steps in frequency rather then adjustability over a continuous range. The steps can be rather large or very small, depending upon the application in which the device to be used. 5. In this tuner, many configurations were combined into tuner like VIF part, band selection IC and also SIF selection part. 6. By using the FS tuner, many different configurations were applied if compared with the Voltage Synthesizer such as BT Voltage and Band Selection. Both data from the BT Voltage and Band Selection were applied to the tuner from UOC by input signal voltage through SDA and SCL bus. 7. PLL function is built in the UOC.

AFT Tuning Operation


1. UOC output AFT by IC Bus [Fig 2.0]. 2. When UOC receives Tuning demand, it sends data to Tuner. If it is without demand, data will be refreshed. 3. IF signal is sent to UOC after the Tuner received the data from UOC. Then, Search Mode is carried out by UOC. The output status is as the following table.

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Read out IF Lock


AFT-W (w) (n)

AFT-C

Frequency range for 1 output fo-1.8MHz --fo-- fo+1.8MHz fo-200kHz --fo-- fo+200kHz fo-50kHz --fo-- fo+50kHz --fo--

IF Lock shows the locked/ unlocked status of IF APC AFT-W shows that the VCO oscillation frequency is within or without the set range (wide/narrow). AFT-C shows higher or lower status than center frequency, fo.

4. UOC is ready to send the next data to Tuner and the whole process repeats. 5. During standby or 1 sec after switch off, UOC will not send data to Tuner. 6. 1 sec after switch ON, UOC will send the data to Tuner.

Search Mode 1) The sequence for searching in GP-3 is set to search from Lower channel to Upper channel. Beside this, it is also set to search from AFT-W (w) to AFT-W (n). 2) The IF center frequency is set to be 38.0MHz. 3) The followings describe the sequence of represent Lower channel to Upper channel searching. The tuned frequency is the point when AFT-C turns from 0 to 1.

AFT-W (w) (n) IF Lock

AFT- C

Repeat the process for AFT-W (n)

Phase 1. IF Lock = 0 while unlocked 2. After Tuner sweep and IF is locked, the IF Lock turns to 1 3. Sweep the Tuner more, AFT- W (w) or (n) turns to 1 4. Sweep the Tuner more, AFT-C turns to 1

0 1 1 1

? 0 1 1

? 0 0 1

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3.

VIF and Demodulation

Outline
1. The VIF circuit generates the necessary VIF signal by passing the receiving signal converted in the tuning circuit through the amplifier with the predetermined selectivity characteristic. 2. The VIF circuit consists of the following parts in the UOC IC601: The video detection circuit employs the synchronous detection system. [ie. when power ON or Tuning, UOC synchronized with VIF signal which is ensured by APC.] The video signal is obtained by switching the reference signal (38.0MHz) which is generated from the VIF signal through VCO (Voltage Controlled Oscillator) and PLL (Phase Locked Loop) in the VIF Detection. VCO and APC circuits generate the frequency signal for detection. AFC circuit keeps Tuner local oscillator frequency constant so that it may not fluctuate due to changes of temperature and voltage during reception.
The IF signal leaving from the Tuner is separated into two paths [Fig 3.0]. One for SIF processing and the other for VIF processing. For VIF processing, it passes through transistor Q102 making up for input loss in X101. VIF signal is applied to SAW filter X101 in order to provide the required bandpass shaping. From X101 the signal is fed to the first stage of VIF amplification. After amplification, the signal is passed to the VIF DETECT. VCO free runs at 38MHz. APC compare the unmodulated portion of VIF frequency with VCO frequency and correct the VCO output until VCO frequency corresponds with that of VIF. Since brightness of picture and depth of colour changes when IF strength of receiving radio wave changes, AGC keep video detection output constant. The IF AGC controls the level of amplification in the VIF AMP while RF AGC controls amplification degree of the RF amplifier of Tuner. After detection, the signal is fed to an external SIF trap circuit to remove / filter the SIF component.

Fig 3.0

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4.

Deflection Circuit

Outline
1. The diagram in Fig 4.0 shows the signal flow for the deflection circuits. 2. The composite video signal is input to IC601 pin 44 and is separated by the horizontal and vertical sync separator circuits in order to provide scan synchronizing pulses. 3. The vertical synchronous signal is fed from pin 16 and 17 of IC601 to pin 1 and 7 of vertical drive IC451. 4. The IC451 consists of vertical drive, vertical output and pump up circuits. It sends sufficient sawtooth current to the vertical deflection coil for vertical scanning. 5. The horizontal synchronous signal from pin 30 of IC601 goes through the H-drive circuit, transistor Q501 and then to the drive transformer T553 in A-Board to produce large driving current needed to drive the horizontal output transistor Q551. 6. The Q551 amplifies the horizontal synchronous signal before sending to the horizontal deflection coil.

Fig 4.0

16

VL/VH

140V

COLLECTOR (FBT)

Horizontal Output Circuit

17

HL / H-DRIVE

a)

Horizontal Output Circuit

Outline 1. The horizontal synchronous pulse output from IC601 pin 30 is then input to the ABoard Horizontal Drive Circuit (Q501, T553). 2. The horizontal drive circuit creates a base current (drive current) fully sufficient to turn the horizontal output circuit (Q551) ON and OFF quickly, and inputs this current to the horizontal output circuit (Q551). 3. The horizontal output circuit (Q551) has the function of sending the deflection current to DY in order to make the electrical beam scans horizontally. Beside this, it also has an additional function of generating a high voltage in the second stage voltage coil of the Flyback Transformer (FBT) and supplying this voltage to the CRT anode pole and the focus pole. 4. A number of voltages are taken for using in Focus, CRT, and Heaters etc from the secondary of the Flyback Transformer.

OFF

ON

OFF

ON

OFF

Base Voltage

H-OUT

3
D

Q551

C561 C565 C568

D556 D557

Collector Current

Coil Current

Damper Current

Collector Voltage

t1

t2 t3 t4

t1 t2 t3 t4

Fig 4.1

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Horizontal Output Operation


1. Tr (Q551) base input does not work until it exceeds a certain level [Fig 4.1]. 2. A positive polarized pulse is added to the base and as the base voltage exceeds a certain level, Tr turns ON. Then the collector current increases and the current flows into the deflection coil (t1- t2). 3. If the base input falls to a certain level, Tr turns OFF. The collector current become zero, but the coil current continues to flow and while charging the resonance capacitor C, it gradually decreases until finally reaching zero (t2-t3). 4. Then discharging begins along the path 3 going to the deflection coil from the resonance capacitor. A current opposes to the present current flows into the deflection coil (t3-t4). 5. Then the deflection coil current begins charging the capacitor with an opposite characteristic in the LC only resonance circuit. 6. However, since the damper diode D is connected, the deflection coil voltage between terminals biases the diode in a forward direction, the deflection coil current does not flow in to the resonance capacitor so the damper current flows into the diode. As a result, the resonance phenomenon is absorbed (t4-t1). 7. When the diode current reaches zero, a positively polarized pulse is added again to the Tr base. Therefore, it returns to Step 1. 8. Thus, operation is repeated from Step 2 to 5 and saw tooth wave flows regularly into the deflection coil. 9. At the moment the Tr turns OFF, a positive flyback pulse voltage greater than the power supply voltage is generated. 10. The flyback transistor uses this flyback pulse to generate the CRT anode voltage, Focus voltage and the Screen voltage.

Horizontal Scanning
Diode modulation method using the bridge circuit formed by the resonance capacitor (C1, C2), damper diode (D1,D2), horizontal deflection coil (H,DY), L1 and modulates the current flowing into horizontal deflection coil (H, DY) with the parabolic wave of the V-rate (vertical parabola) added to the PWM.

i1

Q551 H-OUT

Operation
1. During the first half of the horizontal scanning, which takes place without adding vertical parabolic voltage at PWM [Fig 4.2], i1 and i2 currents flow as power supply and VA becomes VF= VA+VB. Then, during the second half of horizontal scanning, it takes the sum voltage of the counter- electromotive voltage VY generate in the horizontal deflection coil enclosure and the VL generated in L1. This voltage size is fixed by VF= VY+VL because the current that flows is proportioned to the current i1 and i2 that

IC601 15

PWM

FigFig 4.26.2

flowed during the first half of the scanning period.


19

Q551 H-OUT

2. By adding the vertical parabolic voltage for correction to the PWM and it sends current i3 during that first half of scanning [Fig 4.3]. Thus, C4 enclosure voltage decreases and VA supersedes VB. However, since the current IM flows, VA increases and VF is fixed.

IC601 15

PWM

Fig 4.3

3. During the second half of scanning [Fig 4.4], current IM flows, VA increases, VY increases and VB decreases resulting in decrement in VL.
Q551 H-OUT

VA VF VL VY

: C4 enclosed voltage : FBT primary side voltage : counter- electromotive voltage generated at the L1 enclosure : counter- electromotive voltage generated at the H- deflection coil enclosure.

IC601 15

PWM

Fig 4.4

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Vertical Output Circuit

EHT/Protection UOC

DY -Vcc

+Vcc

8V

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b)

Vertical Synchronous Processing Circuit

Outline 1. The main function of this circuit is to produce a sawtooth deflection current and amplify the vertical sawtooth waveform to the vertical deflection coil for vertical scanning. 2. The output IC451 is a vertical IC to provide output deflection current to the vertical coil of the deflection yoke. 3. The vertical sync. pulse output from pin 16 and 17 of IC601 is fed into pin 1 and 7 of IC451. The sawtooth waveform is then compared with the Vref from non-inverting input at pin 7 IC451. Then, sawtooth waveform is then amplified and output through pin 5 IC451 to the vertical deflection coil. 4. The Pump Up circuit in IC451 works along with the external components C406 and D402 to boost the vertical sawtooth waveform peak value. IC451 Vertical Out

+26V

D402

C406 C408 R406 C404 R407

R1 R2

Pin 1 of IC451

Pin 5 of IC451

Fig 4.5

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Signal Flow 1. The vertical drive signal (sawtooth wave voltage) enters IC451 at pin 1 and 7[Fig 4.5]. 2. After the input sawtooth wave voltage is inverted by Tr1(b), it is input into the base of Tr2 and Tr3. 3. The threshold voltage of Tr2 and Tr3 are set by R1 and R2 at the center of the sawtooth wave. While scanning the upper half of the screen, Tr2 switches ON and Tr3 switches OFF. 4. As Tr2 switches ON, the following occurs: +26V is input into pin6 of IC451 via D402. The input +26V is output from pin5 of IC451 via Tr2 to deflection yoke to achieve scan. 5. As a result, a directed magnetic field is generated in DY, and it scans with an electronic beam from the top to the center of the screen. (As this progress, the density of magnetic flux decrease) 6. C408 is charged by the current flowing through DY. The operations of Tr4 and Tr5 are controlled by the vertical pulse. 7. During the scanning period, Tr4 switches to OFF and Tr5 to ON since the vertical pulse is zero. Thus, a current runs to the Tr5 collector via D402 and C406, and +26V charges up C406. 8. Next during the scanning period, Tr3 switches ON and Tr2 turns OFF. Therefore, C406 discharges from pin5 of IC451 via Tr3. 9. At this point, a B-directed magnetic field is generated in DY and an electronic beam is passed from the center to the lower side of the screen. (As this progress, the density of magnetic flux decrease) 10. The scanning process of the lower side is completed and as the flyback line period begins, a vertical pulse is added to the pulse amplification circuit (Tr4 and Tr5 base). 11. During the pulses High period, Tr5 switches OFF and Tr4 switches ON, the +26V added to pin2 is added to pin3 via Tr4. 12. As a result, a current of the opposite direction flows in to C406. Beside this, Tr3 switches OFF and Tr2 switches ON during the scanning period. Therefore, this +26V is added to the +26V discharged by C406 resulting in a 52V of voltage applied to vertical DY. 13. As a result of the above operation, the +B is added to vertical DY only during the vertical flyback line period is doubled, the line period is shortened and the start of raster at the top of the screen is erased. 14. C404 and R407 are included for prevention of abnormal oscillation.

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c)

Geomagnetic Circuit

Outline TVs with 29 in CRTs requires an additional circuit which is used for picture geomagnetic adjustment [Fig 4.6]. This additional circuit is used to cancel the effects of the earths magnetic field. On GP-3 chassis, this geomagnetic circuit is provided in the form of IC4803. Signal Flow 1. The control line from IC601 pin 74 is fed to pin 3 of IC4803 in DC form. 2. When the geomagnetic change in Features Menu, output voltage frequency changes in IC601. 3. Rotation of the picture is achieved by controlling only the output from pin 1 and pin 7 by increasing and decreasing its DC output. 4. Signal is output via pin 1 and 7 and is fed to the rotation coil.

Rotation Coil

IC601 Pin 74

+9V

Fig 4.6

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Audio Circuit

25

5.

Audio Circuit

Outline The SIF circuit is built inside the UOC IC601 in GP-3 chassis. The SIF output from UOC IC601 is sent to Sound Processor IC2101 at pin 60 and pin 67. Then the sound signals are sent to audio amplifier IC2301. Audio Processor Two different sound processors are used in GP-3. IC2101 is used as Sound Processor and IC2301 as Audio Amplifier. a) Sound Processor (IC2101)

Outline
IC2101 is a single-chip multi-standard Sound Processor that simultaneously performs digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM-mono TV sound. It covers the sound processing of all analog TVStandards worldwide (B/G, L, I, D/K, M, M-KOREA, Satellite) for Mono and stereo demodulation. The full sound processing starts with analog SIF signal-in until to process analog AF-out, is done on this single chip. RF Input 1. The analog- to- digital conversion of the pre-selected sound SIF signal from pin 60 (MONO) and pin 67 (STEREO) is done by an A/D-converter. 2. An analog automatic gain circuit (AGC) allows a wide range of inputs level. 3. Then, this converted signal is gone through the demodulation in order to generate the Mono/Stereo sound. AV Input 1. Audio outputs from AV terminals are fed into pin 56 and 57 (AV2), and pin 53 and 54 (AV1). 2. The selected audio signal source then will be processed and output to Audio Amplifier IC2301. 3. At the same time, the selected unprocessed audio signal is also output to IC2101 pin 36 and 37 for Monitor Out purpose. b) Audio Amplifier (IC2301)

Outline
The sound signal from IC2101 pin 27 and 28 is amplified by IC2301 and passes it to loudspeakers.

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6.

Protection Circuit

Outline 1. The main function of the protection circuit is to prevent main chassis of TV set from serious damage when faults occur in the circuit. 2. The protection on the EHT input (Pin 34 of IC601) is intended for overvoltage (X-ray) protection. When this protection is activated, the horizontal drive is directly switched off (protection mode).

PIN 34 OUC

+8V

FBT T501

Q400 X- RAY

Fig 6.0

3. This circuit will function whenever X-ray stage starts operation. The X-ray voltage will trigger Q580 ON Q581 ON D583 ON EHT/ PROTECTION input (Pin 34) pulled HIGH UOC OFF. [Fig 6.0] 4. Therefore, EHT/ PROTECTION input will pull down to latch mode by the emitter of Q581 and circuit will go to shut down mode until reset by main power switch.

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Operation Power Supply Protection Condition 1: power supply interruption during power ON If the power supply is interrupted, pin 34 of IC601 pulled HIGH, then TV set will go to standby (protection mode). Condition 2: circuit malfunction when TV set is already ON If TV set is under ON condition and circuit malfunction happened, pin 34 of IC601 pulled HIGH, then TV set will go to standby (protection mode). Excessive Current in +140V line : When the break over voltage of D520 is exceeded, a HIGH level is applied to the base of Q580. Q520 ON D520 ON Protection circuit ON Pin 34 of UOC High UOC OFF Overvoltage Of CRT Heater in X- Ray Protector Circuit : When the heater voltage exceeds the zener (D511) breakover voltage, a HIGH level is applied to base of Q580. D511 ON (X-ray protector circuit) Protection circuit ON Pin 34 of UOC High UOC OFF Excessive Voltage In Vertical Deflection Chip IC451 : When an error in the vertical deflection circuit occurs, a LOW level is applied to the base of Q400 causing the transistor to switch OFF. A HIGH level is fed via D404 to base of protection Q581. Q400 OFF D404 ON D583 ON Pin 34 of UOC High UOC OFF

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+5V

AC CORD RELAY

VIN IC851

+140V

Power Circuit

29 VIN IC2301 IC802 Q857

7.

Power Circuit

Outline

The supply voltage for the main power supply circuit is fed to the bridge rectifier D803 where the AC voltage is fully rectified and smoothed. [Fig 7.0].

Fig 7.0

7.1 Start-Up Circuit 1. The start-up circuit detects Vin terminal (pin 4 IC801) voltage, and makes the control IC (IC801) start and stop. 2. At start-up, C816 is charged through the start-up resistor R818. Once the Vin terminal pin 4 voltage reaches 18.2V, the control circuit starts operating by the function of the start-up circuit. 3. After the control circuit starts its operation, power supply is fed to pin 4 by smoothing and rectifying the voltage of the drive winding (V2-V1) through R817, C816 and D817. 4. The drive winding voltage does not increase to the set voltage after the control circuit starts its operation, and the Vin terminal voltage starts decreasing. 5. However, because the shutdown voltage is set as low as 9.6V, the drive winding voltage reaches stabilizing voltage before falling to the operation stop voltage, and the control circuit continues its operation. 6. If voltage at pin 4 is below 9.6V, IC801 stop functioning.

7.2 Output Voltage Control 1. Output voltage is controlled by voltage at pin 7 of IC801. This control system is called DC bias control system. 2. Threshold voltage of the internal oscillation circuit at pin 7 of IC801 is 0.95V. 3. Voltage at pin 7 is determined by feedback current flow through R820, R821 and R830.

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7.3 Over Voltage Protection Circuit 1. When the voltage imposed between Vin and Ground terminals exceeds 27.5V, this circuit starts its operation and turns latch-mode, and the control IC stops its oscillation. 2. Although this circuit basically functions as protection of the Vin terminal, it also prevents overvoltage at the secondary output (ie open circuited or by some other event), since the Vin terminal voltage is supplied from the drive winding of the transformer, whose voltage is proportional to the output voltage from the secondary windings. 7.4 Over Current Protection Circuit 1. This is a pulse-by-pulse type overcurrent protection circuit, which detects the peak of the MOSFET drain current per pulse and reverses the oscillator output. 2. When the output voltage drops in the overload condition, the drive winding voltage of the primary side also goes down proportionally, and the Vin terminal voltage drops below the shutdown voltage to stop the operation. 3. In this case, as the circuit current also decreases simultaneously, the Vin terminal voltage increases again and the circuit operates intermittently by restoring the operation start voltage. 4. R830 and C825 construct the filter circuit that prevents malfunctions caused by the surge current generating at the MOSFET turn-ON. Threshold voltage at pin 7 is 0.95V. 7.5 Overload Protection Circuit 1. When the output voltage at secondary side falls below the overload mode, the auxiliary winding voltage of the primary side also falls proportionally, and the Vin terminal voltage falls below shutdown voltage to stop the operation. 2. Thus, the error-amplifier and photo-coupler in secondary side will be cut-off. 3. Threshold voltage at pin 5 is 5V. 7.6 Stand- by Operation 1. During standby operation, output voltage is decreased. 2. At the same time V2-V1 winding voltage is decreased, voltage at pin 4 also drops. It reaches operation stop voltage and IC801 stops its operation. 3. IC801 operates again when pin 4 voltage reaches the operation starting voltage when current flows through R818 and C816. The operation is repeated. 4. D862 and R867 are designed in such a way that when output voltage drops, error amplifier gain is reduced. Thus, resulting lower feedback current to IC801.

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