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3
i ) (t
2
i ) (t
) (t
1
i
) (
3
t e
) (
2
t e
) (
1
t e
3
u ) (t
2
u ) (t
) (t
1
u
+
+
+
C
PWM
) (k
) (
e
) (k
) (t sw
i t) (
dc
dc-link VSC Rectifier Line Filter Grid
Generator
Turbine
sample and hold
3/2
sample and hold
3
i t) (
v
) (k
) (
i
2 2
dc
k u ) (
i k) (
dc
Vector Current Controller
+
Dc-link Voltage
Controller
G
Fig.1. Grid-connected VSC in variable-speed wind turbine application.
II. DETECTION METHODS OF SYMMETRICAL COMPONENTS
Correct operation of VSC controllers during grid disturbances
requires a fast and accurate on-line detection of positive and
2419
0-7803-7116-X/01/$10.00 (C) 2001 IEEE
- 2 -
negative phase-sequence components. In this Section, four
on-line sequence separation methods (SSMs) implemented in
rotating frames are analyzed. These methods are based on
notch-filter; band-stop filter (BS); low-pass filter (LP) and
delayed signal cancellation (DSC) [7]. For all detection
methods, the grid frequency
N
f is 50 Hz and the sampling
time
s
T is 200 s. The transformation angle ) (k is
synchronized with the grid flux vector and is not affected by
the applied dips.
Positive sequence components appear as dc quantities in the
dqp-frame rotating positively with the grid angular frequency,
while negative sequence components appear as 100 Hz
components. On the contrary, in the dqn-frame, rotating
clockwise with the grid angular frequency, positive sequence
components appear as 100 Hz quantities while the negative
ones appear as dc components. Thus, sequence components
can be detected using filters that cut-off the second order
harmonic.
delayed
by T/4
-
+
+
dq
n
dq
p 1/2
1/2
3/2 j
+
e
-j
e
j dq
n
dq
p
Notch
Notch 3/2
3/2
e
-j
e
j dq
n
dq
p
Band stop
Band stop
3/2
e
-j
e
j
Low Pass
Low Pass
dq
n
dq
p
(a)
(b)
(c) (d)
e
-j
e
j
Fig.2. On-line sequence separation methods. (a): band stop filter, (b):
notch filter, (c): low-pass filter; (d): delayed signal cancellation.
A. Notch filter
The notch filter contains a deep notch at
0
in its frequency
response and has the following the transfer function [7,8]:
2 2 1
0
2 1
0
F
cos 2 1
cos 2 1
) ( G
+
+
=
z r rz
z z
K z
F
(1)
where
s
T
0 0
= and
F
K is the gain, set equal to
1 cos 2 1
cos 2 1
0
2
0
+
+
=
r r
K
F
(2)
in order to obtain unity dc-gain.
Two step responses, using r=0.95 and r=0.25, respectively,
have been simulated. The steady-state performance of the
filter with r=0.95 is satisfactory, since it cuts off the 100 Hz
component of the signal. However, the transient performance
is rather slow. The transient lasts almost 120 samples
(24 ms). The step response that uses r=0.25 shows a fast
transient response of 10 samples (2 ms). The gain
F
K
introduced to force the dc-component to unity is large (36),
thus producing large transient overshoots. It can be concluded
that the notch filter detects symmetrical components in the
dqp- and dqn-frame by cutting-off the second order harmonic
but it responds too slowly.
B. Band-stop and low-pass filters
The BS-filter can be designed so that its frequency response
characteristics are similar to the notch filter. Narrowing the
frequency range reduces the bandwidth, thus obtaining a slow
and oscillating transient response. A faster transient
performance has been obtained by using low-order filters. For
instance, the step response of a 1
st
order Butterworth BS-filter
with a stop band between 57 and 175 Hz has been calculated.
The filter cuts off the 100 Hz component, but the transient
response is rather slow, approximately 80 samples (16 ms).
To attenuate the 100 Hz component with LP-filters, the best
arrangement between the cut-off frequency and the filter
order has to be found: the lower the cut-off frequency, the
slower the transient response; the lower the order, the faster
the transient response. An example is a 6
th
order Butterworth
LP-filter with a cut-off frequency of 25 Hz. The 100 Hz
component is cancelled out, but the transient lasts
400 samples (80 ms). In conclusion, SSMs based on filtering
techniques are not suitable for applications in which high
bandwidth operation is demanded.
C. Delayed signal cancellation
An effective detection method both for its steady state and
transient performance is the DSC method. The method, when
applied on the grid voltages in the fixed -plane is defined
by the expressions
( ) ( ) 4 / j ) ( 5 . 0 ) (
) ( ) ( ) (
T t e t e t e
pos
+ =
(3)
( ) ( ) 4 / j ) ( 5 . 0 ) (
) ( ) ( ) (
T t e t e t e
neg
=
(4)
where T is the period of the fundamental frequency. The
proposed method implies delaying the signal by one fourth of
period at the fundamental frequency (5 ms), which constitutes
its inherent time delay. Positive and negative sequence
components thus obtained are then transformed into the dqp-
and the dqn-frame, respectively.
D. Dip responses
To test the effectiveness of the above-described SSMs, a
50 % B dip has been simulated. Due to the dip, the voltage
amplitude in phase one is reduced down to 50 %. In Fig. 5,
the positive q-components of the grid voltages are shown.
The SSM using LP-filters (Fig.5a) is very slow compared
with the other tested methods (note the different x-axis scale).
The SSMs using BS-filter (Fig.5b) and notch filter with
r=0.95 (Fig.5c), showing almost the same response, are not
fast enough. By using the notch filter with r=0.25 (Fig.5e),
steady state is established within 2 ms. Unfortunately, the
2420
- 3 -
highly amplified response during the transients causes
inappropriate effects, such as overmodulation. The best
solution has been found to be the method using the DSC
(Fig.5d) both for its accuracy and transient response. Thus,
the DSC has been adopted in the forthcoming simulations.
0 50 100 150 200 250
0.8
0.9
1
1.1
e
q
p
[
p
u
]
(a)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p
[
p
u
]
(b)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p
[
p
u
]
(c)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p
[
p
u
]
(d)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
Time [ms]
e
q
p
[
p
u
]
(e)
Fig. 5: Positive sequence q-components of grid voltages during 50% B dip.
(Solid line) SSM dip response,(dotted line) ideal response. (a) LP-filter (6
th
order Butterworth, 25 Hz), (b) BS-filter (1
st
order Butterworth, 57 to
175 Hz), (c) notch filter (r=0.95), (d) DSC, (e) notch filter (r=0.25).
TABLE 1
SYSTEM PARAMETERS.
E=400 V=1 pu udc=650 V=1 pu fN=50 Hz
L =0.73 mH=0.1 pu R= 23 m=0.01 pu fs=2fsw=5 kHz
VCC: kp=3.7 (deadbeat) kI=
3
10 23
u
* ) 123 (
u
) (t sw
3
2
3
dqp
) (k
CC
in
positive SRF
) (k
dqp
dqp
) (
e
) (
i
* ) (dq
i
) (dq
i
) (dq
e
* ) (dq
u
VCC
2
2
2
2
2
2
Fig. 6: Block scheme of VCC that uses positive SRF.
) (k
dqp
) (
i
) (dq
i
+
SSM ) (
e
) (dqp
e
dqp
) (k
CC
in
positive SRF
) (dqn
e
)* (dq
i
+
* ) (dq
u
VCCF
2
3
PWM
* ) (
u
* ) 123 (
u
) (t sw
3
2
3
2
2
2
2
2
2
2
Fig. 7: Block scheme of VCCF that uses positive SRF and feedforward of
negative sequence grid voltage.
dqp
dqn
+
+
) (k ) (k
DVCC
) (dqp
e
) (dqn
e
) (dqn
i
) (dqp
i
* ) (dqp
i
* ) (dqn
i
) (
e
) (
i
CC
in
negative SRF
SSM
SSM
CC
in
positive SRF
2
3
PWM
* ) (
u
* ) 123 (
u
) (t sw
3
2
3
2
2
2
2
2
2
2
2 2
2
Fig. 8: Block scheme of DVCC that uses positive and negative SRF.
IV. OPERATION DURING DIPS
USING CONSTANT DC-LINK VOLTAGE
In this Section, the three controllers are investigated when
the dc-link voltage is constant and a 50 % B dip occurs at
20 ms and ends at 80 ms. The positive-sequence components
2421
- 4 -
of active and reactive reference currents are
qp
i =0.50 pu and
dp
i =0.20 pu, respectively. As shown in Fig.9, the phase
currents when using VCC are unbalanced during the dip,
whereas when using VCCF and DVCC they are balanced and
thus not affected by the dip. This proves that the controller
should deal both with positive and negative sequence
voltages to track the reference currents correctly when the dc-
link voltage is fixed.
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,
i2
,
i3
[
p
u
]
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,
i2
,
i3
[
p
u
]
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,
i2
,
i3
[
p
u
]
Fig. 9: VSC current during 50 % B dip using constant dc-link voltage.
(Top) VCC, (middle) VCCF, (bottom) DVCC.
TABLE 2
SYSTEM PARAMETERS FOR DC-LINK VOLTAGE CONTROLLER
kFF =0.81 kp,dc=0.55 (VCC) kp,dc=0.17 (DVCC)
C=550F (1.7 ms) TI,dc=2 ms (VCC) TI,dc=10 ms (DVCC)
V. CONTROL OF DC-LINK VOLTAGE
In most applications the grid-connected VSC must control
and keep the voltage of the dc-link constant independently of
the load behavior. In this configuration, called weak dc
grid, the link consists of a capacitor C . The current from the
capacitor to the VSC is denoted by
v
i and the load current is
denoted by
dc
i . Two dc-link voltage controllers, one for both
VCC and VCCF and one for DVCC, are presented here. Both
dc-link parameters are listed in Table 2.
A. Dc-link controller when using VCC and VCCF
This controller uses a PI-regulator to eliminate the
deviation between the reference dc-link voltage
dc
u and the
dc-link voltage
dc
u . To decrease the voltage fluctuations a
feed-forward, denoted by F.F., of the load current
dc
i is used.
The feed-forward gain is determined from power invariance
between ac and dc side of the VSC. The controller output
constitutes the reference active current
q
i for the CC. The
block scheme of the system including the dc-link is shown in
Fig.10. When deriving the parameters of the PI-controller, the
current response of the VSC is assumed to be instantaneous.
The poles of the closed-loop system are selected as double
poles. To obtain a stable response with minimum voltage
overshoot that is still free of damping, a factor of 7 . 0 = is
selected. If the capacitor size and the integral time are fixed,
the proportional gain can be calculated.
dc
u
dc
i
=
C
+
F.F.
+
+
dc
u
*
dc
u
*
dp
i
*
qp
i
v
i
v dc
i i
+
+
+