SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

64Mb H-die SDRAM Specification

54 TSOP-II with Pb-Free (RoHS compliant)

Revision 1.3 August 2004

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

Revision History Revision 1.0 (September, 2003)
Finalized

CMOS SDRAM

Revision 1.1 (October, 2003)

Deleted speed -7C and AC parameter notes 5.

Revision 1.2 (May, 2004)

Added Note 5. sentense of tRDL parameter

Revision 1.3 (August, 2004)

Corrected typo.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM

FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (4K cycle)

Pb-free Package
RoHS compliant

GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Ordering Information
Part No. K4S640432H-UC(L)75 K4S640832H-UC(L)75 K4S641632H-UC(L)60 K4S641632H-UC(L)70 K4S641632H-UC(L)75 4Mb x 16 Orgainization 16Mb x 4 8Mb x 8 Max Freq. 133MHz(CL=3) 133MHz(CL=3) 166MHz(CL=3) 143MHz(CL=3) 133MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package

Organization 16Mx4 8Mx8 4Mx16

Row Address A0~A11 A0~A11 A0~A11

Column Address A0-A9 A0-A8 A0-A7

Row & Column address configuration

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

Package Physical Dimension

CMOS SDRAM

0~8C 0.25 TYP 0.010 #54 #28 0.45~0.75 0.018~0.030 0.05 MIN 0.002 ( 0.50 ) 0.020

11.760.20 0.4630.008

#1 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.71 ) 0.028
0.10 0.004

#27

0.21 0.008

0.05 0.002

1.00 0.039

0.10 0.004

0.30 -0.05 0.004 0.012 + -0.002

+0.10

0.80 0.0315

54Pin TSOP(II) Package Dimension

10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 1.20 MAX 0.047

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

FUNCTIONAL BLOCK DIAGRAM

CMOS SDRAM

I/O Control

LWE LDQM

Data Input Register Bank Select 4M x 4 / 2M x 8 / 1M x 16 Sense AMP 4M x 4 / 2M x 8 / 1M x 16 4M x 4 / 2M x 8 / 1M x 16 4M x 4 / 2M x 8 / 1M x 16 Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK ADD

Column Decoder Col. Buffer Latency & Burst Length

LRAS

LCBR

LCKE LRAS LCBR LWE LCAS Timing Register

Programming Register LWCBR LDQM

CLK

CKE

CS

RAS

CAS

WE

L(U)DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

PIN CONFIGURATION (Top view) x8 x4 x16
VDD VDD VDD DQ0 DQ0 N.C VDDQ VDDQ VDDQ DQ1 N.C N.C DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 N.C N.C DQ4 DQ2 N.C VDDQ VDDQ VDDQ DQ5 N.C N.C DQ6 DQ3 DQ1 VSSQ VSSQ VSSQ DQ7 N.C N.C VDD VDD VDD LDQM N.C N.C WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

CMOS SDRAM
x4
VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS

x8
VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS

x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS

54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.

CKE

Clock enable

A0 ~ A11

Address

BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ X15 VDD/VSS VDDQ/VSSQ N.C/RFU

Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50

CMOS SDRAM
Unit V V C W mA

Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS
Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note

Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE
Clock

(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note 1 2 2 3

RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ3

Notes : 1. -75 only specify a maximum value of 3.5pF 2. -75 only specify a maximum value of 3.8pF 3. -75 only specify a maximum value of 6.0pF

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

(Recommended operating condition unless otherwise noted, TA = 0 to 70C for x4, x8) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Version 75 75 1 1 15

CMOS SDRAM

DC CHARACTERISTICS

Unit

Note

ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS

mA mA

mA 6 3 3 30 mA 25 mA

Operating current (Burst mode) Refresh current Self refresh current

ICC4

115

mA

ICC5 ICC6

135 1 400

mA mA uA

2 3 4

Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S6404(08)32H-TC** 4. K4S6404(08)32H-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

DC CHARACTERISTICS
Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) (Recommended operating condition unless otherwise noted, TA = 0 to 70C for x16 only) Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Test Condition

CMOS SDRAM

Version
60 70 75

Unit

Note

ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS

140

115
1 1 15

110

mA mA

mA
6 3 3 30

mA

mA
25

Operating current (Burst mode) Refresh current Self refresh current

ICC4

160

140

135

mA

ICC5 ICC6

160

140
1 400

135

mA mA uA

2 3 4

Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632H-TC** 4. K4S641632H-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V

CMOS SDRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V

Unit V V ns V

1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50

50

30pF

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol 60 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency = 3 CAS latency = 2 60 12 18 18 42 70 14 20 20 49 100 68 2 2 CLK + tRP 1 1 1 2 1 65 75 15 20 20 45 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 2.5 2.5 2.5 1.5 1 1 5 tSAC Symbol Min CLK cycle time tCC 6 5 3 3 3 2 1 1 6 60 Max 1000 Min 7 6 3 3 2.5 2.5 1.5 0.8 1 70 Max 1000 Min 7.5 10

CMOS SDRAM
75 Max 1000 5.4 6 ns ns ns ns ns ns 5.4 6 ns 2 3 3 3 3 2 ns 1

Unit

Note

ns

1,2

Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2

Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.30 3.00 2.70 2.50 1.95 1.80 1.65 1.50 1.40 1.00 0.20 133MHz Min I (mA) -0.35 -3.75 -6.65 -13.75 -17.75 -20.55 -23.55 -26.2 -36.25 -46.5 133MHz Max I (mA) -1.68 -19.11 -51.87 -90.44 -107.31 -137.9 -158.34 -173.6 -188.79 -199.01 -241.15 -351.68 0 0 -100 -200 mA -300 -400 -500 -600 Voltage
IOH Min (133MHz)

CMOS SDRAM
133MHz Pull-up 0.5 1 1.5 2 2.5 3 3.5

IOH Max (133MHz)

133MHz Pull-down

IOL Characteristics (Pull-down)

Voltage (V) 3.45 3.30 3.00 1.95 1.80 1.65 1.50 1.40 1.00 0.85 0.65 0.40 133MHz Min I (mA) 43.92 43.36 41.20 40.56 39.60 38.40 37.28 30.08 26.64 21.52 14.16 133MHz Max I (mA) 155.82 153.72 148.40 146.02 141.75 136.08 131.39 105.84 93.66 75.25 49.14

250

200

150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5

Voltage
IOL Min (133MHz)

IOL Max (133MHz)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM
Minimum VDD clamp current (Referenced to VDD) 20

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31

15

mA

10

0 0 1 Voltage
I (mA)

Minimum VSS clamp current

VSS Clamp @ CLK, CKE, CS, DQM & DQ

VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60

-3

-2

-1

Voltage
I (mA)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1

CMOS SDRAM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
A10/AP A11, A9 ~ A0 Note

H H L H H H H

X H L H X X X X X L H L H

L L L H L L L L L H L X H L H L H L

L L H X L H H H L X V X X H X V X X H

L L H X H L L H H X V X X H X V X H

L H H X H H L L L X V X X H X V X H

X X X X X X X X X X X V X V V V

OP code X X Row address L H L H X L H X X

Column address Column address

1,2 3 3 3 3 4 4,5 4 4,5 6

Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable

H H L H L H H

Clock suspend or active power down

X X V X X X 7

Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.3 August 2004