Layout Tutorial for Mentor

Designing the layout of an Inverter and carrying out DRC/LVS/PEX

First Draw the schematic

Layout
Go to cell view, right click New View and select view type as Layout A Layout panel window will be displayed For designing inverter we need one n-mos and one p-mos This tutorial will go in a particular set of steps, but one need not follow similar steps for designing, one may design in his/her way. There are no rule as of what should be drawn earlier n-mos or p-mos and there are no restriction in what should be placed first an active area or poly or a well. One neednt worry about the layers, it automatically assign layers But do follow design rules(which are function of )

N-mos
First we will draw active area(ACTIVE 43). To go about it we select ACTIVE 43 from layer selection window on right side of the panel, then we click on ADD Rectangle icon(icon above ruler icon in the left of the panel). Our channel for n-mos is 2(L) X 4 (W). The minor spacing between two dots is 1. Channel length is specified by length of poly not of active area, and channel width is width of poly and active overlap

The black background is a p-substrate so one neednt draw P-well

Placing poly( defining Channel)

POLY 46

Defining source drain and Implanting

N-mos source and drain are n+ doped(using N_PLUS 45) and body is p+ doped (P_PLUS 44) As we have to make contacts the area of Source/Drain has been extended.

Designing P-mos
P-mos is drawn on n-substrate, so we need to draw n-well (N_WELL 42) Rest design is similar to n-mos, with channel dim. 2 X 8 , source and drain doped with p+ and body with n+

Defining contacts
To define contact for active, poly use CONTACT_TO_ACTIVE 48 , Contact_To_Poly 47 resp. Contact are always of size 2 X 2 Then route the design using metal (METAL1 49)

Ports are placed on metal using METAL1_PORT 2 To name port click on Add Text (icon above the Add Rectangle icon) Select layer Metal1.port and write in Value the name of port same as that written in schematic and click Hide and place the text inside Metal1.port If you have defined GND and VDD port separately as input ports in schematic you need to define the same name here as well. But if you dont assign port for VDD or GND in schematic, they are treated globally and you need to assign name as VDD! and GND! when assigning name using ADD Text in layout.

Placing ports

Final Design

DRC check
Once we have completed the design, click on check and save icon(top left). Now we will check our design. Go to Tools->Calibre->Run DRC Click on Input tab and select file INV.calibre.gds if already not selected. Note INV is the view name, if you have given some other name as view name while creating view initially, that name will be there in place of INV. Hit on Run DRC, hit OK If all design is made pertaining to design rules, no error will be displayed or else if you have committed some error. It will display the error, its location and its explanation and you have to rectify error and then run DRC again.

LVS
Go to Tools->Calibre->Run LVS Click on tab Inputs and select files in Layout as INV.calibre.gds and files in Netlist as INV.calibre.src.net if already not selected. If selected files are correct the Layout tab and Netlist tab will turn green which would have been red earlier. Hit Run LVS, click ok then click *cancel in Open connectivity View. This will open a window saying Open logic by Name , click on Browse and hit back twice and then give path logic views>INV>tsmc018. Click ok and the path of the logic file will be displayed in the Logic Name text box. Hit ok If LVS is correct It will display a window showing Designs Match If design doesnt match, the most frequent error is of not defining ports correctly or the name of ports are different in schematic than that in layout. Rectify the error and run LVS again.

PEX
Go to Tools->Calibre->Run PEX Inputs Files will be same as that in LVS Specify the outfile path with name as INV.pex.netlist Then hit Run PEX which will generate a spice netlist file containing the specification of Layout(such as area of source and drain etc) at specified location given in output file path.

Spice file