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Counter Terminology 1
A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances on state for each clock pulse. State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter.
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Counter Terminology 2
Count Sequence: The specific series of output states through which a counter progresses. Modulus: The number of states through which a counter sequences before repeating (mod-n). Counter directions:
UP - count low to high (LSB to MSB). DOWN - count high to low (MSB to LSB)
Up and Down/
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Counter Modulus
Modulus of a counter is the number of states through which a counter progresses. A Mod-12 UP Counter counts 12 states from 0000 (010) to 1011 (1110). The process then repeats. A Mod-12 DOWN counter counts from 1011 (1110) to 0000 (010), then repeats.
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State Diagram
A diagram that shows the progressive states of a sequential circuit. The progression from one state to the next state is shown by an arrow.
(0000 0001 0010).
Each state progression is caused by a pulse on the clock to the sequential circuit.
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Truncated Counters 1
An n-bit counter that counts the maximum modulus (2n) is called a fullsequence counter such as Mod 2, Mod 4, Mod 8, etc. An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4).
Truncated Counters 2
A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter. A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter.
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Truncated Counters 3
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Synchronous Counters
A counter whose flip-flops are all clocked by the same source and change state in synchronization. The memory section keeps track of the present state. The control section directs the counter to the next state using command and status lines.
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Synchronous Counters
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J 0 = Q2 K0 = 1
J1 = Q0 K1 = Q0
J 2 = Q1 Q0 K2 = 1
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Q2Q1Q0
000 001 010 011 100
J2K2
01 01 01 11 01 (R) (R) (R) (T) (R)
J1K1
00 11 00 11 00 (NC) (T) (NC) (T) (NC)
J0K0
11 11 11 11 01 (T) (T) (T) (T) (R)
Q2Q1Q0
001 010 011 100 000
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VHDL UP Counter
-- simple_int_counter.vhd -- 8-bit synchronous counter with asynchronous clear. -- Uses INTEGER type for counter output. LIBRARY ieee; USE ieee.std_logic_1164.ALL;
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LPM Counters 1
The Altera LPM (Library of Parameterized Modules) counter can be used to create counter designs in VHDL. This is a structured design approach that uses the LPM-counter as a component in a hierarchy. The LPM counter is instantiated in the structured design.
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LPM Counters 2
The basic parameters of the LPM counter, such as width, are defined with a generic map. The port map is used to connect LPM counter I/O to the actual VHDL design entity.
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Bi-Directional Counter
Adds a direction Input (DIR) to the counter and the control logic for up or down counting. Basic counter element is shown in Figure 9.50. The control logic selects the up or down count logic depending on the state of DIR.
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DIN
MSB
LSB
SS Left Shift 1
Q3 D3 < Q2 D2 < Q1 D1 < Q0 D0 < CLK DIN
MSB
LSB
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SS Left Shift 2
Q3 D3 < Q2 D2 < Q1 D1 < Q0 D0 < CLK DIN
MSB
LSB
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SS Left Shift 3
Q3 D3 < Q2 D2 < Q1 D1 < Q0 D0 < CLK DIN
MSB
LSB
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SS Left Shift 4
Q3 D3 < Q2 D2 < Q1 D1 < Q0 D0 < CLK DIN
MSB
LSB
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Universal SR
Combines the basic functions of a Parallel Load SR with a Bi-Directional SR. Uses Two Control Inputs (S1,S0) to select the function as shown in Figure 9.95.
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Universal SR
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Structured VHDL SR
Structured VHDL Design: A VHDL design technique that connects predesigned components using internal signals. Would use DFF primitives to construct different types such as LSR and RSR. A DFF Primitive Port Map is (D, CLK, Q).
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VHDL SR Entity 1
Basic Entity for a Structural RSR Design
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; -- Note: IEEE is before Altera declarations -- maxplus2 is for the primitive DFF Design
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VHDL SR Entity 2
Port description of RSR Entity
ENTITY srg4strc IS PORT( serial_in, clk : IN STD_LOGIC; qo END srg4strc; -- The 4 Bit Register is given a type Buffer to allow -- Q0 Q3 to be used as Input or Output :BUFFER STD_LOGIC_VECTOR(3 downto 0));
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Bi-Directional SR VHDL 1
Adds a basic direction control to the dataflow architecture given earlier.
PROCESS(clk, clear) BEGIN IF clear = 0 THEN q <= (others => 0); -- asynchronous clear ELSEIF (clkEVENT and clk = 1) THEN
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Bi-Directional SR VHDL 2
VHDL Architecture Continued
CASE direction IS WHEN 0 => q <= q(2 downto 0) & lsi; -- Left Shift WHEN 1 => q <= rsi & q(3 downto 1); -- Right Shift WHEN OTHERS => Null; END CASE; END IF; END PROCESS; END bidirectional_shift;
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serial_out:OUT STD_LOGIC);
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LPM SR Architecture
ARCHITECTURE lpm_shift OF srg8_lpm2 IS BEGIN Shift_8 : lpm_shiftreg GENERIC MAP (LPM_WIDTH => 8, LPM_DIRECTION => RIGHT) PORT MAP (clock shiftin shiftout END lpm_shift; => clk, => serial_in, => serial_out);
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Ring Counters 1
A basic Ring Counter (Figure 9.102) is constructed of D-FF with a Feedback Loop. Data is initially loaded into the SR by using either Resets or Presets. The counter can circulate a 0 or 1 by loading a 1000 or 0111.
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Ring Counters 2
The Modulus of a Ring Counter is defined as the maximum number of unique states. Modulus is dependent on the initial load value {1000, 0100, 0010, 0001} = Mod4 while {1010, 0101} = Mod2. Typically an N-FF Ring Counter has N-States, not 2N like a binary counter.
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Johnson Counters 1
Johnson Counter: A serial shift register with the complemented feedback from the output of the last FF to the input of the first FF. Same as the Ring Counter sequences based on a continuous rotation of data through the SR.
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Johnson Counters 2
Same as a Ring (Figure 9.106) except that Q0 (Complement) is fed back to D3, not to Q0. Adds a complement or twist to the data and is called a Twisted Ring Counter. Usually Initialized with 0000 by a Clear.
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Johnson Counters 3
Typically has more states than a ring counter. Sequence of states = {0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001}. Maximum Modulus is 2n for a circuit with n flip-flops.
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