reading assignment ET4074 websites of conferences: http://www.microarch.org/ http://isca2012.ittc.ku.edu/ http://www.hpcaconf.

org/ topic: Multi/many-core: energy/power management methods for processor cores [HPCA 2012 IEEE, 18th Edition] Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs JETC: Joint Energy Thermal and Cooling Management for Memory and CPU Subsystems in Servers AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture Dynamically Heterogeneous Cores Through 3D Resource Pooling

[HPCA 2011 IEEE, 17th Edition] - Efficient Complex Operators for Irregular Codes - Dynamically Specialized Datapaths for Energy Efficient Computing - Hardware/Software Techniques for DRAM Thermal Management [HPCA 2010 IEEE, 16th Edition] Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement BOLT: Energy-Efficient Out-of-Order Latency-Tolerant Execution High-Performance, Low-Vcc In-Order Core Architecting for Power Management: The IBM POWER7TM Approach

[HPCA 2009 IEEE, 15th Edition] Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins Reconciling Specialization and Flexibility Through Compound Circuits CAMP: A Technique to Estimate Per-Structure Power at Run-time using a Few Simple Parameters Variation-Aware Dynamic Voltage/Frequency Scaling Bridging the Computation Gap Between Programmable Processors and Hardwired Accelerators

[ISCA 2012, 39th symposium] - Reducing memory reference energy with Opportunistic Virtual Caching - iSwitch: Coordinating and Optimizing Renewable Energy Powered Server Clusters - The Yin and Yang of Power and Performance for Asymmetric Hardware and Manged Software [ISCA 2011, 38th symposium] Energy-efficient mechanisms for managing thread context in throughput processors Dark silicon and the end of multicore scaling Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems Scalable power control for many-core architectures running multi-threaded applications Energy-efficient cache design using variable-strength error-correcting codes

[ISCA 2010, 37th symposium] WiDGET: Wisconsin decoupled grid execution tiles Forwardflow: a scalable core for power-constrained CMPs Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis Understanding sources of inefficiency in general-purpose chips

[ISCA 2009, 36th symposium] A durable and energy efficient main memory using phase change memory technology Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors Thread motion: fine-grained power management for multi-core systems Temperature-constrained power control for chip multiprocessors with online model estimation

[MICRO 2012] not yet available? [MICRO 2011] Active management of timing guardband to save energy in POWER7 Bundled execution of recurring traces for energy-efficient general purpose processing QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores Pack & Cap: adaptive DVFS and thread packing under power caps Preventing PCM banks from seizing too much power CRAM: coded registers for amplified multiporting

[MICRO 2010] Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling Combating Aging with the Colt Duty Cycle Equalizer Erasing Core Boundaries for Robust and Configurable Performance Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors Understanding the Energy Consumption of Dynamic Random Access Memories

[MICRO 2009] - Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures - A microarchitecture-based framework for pre- and post-silicon power delivery analysis - Reducing peak power with a table-driven adaptive processor core