Datasheet Controlador de Display LCD TFT SSD1289

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1289
Advance Information
240 RGB x 320 TFT LCD Controller Driver
integrated Power Circuit, Gate and Source Driver
with built-in RAM
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1289
Rev 1.3
P 1/82
Apr 2007
Copyright 2007 Solomon Systech Limited
CONTENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GENERAL DESCRIPTION ......................................................................................... 5

FEATURES................................................................................................................. 6
ORDERING INFORMATION....................................................................................... 7
BLOCK DIAGRAM ..................................................................................................... 8
DIE PAD FLOOR PLAN ............................................................................................. 9
PIN DESCRIPTION................................................................................................... 17
BLOCK FUNCTION DESCRIPTION......................................................................... 21
COMMAND TABLE .................................................................................................. 24
COMMAND DESCRIPTION...................................................................................... 27
GAMMA ADJUSTMENT FUNCTION ....................................................................... 53
MAXIMUM RATINGS................................................................................................ 60
DC CHARACTERISTICS.......................................................................................... 60
AC CHARACTERISTICS.......................................................................................... 62
GDDRAM ADDRESS................................................................................................ 68
INTERFACE MAPPING ............................................................................................ 69
DISPLAY SETTING SEQUENCE ............................................................................. 72
POWER SUPPLY BLOCK DIAGRAM...................................................................... 75
SSD1289 OUTPUT VOLTAGE RELATIONSHIP ..................................................... 76
APPLICATION CIRCUIT .......................................................................................... 77
PACKAGE INFORMATION ...................................................................................... 81
Solomon Systech
Apr 2007
P 2/82
Rev 1.3
SSD1289
TABLES
Table 3-1 - Ordering Information ......................................................................................................... 7
Table 5-1 - SSD1289 Bump Pad Coordinate (Bump Center)............................................................. 10
Table 6-1- Power Supply Pins ............................................................................................................ 17
Table 6-2 - Interface Logic Pins ......................................................................................................... 18
Table 6-3 - Mode Selection Pins......................................................................................................... 19
Table 6-4 - Driver Output Pins ........................................................................................................... 20
Table 6-5 - Miscellaneous Pins........................................................................................................... 20
Table 7-1 - Data bus selection modes ................................................................................................. 22
Table 7-2 - RGB signal matching in data bus..................................................................................... 22
Table 8-1 - Command Table ............................................................................................................... 24
Table 8-2 - Gamma Registers POR value........................................................................................... 26
Table 8-3 - Registers POR value at GAMAS[2:0] = 000,100 ............................................................ 26
Table 9-1 - 3-field interlace driving.................................................................................................... 31
Table 13-1 - Parallel 6800 Timing Characteristics ............................................................................. 62
Table 13-2 - Parallel 8080 Timing Characteristics ............................................................................. 63
Table 13-3 - Serial Timing Characteristics......................................................................................... 65
Table 15-1 - Interface setting and data bus setting ............................................................................. 69
Table 15-2 - The Function of 6800-series parallel interface............................................................... 69
Table 15-3 - Interface Mode Selection ............................................................................................... 70
SSD1289
Rev 1.3
P 3/82
Apr 2007
Solomon Systech
FIGURES
Figure 4-1 - SSD1289 Block Diagram Description.............................................................................. 8
Figure 5-1 - SSD1289 Pad Arrangement (Bump face up).................................................................... 9
Figure 7-1 - Read Display Data .......................................................................................................... 21
Figure 9-1 - gate output timing in 3-field interlacing driving............................................................. 31
Figure 9-2 - Line Inversion AC Driver ............................................................................................... 32
Figure 9-3 - OTP circuitry .................................................................................................................. 48
Figure 13-1 - Parallel 6800-series Interface Timing Characteristics .................................................. 62
Figure 13-2 - Parallel 8080-series Interface Timing Characteristics .................................................. 64
Figure 13-3 - 4 wire Serial Timing Characteristics ............................................................................ 65
Figure 13-4 - Pixel Clock Timing in RGB interface mode................................................................. 66
Figure 19-1 - Booster Capacitors........................................................................................................ 77
Figure 19-2 - Filtering and charge sharing capacitors ........................................................................ 77
Figure 19-3 - Power supply pin connection........................................................................................ 78
Figure 19-4 - Panel Connection Example........................................................................................... 79
Figure 19-5 - ITO and FPC connection example................................................................................ 80
Solomon Systech
Apr 2007
P 4/82
Rev 1.3
SSD1289
GENERAL DESCRIPTION
SSD1289 is an all in one TFT LCD Controller Driver that integrated the RAM, power circuits, gate driver and
source driver into a single chip. It can drive up to 262k color amorsphous TFT panel with resolution of 240 RGB x 320.
It also integrated the controller function and consists of 172,800 bytes (240 x 320 x 18 / 8) Graphic Display Data RAM
(GDDRAM) such that it interfaced with common MPU through 8-/9-/16-/18-bit 6800-series / 8080-series compatible
parallel interface or serial peripheral interface and stored the data in the GDDRAM. Auxiliary 18-bit video interface
(VSYNC, HSYNC, DOTCLK, DEN) are integrated into SSD1289 for animation image display.
SSD1289 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver with
minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display counter
electrode. An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide
maximum flexibility and optimal display quality.
SSD1289 can be operated down to 1.4V and provide different power save modes. It is suitable for any portable batterydriven applications requiring long operation period and compact size.
SSD1289
Rev 1.3
P 5/82
Apr 2007
Solomon Systech
FEATURES
240RGBx320 single chip controller driver IC for 262k color amorphous TFT LCD
Power Supply
- VDDEXT = 1.4V 3.6V (Internal Logic)
- VDDIO = 1.4V 3.6V (I/O Interface)
- VCI = 2.5V 3.6V (power supply for internal analog circuit)
Output Voltages
- Gate Driver:
VGH-GND = 9V ~ 15V
VGL-GND = -7 ~ -15V
VGH-VGL = 30Vp-p
- Source Driver:
V0 V63 = 0 5V
Typical Source Output Voltage variation: 10 mV
- VCOM drive:
VCOMH = 3.0V ~ 5.0V
VCOML = -2.0V ~ -3.0V
VCOMHA = 5.5V
System Interface
- High-speed interface by 8-/9-/16-/18-bit 6800-series / 8080-series parallel ports
- Serial Peripheral Interface (SPI)
- Moving picture display interface
- 18-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, DB17-0)
- VSYNC interface (system interface + VSYNC)
- WSYNC interface (system interface + WSYNC)
Support low power consumption:
- Low voltage supply
- Low current sleep mode
- 8-color display mode for power saving
- Charge sharing function for step-up circuits
High-speed RAM addressing functions
- RAM write synchronization function
- Window address function
- Display by RAM data and generic data selectively and simultaneously
- Vertical scrolling function
- Picture in Picture mode
- Partial display mode
Internal power supply circuit
- Voltage generator
- DC-DC converter up to 6x/-6x
Built-in internal oscillator
Internal GDDRAM capacity: 172800Byte
Support Frame and Line inversion AC drive
TFT storage capacitance: Cs on common and Cs on gate
Support source and gate scan direction control
Programmable gamma correction curve
4 Preset gamma correction curve
Built-in Non Volatile Memory for VCOM calibration Display Size: 240 RGB x 320
Support flexible arrangement of gate circuits on both sides of the glass substrate
Solomon Systech
Apr 2007
P 6/82
Rev 1.3
SSD1289
ORDERING INFORMATION
Table 3-1 Ordering Information
SSD1289
Ordering Part
Number
Source
Gate
Package Form
SSD1289Z
240 x 3 (720)
320
Gold Bump Die
Rev 1.3
P 7/82
Apr 2007
Reference
Solomon Systech
BLOCK DIAGRAM
Figure 4-1 - SSD1289 Block Diagram Description
G0 to G319
VCOM
VCI
VDDEXT
VDDIO
VDD
regulator
circuit
Source driver
Regulator
Circuit
Gamma /
Grayscale
Voltage
Generator
REGVDD
SHUT
REV
VCI
CN
CP
C1N
C1P
C2N
C2P
C3N
C3P
CXP
CXN
CYP
CYN
EXTCLK
S0 to S719
Data Latches
Regulator
Circuit
Booster
Circuit
Switches Network
VLCD63
Address
Counter
VGH
VGL
VGOFFH
VGOFFHL
GateDriver
GDDRAM
Timing Generation
System Interface / RGB Interface
OSC
Solomon Systech
Apr 2007
P 8/82
Rev 1.3
GD
BGR
CM
RL
TB
VSYNC
HSYNC
DOTCLK
DEN
D[17:0]
D/C
R/W
CS
PS0-3
RES
WSYNC
VSS/AVSS/
DVSS/VCHS
SSD1289
DIE PAD FLOOR PLAN

Figure 5-1 - SSD1289 Pad Arrangement (Bump face up)
Note
(1)
Diagram showing the die face up.
(2)
Coordinates are referenced to center of the chip.
(3)
Coordinate units and size of all alignment marks are in um.
(4)
All alignment keys do not contain gold bump.
Pin 1
Pin 1336
Alignment Marks:
25
Center:
Size:
50
25 15
25
Center:
Size:
(11802,715.5)
100 x 100 m2
20 15 25
(-11802,715.5)
100 x 100 m2
10
20
20
40 30
Center:
Size:
40 30 40
(-11740,-549.5), (11740,-549.5)
180 x 180 m2
Output Pad Pitch (Gate and source):
Pin 358
115
40
115
22 24
Pin 357
Die Size
Die Thickness
Typical Bump Height
Bump Co-planarity
(within die)
Bump Size 1
Pad Pitch 1
Bump Size 2
Pad Pitch 2
SSD1289
Rev 1.3
P 9/82
Apr 2007
23.984 x 1.600 mm2

406 25 um
15 um
3 um
55 x 117 m2 (Pin 58-300)
85 m
22 x 115 m2 (Pin 1-57, 301-357,
358-1336)
24 m stagger
Solomon Systech
Table 5-1 - SSD1289 Bump Pad Coordinate (Bump Center)

Note: IC material temperature expansion factor is 2.6ppm per degree, customer should take into account during panel design
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
NC
NC
NC
NC
NC
NC
NC
NC
THROUGH1
THROUGH2
G87
G85
G83
G81
G79
G77
G75
G73
G71
G69
G67
G65
G63
G61
G59
G57
G55
G53
G51
G49
G47
G45
G43
G41
G39
G37
G35
G33
G31
G29
G27
G25
G23
G21
G19
G17
G15
G13
G11
G9
G7
G5
G3
G1
DUMMY
NC
NC
DUMMY
VCOM
VCOM
NC
VGH
VGH
VGH
VGH
C2P
C2P
-11928
-11904
-11880
-11856
-11808
-11760
-11712
-11664
-11640
-11616
-11592
-11568
-11544
-11520
-11496
-11472
-11448
-11424
-11400
-11376
-11352
-11328
-11304
-11280
-11256
-11232
-11208
-11184
-11160
-11136
-11112
-11088
-11064
-11040
-11016
-10992
-10968
-10944
-10920
-10896
-10872
-10848
-10824
-10800
-10776
-10752
-10728
-10704
-10680
-10656
-10632
-10608
-10584
-10560
-10536
-10512
-10488
-10285
-10200
-10115
-10030
-9945
-9860
-9775
-9690
-9605
-9520
-547.5
-702.5
-547.5
-702.5
-702.5
-702.5
-702.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
C2N
C2N
C1P
C1P
C1N
C1N
CP
CP
CN
CN
C3P
C3P
C3P
C3P
C3N
C3N
C3N
C3N
VCI
VCI
VCI
VCI
VGL
VGL
VCHS
VCHS
VCHS
VDDIO
GD
VSS
CAD
VDDIO
REV
VSS
GAMAS0
VDDIO
GAMAS1
VSS
GAMAS2
VDDIO
BGR
VSS
TB
VDDIO
RL
VSS
REGVDD
VDDIO
PS2
VSS
PS1
VDDIO
PS0
PS3
SHUT
CM
/RES
/RES
VSYNC
VSYNC
HSYNC
HSYNC
DOTCLK
DOTCLK
DEN
DEN
D17
-9435
-9350
-9265
-9180
-9095
-9010
-8925
-8840
-8755
-8670
-8585
-8500
-8415
-8330
-8245
-8160
-8075
-7990
-7905
-7820
-7735
-7650
-7565
-7480
-7395
-7310
-7225
-7140
-7055
-6970
-6885
-6800
-6715
-6630
-6545
-6460
-6375
-6290
-6205
-6120
-6035
-5950
-5865
-5780
-5695
-5610
-5525
-5440
-5355
-5270
-5185
-5100
-5015
-4930
-4845
-4760
-4675
-4590
-4505
-4420
-4335
-4250
-4165
-4080
-3995
-3910
-3825
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
D17
D16
D16
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
/RD
/RD
/WR
/WR
DC
DC
SDO
SDO
SDI
SDI
SCK
SCK
/CS
/CS
WSYNC
WSYNC
TESTA
TESTB
TESTC
EXTCLK
VREGC
VREGC
VCORE
VCORE
VREGR
VREGR
VRAM
VRAM
VDDEXT
VDDEXT
VDDEXT
VDDEXT
-3740
-3655
-3570
-3485
-3400
-3315
-3230
-3145
-3060
-2975
-2890
-2805
-2720
-2635
-2550
-2465
-2380
-2295
-2210
-2125
-2040
-1955
-1870
-1785
-1700
-1615
-1530
-1445
-1360
-1275
-1190
-1105
-1020
-935
-850
-765
-680
-595
-510
-425
-340
-255
-170
-85
0
85
170
255
340
425
510
595
680
765
850
935
1020
1105
1190
1275
1360
1445
1530
1615
1700
1785
1870
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
Solomon Systech
Apr 2007 P 10/82
Rev 1.3
SSD1289
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
VSSRC
VSSRC
CDUM0
CDUM0
CDUM1
CDUM1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VDDIO
VDDIO
VDDIO
VDDIO
VCI
VCI
VCI
VCI
VCI
VCI
VCIP
VCIP
VCIP
VCIP
VGOFFHL
VGOFFHL
NC
NC
VLCD63
VLCD63
VLCD63
VLCD63
VCOML
VCOML
VCOML
VCOML
VCOMH
VCOMH
VCOMH
VCOMH
VCIM
VCIM
VCIM
VCIM
NC
NC
VCI
VCI
VCI
VCI
VCIX2J
VCIX2J
VCIX2G
VCIX2G
VCIX2
VCIX2
VCIX2
1955
2040
2125
2210
2295
2380
2465
2550
2635
2720
2805
2890
2975
3060
3145
3230
3315
3400
3485
3570
3655
3740
3825
3910
3995
4080
4165
4250
4335
4420
4505
4590
4675
4760
4845
4930
5015
5100
5185
5270
5355
5440
5525
5610
5695
5780
5865
5950
6035
6120
6205
6290
6375
6460
6545
6630
6715
6800
6885
6970
7055
7140
7225
7310
7395
7480
7565
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
VCIX2
CYP
CYP
CYP
CYP
CYP
CYP
CYN
CYN
CYN
CYN
CYN
CYN
VCHS
VCHS
VCHS
VCHS
VCHS
VCHS
CXN
CXN
CXN
CXP
CXP
CXP
VGOFFH
VGOFFH
VCOM
VCOM
VCOM
VCOM
VCOMR
NC
NC
GTESTR
G0
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G32
G34
G36
G38
G40
G42
G44
G46
G48
G50
G52
G54
G56
G58
G60
G62
7650
7735
7820
7905
7990
8075
8160
8245
8330
8415
8500
8585
8670
8755
8840
8925
9010
9095
9180
9265
9350
9435
9520
9605
9690
9775
9860
9945
10030
10115
10200
10285
10488
10512
10536
10560
10584
10608
10632
10656
10680
10704
10728
10752
10776
10800
10824
10848
10872
10896
10920
10944
10968
10992
11016
11040
11064
11088
11112
11136
11160
11184
11208
11232
11256
11280
11304
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-701.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
G64
G66
G68
G70
G72
G74
G76
G78
G80
G82
G84
G86
THROUGH3
THROUGH4
NC
NC
NC
NC
NC
NC
NC
NC
DUMMY
VGL
DUMMY
DUMMY
THROUGH5
THROUGH6
G88
G90
G92
G94
G96
G98
G100
G102
G104
G106
G108
G110
G112
G114
G116
G118
G120
G122
G124
G126
G128
G130
G132
G134
G136
G138
G140
G142
G144
G146
G148
G150
G152
G154
G156
G158
G160
G162
G164
11328
11352
11376
11400
11424
11448
11472
11496
11520
11544
11568
11592
11616
11640
11664
11712
11760
11808
11856
11880
11904
11928
11736
11712
11688
11664
11640
11616
11592
11568
11544
11520
11496
11472
11448
11424
11400
11376
11352
11328
11304
11280
11256
11232
11208
11184
11160
11136
11112
11088
11064
11040
11016
10992
10968
10944
10920
10896
10872
10848
10824
10800
10776
10752
10728
10704
10680
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-547.5
-702.5
-702.5
-702.5
-702.5
-702.5
-547.5
-702.5
-547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
SSD1289
Rev 1.3
P 11/82
Apr 2007
Solomon Systech
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
G166
G168
G170
G172
G174
G176
G178
G180
G182
G184
G186
G188
G190
G192
G194
G196
G198
G200
G202
G204
G206
G208
G210
G212
G214
G216
G218
G220
G222
G224
G226
G228
G230
G232
G234
G236
G238
G240
G242
G244
G246
G248
G250
G252
G254
G256
G258
G260
G262
G264
G266
G268
G270
G272
G274
G276
G278
G280
G282
G284
G286
G288
G290
G292
G294
G296
G298
10656
10632
10608
10584
10560
10536
10512
10488
10464
10440
10416
10392
10368
10344
10320
10296
10272
10248
10224
10200
10176
10152
10128
10104
10080
10056
10032
10008
9984
9960
9936
9912
9888
9864
9840
9816
9792
9768
9744
9720
9696
9672
9648
9624
9600
9576
9552
9528
9504
9480
9456
9432
9408
9384
9360
9336
9312
9288
9264
9240
9216
9192
9168
9144
9120
9096
9072
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
G300
G302
G304
G306
G308
G310
G312
G314
G316
G318
DUMMY
DUMMY
VCOM
VCOM
DUMMY
DUMMY
DUMMY
S719
S718
S717
S716
S715
S714
S713
S712
S711
S710
S709
S708
S707
S706
S705
S704
S703
S702
S701
S700
S699
S698
S697
S696
S695
S694
S693
S692
S691
S690
S689
S688
S687
S686
S685
S684
S683
S682
S681
S680
S679
S678
S677
S676
S675
S674
S673
S672
S671
S670
9048
9024
9000
8976
8952
8928
8904
8880
8856
8832
8808
8784
8760
8736
8712
8688
8664
8640
8616
8592
8568
8544
8520
8496
8472
8448
8424
8400
8376
8352
8328
8304
8280
8256
8232
8208
8184
8160
8136
8112
8088
8064
8040
8016
7992
7968
7944
7920
7896
7872
7848
7824
7800
7776
7752
7728
7704
7680
7656
7632
7608
7584
7560
7536
7512
7488
7464
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
S669
S668
S667
S666
S665
S664
S663
S662
S661
S660
S659
S658
S657
S656
S655
S654
S653
S652
S651
S650
S649
S648
S647
S646
S645
S644
S643
S642
S641
S640
S639
S638
S637
S636
S635
S634
S633
S632
S631
S630
S629
S628
S627
S626
S625
S624
S623
S622
S621
S620
S619
S618
S617
S616
S615
S614
S613
S612
S611
S610
S609
S608
S607
S606
S605
S604
S603
7440
7416
7392
7368
7344
7320
7296
7272
7248
7224
7200
7176
7152
7128
7104
7080
7056
7032
7008
6984
6960
6936
6912
6888
6864
6840
6816
6792
6768
6744
6720
6696
6672
6648
6624
6600
6576
6552
6528
6504
6480
6456
6432
6408
6384
6360
6336
6312
6288
6264
6240
6216
6192
6168
6144
6120
6096
6072
6048
6024
6000
5976
5952
5928
5904
5880
5856
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
Solomon Systech
Apr 2007 P 12/82
Rev 1.3
SSD1289
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
S602
S601
S600
S599
S598
S597
S596
S595
S594
S593
S592
S591
S590
S589
S588
S587
S586
S585
S584
S583
S582
S581
S580
S579
S578
S577
S576
S575
S574
S573
S572
S571
S570
S569
S568
S567
S566
S565
S564
S563
S562
S561
S560
S559
S558
S557
S556
S555
S554
S553
S552
S551
S550
S549
S548
S547
S546
S545
S544
S543
S542
S541
S540
S539
S538
S537
S536
5832
5808
5784
5760
5736
5712
5688
5664
5640
5616
5592
5568
5544
5520
5496
5472
5448
5424
5400
5376
5352
5328
5304
5280
5256
5232
5208
5184
5160
5136
5112
5088
5064
5040
5016
4992
4968
4944
4920
4896
4872
4848
4824
4800
4776
4752
4728
4704
4680
4656
4632
4608
4584
4560
4536
4512
4488
4464
4440
4416
4392
4368
4344
4320
4296
4272
4248
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
S535
S534
S533
S532
S531
S530
S529
S528
S527
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
S516
S515
S514
S513
S512
S511
S510
S509
S508
S507
S506
S505
S504
S503
S502
S501
S500
S499
S498
S497
S496
S495
S494
S493
S492
S491
S490
S489
S488
S487
S486
S485
S484
S483
S482
S481
S480
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
4224
4200
4176
4152
4128
4104
4080
4056
4032
4008
3984
3960
3936
3912
3888
3864
3840
3816
3792
3768
3744
3720
3696
3672
3648
3624
3600
3576
3552
3528
3504
3480
3456
3432
3408
3384
3360
3336
3312
3288
3264
3240
3216
3192
3168
3144
3120
3096
3072
3048
3024
3000
2976
2952
2928
2904
2880
2856
2832
2808
2784
2760
2736
2712
2688
2664
2640
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
S468
S467
S466
S465
S464
S463
S462
S461
S460
S459
S458
S457
S456
S455
S454
S453
S452
S451
S450
S449
S448
S447
S446
S445
S444
S443
S442
S441
S440
S439
S438
S437
S436
S435
S434
S433
S432
S431
S430
S429
S428
S427
S426
S425
S424
S423
S422
S421
S420
S419
S418
S417
S416
S415
S414
S413
S412
S411
S410
S409
S408
S407
S406
S405
S404
S403
S402
2616
2592
2568
2544
2520
2496
2472
2448
2424
2400
2376
2352
2328
2304
2280
2256
2232
2208
2184
2160
2136
2112
2088
2064
2040
2016
1992
1968
1944
1920
1896
1872
1848
1824
1800
1776
1752
1728
1704
1680
1656
1632
1608
1584
1560
1536
1512
1488
1464
1440
1416
1392
1368
1344
1320
1296
1272
1248
1224
1200
1176
1152
1128
1104
1080
1056
1032
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
Rev 1.3
P 13/82
SSD1289
Apr 2007
Solomon Systech
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
S401
S400
S399
S398
S397
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365
S364
S363
S362
S361
S360
DUMMY
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
1008
984
960
936
912
888
864
840
816
792
768
744
720
696
672
648
624
600
576
552
528
504
480
456
432
408
384
360
336
312
288
264
240
216
192
168
144
120
96
72
48
24
0
-24
-48
-72
-96
-120
-144
-168
-192
-216
-240
-264
-288
-312
-336
-360
-384
-408
-432
-456
-480
-504
-528
-552
-576
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
-600
-624
-648
-672
-696
-720
-744
-768
-792
-816
-840
-864
-888
-912
-936
-960
-984
-1008
-1032
-1056
-1080
-1104
-1128
-1152
-1176
-1200
-1224
-1248
-1272
-1296
-1320
-1344
-1368
-1392
-1416
-1440
-1464
-1488
-1512
-1536
-1560
-1584
-1608
-1632
-1656
-1680
-1704
-1728
-1752
-1776
-1800
-1824
-1848
-1872
-1896
-1920
-1944
-1968
-1992
-2016
-2040
-2064
-2088
-2112
-2136
-2160
-2184
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
-2208
-2232
-2256
-2280
-2304
-2328
-2352
-2376
-2400
-2424
-2448
-2472
-2496
-2520
-2544
-2568
-2592
-2616
-2640
-2664
-2688
-2712
-2736
-2760
-2784
-2808
-2832
-2856
-2880
-2904
-2928
-2952
-2976
-3000
-3024
-3048
-3072
-3096
-3120
-3144
-3168
-3192
-3216
-3240
-3264
-3288
-3312
-3336
-3360
-3384
-3408
-3432
-3456
-3480
-3504
-3528
-3552
-3576
-3600
-3624
-3648
-3672
-3696
-3720
-3744
-3768
-3792
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
Solomon Systech
Apr 2007 P 14/82
Rev 1.3
SSD1289
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
S201
S200
S199
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
-3816
-3840
-3864
-3888
-3912
-3936
-3960
-3984
-4008
-4032
-4056
-4080
-4104
-4128
-4152
-4176
-4200
-4224
-4248
-4272
-4296
-4320
-4344
-4368
-4392
-4416
-4440
-4464
-4488
-4512
-4536
-4560
-4584
-4608
-4632
-4656
-4680
-4704
-4728
-4752
-4776
-4800
-4824
-4848
-4872
-4896
-4920
-4944
-4968
-4992
-5016
-5040
-5064
-5088
-5112
-5136
-5160
-5184
-5208
-5232
-5256
-5280
-5304
-5328
-5352
-5376
-5400
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
-5424
-5448
-5472
-5496
-5520
-5544
-5568
-5592
-5616
-5640
-5664
-5688
-5712
-5736
-5760
-5784
-5808
-5832
-5856
-5880
-5904
-5928
-5952
-5976
-6000
-6024
-6048
-6072
-6096
-6120
-6144
-6168
-6192
-6216
-6240
-6264
-6288
-6312
-6336
-6360
-6384
-6408
-6432
-6456
-6480
-6504
-6528
-6552
-6576
-6600
-6624
-6648
-6672
-6696
-6720
-6744
-6768
-6792
-6816
-6840
-6864
-6888
-6912
-6936
-6960
-6984
-7008
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
-7032
-7056
-7080
-7104
-7128
-7152
-7176
-7200
-7224
-7248
-7272
-7296
-7320
-7344
-7368
-7392
-7416
-7440
-7464
-7488
-7512
-7536
-7560
-7584
-7608
-7632
-7656
-7680
-7704
-7728
-7752
-7776
-7800
-7824
-7848
-7872
-7896
-7920
-7944
-7968
-7992
-8016
-8040
-8064
-8088
-8112
-8136
-8160
-8184
-8208
-8232
-8256
-8280
-8304
-8328
-8352
-8376
-8400
-8424
-8448
-8472
-8496
-8520
-8544
-8568
-8592
-8616
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
Rev 1.3
P 15/82
SSD1289
Apr 2007
Solomon Systech
Pad#
Signal
X-pos
Y-pos
Pad#
Signal
X-pos
Y-pos
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
S0
NC
DUMMY
DUMMY
VCOM
VCOM
DUMMY
GTESTL
G319
G317
G315
G313
G311
G309
G307
G305
G303
G301
G299
G297
G295
G293
G291
G289
G287
G285
G283
G281
G279
G277
G275
G273
G271
G269
G267
G265
G263
G261
G259
G257
G255
G253
G251
G249
G247
G245
G243
G241
G239
G237
G235
G233
G231
G229
G227
G225
G223
G221
G219
G217
G215
G213
G211
G209
G207
G205
G203
-8640
-8664
-8688
-8712
-8736
-8760
-8784
-8808
-8832
-8856
-8880
-8904
-8928
-8952
-8976
-9000
-9024
-9048
-9072
-9096
-9120
-9144
-9168
-9192
-9216
-9240
-9264
-9288
-9312
-9336
-9360
-9384
-9408
-9432
-9456
-9480
-9504
-9528
-9552
-9576
-9600
-9624
-9648
-9672
-9696
-9720
-9744
-9768
-9792
-9816
-9840
-9864
-9888
-9912
-9936
-9960
-9984
-10008
-10032
-10056
-10080
-10104
-10128
-10152
-10176
-10200
-10224
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
G201
G199
G197
G195
G193
G191
G189
G187
G185
G183
G181
G179
G177
G175
G173
G171
G169
G167
G165
G163
G161
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G131
G129
G127
G125
G123
G121
G119
G117
G115
G113
G111
G109
G107
G105
G103
G101
G99
G97
G95
G93
G91
G89
THROUGH7
THROUGH8
DUMMY
DUMMY
VGL
DUMMY
-10248
-10272
-10296
-10320
-10344
-10368
-10392
-10416
-10440
-10464
-10488
-10512
-10536
-10560
-10584
-10608
-10632
-10656
-10680
-10704
-10728
-10752
-10776
-10800
-10824
-10848
-10872
-10896
-10920
-10944
-10968
-10992
-11016
-11040
-11064
-11088
-11112
-11136
-11160
-11184
-11208
-11232
-11256
-11280
-11304
-11328
-11352
-11376
-11400
-11424
-11448
-11472
-11496
-11520
-11544
-11568
-11592
-11616
-11640
-11664
-11688
-11712
-11736
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
547.5
702.5
Solomon Systech
Pad#
Signal
Apr 2007 P 16/82
X-pos
Rev 1.3
Y-pos
SSD1289
PIN DESCRIPTION
Remark:
I = Input;
O = Output;
IO = Bi-directional;
P = Power;
VCC = System VDD;
GND = System VSS;
Table 6-1: Power Supply Pins

Name
VSS
AVSS
VSSRC
Type
Connect to
GND
GND
Ground of
the Power
Supply
GND
VCHS
AVSS
VCI
Power Supply
P
VCIP
VCIM
VCI
VCIX2
VCIX2J
VCIX2G
VCOMR
VCOMH
VCOML
VLCD63
CXP
CXN
CYP
CYN
CP
CN
C1P
Voltages for
VCOM
Signal
CDUM0
CDUM1
I
VSS
Rev 1.3
System ground pin of the IC.

Grounding for analog circuit.
Grounding for analog circuit. This pin requires a noise free path for
providing accurate LCD driving voltages.
Grounding for booster circuit.
Booster input voltage pin.
- Connect to voltage source between 2.5V to 3.6V
Voltage supply pin for analog circuit. This pin requires a noise free path
for providing accurate LCD driving voltages.
- Connect to same source of VCI
LCD
Driving
Voltages
Booster and
Stabilization
Capacitors
Stabilization
Capacitors
OSC input
P 17/82
Apr 2007
When not in
use
-
Negative voltage of VCI.
Equals to 2x VCI
They are the power supply used by on chip analog blocks and VGH/VGL
dcdc.
This pin provides voltage reference for internal voltage regulator when
register VDV[4:0] of Power Control 4 set to 01111.
- Connect to an external voltage source for reference
This pin indicates a HIGH level of VCOM generated in driving the
VCOM alternation.
This pin indicates a LOW level of VCOM generated in driving the
VCOM alternation.
Open
-
A positive power output pin for gate driver.
Stabilizing
capacitor to
VCOM or open
Booster
capacitor
Booster
capacitor
Booster
capacitor
Booster
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
Description
This pin is the maximum source driver voltage.
Booster
capacitor
C3P
C3N
SSD1289
External
Reference
C2N
EXTCLK
Voltage for
analog
Stabilizing
capacitor
Booster
capacitor
C1N
C2P
Booster
voltages
Stabilizing
capacitor or
open
VGOFFH
VGOFFHL
Stabilizing
capacitor
Stabilizing
capacitor
VCIX2 on FPC
VCIX2 on FPC
External
voltage source
or Open
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
Power
Supply for
Analog
Circuits
Stabilizing
capacitor
VGH
VGL
Function
This pin is ESD sensitive. It can achieve 2000V ESD (HBM) with connection of external
components in applicaton circuit.
A negative power output pin for gate driver.
When the VGOFF alternation is driven, this pin indicates a high level of
VGOFF.
- Connect a capacitor for stabilization if Cs on gate structure is used
- This pin can be open if Cs on common structure is used
Open
- Connect a capacitor to VCOM if Cs on gate application.
Open
- Connect a capacitor to CXN

- Connect a capacitor to CXP
- Connect a capacitor to CYN
- Connect a capacitor to CYP
- Connect a capacitor to CN
- Connect a capacitor to CP
- Connect a capacitor to C1N
- Connect a capacitor to C1P


- Connect a capacitor to VSS
Open
- Connect a capacitor to VSS
Open
A clock input pin for internal oscillator. Connect to VSS when using the
internal oscillator.
GND
Solomon Systech
REGVDD
VDDIO or VSS
VCORE
Stablilizing
capacitor
VREGC
VCORE
VRAM
Stablilizing
capacitor
VREGR
VRAM
VDDEXT
Power Supply
VDDIO
Power Supply
Logic
Control
Power for
Core Logic
Regulator
output for
logic
circuits
Power for
RAM
Regulator
output for
RAM
Power for
internal VDD
regulator
Power for
interface
logic pins
Input pin to enable internal vdd regulation.

- Connect to VDDIO if system Vdd > 1.95V or system Vdd < 1.65V,
internal Vdd regulator will be enabled
- Connect to VSS if system Vdd is 1.65V 1.95V. Internal vdd regulator
will be disabled.
Vdd for core use. Connect a capacitor for stabilization
Regulator output for VCORE use.
GND
Vdd for RAM use. Connect a capacitor for stabilization
Regulator output for RAM use.
Voltage input pin for internal logic, connect to system VDD.

Voltage input pin for logic I/O, connect to system VDD.

Table 6-2 - Interface Logic Pins

Name
Type
Connect
to
DEN
VSYNC
MPU
MPU
HSYNC
MPU
DOTCLK
MPU
SHUT
Function
VDDIO or
VSS
DC
Display
Timing
Signals
Logic
Control
MPU
MPU
E ( RD )
Logic
Control
I
R/ W
MPU
( WR )
D0-D17
IO
MPU
Data bus
WSYNC
MPU
Logic
Control
RES
MPU
System
Reset
CS
SCK
SDO
Solomon Systech
Display enable pin from controller. Data will be treated as dummy regardless the DEN
status during front/back porch setting at registers R16 and R17.
Frame synchronization signal.
- Fixed to VDDIO or VSS if not used
Line synchronization signal.
- Fixed to VDDIO or VSS if not used
Dot-clock signal and oscillator source. A non-stop external clock must be provided to
that pin even at front or black porch non-display period.
When using the RGB interface, it is a input pin put the driver into sleep mode. A sharp
falling edge must be provided to such pin when IC power on.
- Connect to VDDIO for sleep mode
- Connect to VSS for normal operating mode
This pin has no effect in system interface and should be connected to VDDIO / VSS
Data or command
6800-system : E (enable signal)
8080-system : /RD (read strobe signal)
Serial mode : Not used and should be connected to VDDIO or Vss
VDDIO
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
68-system : R/ W (indicates read cycle when High, write cycle when Low)
VDDIO or Vss
80-system : WR (write strobe signal)

Serial mode : Not used and should be connected to VDDIO or Vss
For parallel mode, 8/9/16/18 bit interface.
For generic mode, RGB interface.
Please refer to Section 15 Interface Mapping for definition.
Unused pins must be float or connect to VSS.
VSS
Ram Write Synchronization output
Open
System reset pin.

- Connect to VDDIO when not used
VDDIO
MPU
Chip select pin of serial interface.

- Leave it OPEN when not used
Open
MPU
Clock pin of serial interface.

Open
MPU
Data input pin in serial mode.

Open
MPU
Data output pin in serial mode.

Open
Serial
Interface
SDI
When not
in use
Description
Apr 2007 P 18/82
Rev 1.3
SSD1289
Table 6-3: Mode Selection Pins

Name
CM
Type
Connect
to
VDDIO or
VSS
RL
VDDIO or
VSS
GD
VDDIO or
VSS
TB
VDDIO or
VSS
I
BGR
VDDIO or
VSS
REV
VDDIO or
VSS
CAD
VDDIO or
VSS
PS0
VDDIO or
VSS
PS1
VDDIO or
VSS
PS2
VDDIO or
VSS
PS3
VDDIO or
VSS
GAMAS1
GAMAS2
SSD1289
Logic
Control
Panel
Mapping
Controls
Interface
Selection
GAMAS0
Function
VDDIO or
VSS
VDDIO or
VSS
VDDIO or
VSS
Rev 1.3
When using the RGB interface, it is a input pin to select 262k-color or 8-color display
mode. After entered 8-color display mode, the driver will switch to Frame-InversionMode, and only MSB of the data Red, Green and Blue will be considered.
- Connect to VDDIO for 8-color display mode
- Connect to VSS for 262k-color display mode
This pin has no effect in system interface and should be connected to VDDIO / Vss
Input pin to select the Source driver data shift direction.
- Connect to VDDIO for display first RGB data at S0-S2
- Connect to VSS for display first RGB data at S719-S717
Input pin to select the 1st output Gate
GD = 0, G0 is 1st output Gate, Gate sequence G0, G1, G2, G3, , G318, G319
GD = 1, G1 is 1st output Gate, Gate sequence G1, G0, G3, G2, , G319, G318
Input pin to select the Gate driver scan direction.
- Connect to VDDIO for Gate scan from G0 to G319
- Connect to VSS for Gate scan from G319 to G0
Input pin to select the color mapping.
- Connect to VDDIO for Blue-Green-Red mapping
- Connect to VSS for Red-Green-Blue mapping
(Refer to S0-S719 pin description on Page 19 for details)
Input pin to select the display reversion.
- Connect to VDDIO mapping data 0 to maximum pixel voltage for normal white panel
- Connect to VSS mapping data 0 to minimum pixel voltage for normal black panel
Panel structure selection pin.
- Connect to VDDIO if Cs on gate structure is used
- Connect to VSS if Cs on common structure is used
PS3
1
1
1
1
1
1
0
0
0
0
0
0
0
PS2
1
1
0
0
0
0
1
1
1
1
0
0
0
PS1
1
1
1
1
0
0
1
1
0
0
1
1
0
PS0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interface Mode
3-wire SPI
4-wire SPI
16-bit 6800 parallel interface
18-bits 6800 parallel interface
Reserved
Reserved
18-bit RGB interface + 4-wire SPI
Gamma selection pin. This pin should be connected to VDDIO / VSS

Logic
Control

P 19/82
When not
in use
Description
Apr 2007
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or Vss
VDDIO or
VSS
VDDIO or
VSS
VDDIO or
VSS
Solomon Systech
Table 6-4: Driver Output Pins

Name
VCOM
G0-G319
GTESTR
GTESTL
Type
S0-S719
Connect
to
LCD
LCD
LCD
LCD
Function
Description
A power supply for the TFT-display common electrode.

Gate driver output pins. These pins output VGH, VGL or VGOFFH level.
LCD
Driving
Signals
LCD
Gate driver output test pins, leave these pins no connection when using Cs on common
Source driver output pins.
S(3n) : display Red if BGR = LOW, Blue if BGR = HIGH.
S(3n+1) : display Green.
S(3n+2) : display Blue if BGR = LOW, Red if BGR = HIGH.
When not
in use
Open
Open
Open
Open
Open
Table 6-5: Miscellaneous Pins

Name
Type
NC
THROUGH1
THROUGH7
THROUGH2
THROUGH8
THROUGH3
THROUGH5
THROUGH4
THROUGH6
DUMMY
Connect
to
-
TESTA
TESTB
Function
FPC
IO
TESTC
Solomon Systech
FPC
FPC
IC
Testing
Signal
Description
These pins must be left open and cannot be connected together

Dummy pads. Used to measure the COG contact resistance.
These two pads are short circuited within the chip
Floating pins and no connection inside the IC. These pins should be open.
Test pin of the internal circuit.
- Leave this pin open and insert test point in FPC
Apr 2007 P 20/82
Rev 1.3
When not
in use
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
SSD1289
BLOCK FUNCTION DESCRIPTION
7.1
System Interface
The System Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-series
high speed parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral interface. The selection of
different interface is done by PS3, PS2, PS1 and PS0 pins. Please refer to the pin descriptions on page 19.
a)
MPU Parallel 6800-series Interface

The parallel Interface consists of 18 bi-directional data pins D[17:0], R / W , D/ C , E and CS . R / W input
high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register.
R / W input low indicates a write operation to Display Data RAM or Internal Command Registers depending
on the status of D/ C input. The E input serves as data latch signal (clock) when high provided that CS is low.
Please refer to Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the
operating frequency of the GDDRAM with that of the MCU, pipeline processing is internally performed which
requires the insertion of a dummy read before the first actual display data read. This is shown in the following
diagram.
R/W#(WR#)
E(RD#)
DATA BUS
write column address
dummy read
data read1
n+1
data read 2
n+2
data read 3
Figure 7-1 Read Display Data
b) MPU Parallel 8080-series Interface

The parallel interface consists of 18 bi-directional data pins D[17:0], RD , WR , D/ C and CS . RD input
serves as data read latch signal (clock) when low provided that CS is low. Whether reading the display data
from GDDRAM or reading the status from the status register is controlled by D/ C . WR input serves as data
write latch signal (clock) when low provided that CS is low. Whether writing the display data to the
GDDRAM or writing the command to the command register is controlled by D/ C . A dummy read is also
required before the first actual display data read for 8080-series interface. Please refer Figure 7-1.
c)
MPU 4-lines Serial Peripheral Interface

The 4-lines serial peripheral Interface consists of serial clock SCK, serial data SDI, D/ C and CS . SDI is
shifted into 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6 data bit 0.
D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the
Display Data RAM or command register at the same clock.
SSD1289
Rev 1.3
P 21/82
Apr 2007
Solomon Systech
d) MPU 3-lines Serial Peripheral Interface

The operation is similar to 4-lines serial peripheral interface while D/ C is not used. There are altogether 9-bits
will be shifted into the shift register on every ninth clock in sequence: D/ C bit, D7 to D0 bit. The D/C bit
(first bit of the sequential data) will determine the following data byte in the shift register is written to the
Display Data RAM ( D/ C bit = 1) or the command register ( D/ C bit = 0).
Data Read
Data Write
Command Read
Command Write
6800 series Parallel

Interface
18/16/9/8-bits
18/16/9/8-bits
Status only
Yes
8080 series Parallel

Interface
18/16/9/8-bits
18/16/9/8-bits
Status only
Yes
MCU Serial Interface

No
8-bits
No
8-bits
Table 7-1 - Data bus selection modes
7.2
RGB Interface
SSD1289 supports RGB interface and VSYNC interface as the moving display interace to display animation image.
RGB interface unit consists of D[17:0], HSYNC, VSYNC, DOTCLK and DEN signals for display moving pictures.
When the RGB interface is selcted, the display operation is synchronized with external control signals (HSYNC,
VSYNC and DOTCLK). In this operation, Data D[17:0,] will be treated as RR[5:0], GG[5:0] and BB[0:5], is written in
synchronization with the control signals when DEN is enabled for write operation in order to avoid flicker or tearring
effect while updating display data.
Table 7-2: RGB signal matching in data bus
Data Bus
D[17:12]
RGB signals
RR[5:0]
D[11:6]
GG[5:0]
D[5:0]
BB[0:5]
In VSYNC interface operation, the display operation is synchronized with the internal clock, which synchronizes the
display operation with the VSYNC signal. The display data is written to the GDDRAM through the system interface.
When writing data via VSYNC interface, the speed of writing data in the internal RAM is faster from the falling edge of
frame synchronous (VSYNC) than calculated minimum speed. The display may be updated even the data written in the
RAM is not completed. In this operation, some restrictions in setting the frequency and the method to write data to the
internal RAM are required.
7.3
Address Counter (AC)
The address counter (AC) assigns address to the GDDRAM. When an address set instruction is written into the IR, the
address information is sent from the IR to the AC.
After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading the data,
the AC is not updated. A window address function allows for data to be written only to a window area specified by
GRAM.
7.4
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 240 RGB x
320 x 18 / 8 = 172,800 bytes. For mechanical flexibility, re-mapping on both Segment and Common outputs can be
selected by software. Please refer to the command Data Output/Scan direction for detail description.
Four pages of display data forms a RAM address block and stored in the GDDRAM. Each block will form the
fundamental units of scrolling addresses. Various types of area scrolling can be performed by software program
according to the command Set area Scroll and Set Scroll Start.
Solomon Systech
Apr 2007 P 22/82
Rev 1.3
SSD1289
7.5
Gamma/Grayscale Voltage Generator
The grayscale voltage circuit generates a LCD driver circuit that corresponds to the grayscale levels as specified in the
grayscale gamma adjustment resister. 262,144 possible colors can be displayed when 1 pixel = 18 bit. For details, see the
gamma adjustment register.
7.6
Booster and Regulator Circuit
These two functional blocks generate the voltage of VGH, VGL, VCOM levels and VLCD0~63 which are necessary for
operating a TFT LCD.
7.7
Timing Generator
The timing generator generates a timing signal for the operation of internal circuit such as the internal RAM accessing,
date output timing etc.
7.8
Oscillation Circuit (OSC)
This module is an on-chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC voltage
converter. This clock is also used in the display timing generator.
7.9
Data Latches
This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to
the HV Buffer Cell and Level Selector to output the required voltage level.
7.10 Liquid Crystal Driver Circuit

SSD1289 consists of a 720-output source driver (S0-S719) and a 320-output gate driver (G0-G319). The display image
data is latched when 720 bits of data are inputted. The latched data control the source driver and output drive waveforms.
The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output
from the source driver can be changed by setting the RL bit and the shift direction of gate output from the gate driver can
be changed by setting the TB bit. The scan mode by the gate driver can be changed by setting the SM bit. Sets the gate
driver pin arrangement in combination with the TB bit to select the operimal scan mode for the module.
SSD1289
Rev 1.3
P 23/82
Apr 2007
Solomon Systech
COMMAND TABLE
Table 8-1 - Command Table
Reg#
R
SR
R00h
R01h
Register
Index
Status Read
Oscillation Start
R/W D/C IB15 IB14 IB13 IB12 IB11 IB10

0
1
0
0
0
1
(0000h)
Driver output
control
[0XXX][X0X1]3F
R02h
LCD drive AC
control
R03h
R05h
Compare register
(2)
R0Bh
R0Ch
Display control
IB3
IB2
IB1
IB0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
L7
L6
L5
L4
L3
L2
L1
L0
0
OSCE
N
RL
REV
CAD
BGR
SM
TB
MUX8
MUX7
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
FLD
ENWS
B/C
EOR
WSMD
NW7
NW6
NW5
NW4
NW3
NW2
NW1
NW0
DCT3
DCT2
DCT1
DCT0
BT2
BT1
BT0
DC3
DC2
DC1
DC0
AP2
AP1
AP0
CPR5
CPR4
CPR3
CPR2
CPR1
CPR0
CPG5
CPG4
CPG3
CPG2
CPG1
CPG0
(5308h)
Power control (2)
IB4
(0000h)
Frame cycle control
IB5
(0000h)
R07h
IB6
(0000h)
R06h
IB7
All GAMAS[2:0] setting

8 color (6A64h)
Compare register
(1)
IB8
(0000h)
Power control (1)
IB9
(0004h)
CPB5
CPB4
CPB3
CPB2
CPB1
CPB0
0
D0
PT1
PT0
VLE2
VLE1
SPT
GON
DTE
CM
D1
NO1
NO0
SDT1
SDT0
EQ2
EQ1
EQ0
DIV1
DIV0
SDIV
SRTN
RTN3
RTN2
RTN1
RTN0
VRC2
VRC1
VRC0
VRH3
VRH2
VRH1
VRH0
VCOMG
VDV4
VDV3
VDV2
VDV1
VDV0
0
SCN0
R0Dh
Power control (3)
R0Eh
Power control (4)
R0Fh
Gate scan start

position
(0000h)
R10h
R11h
R12h
R15h
Sleep mode
R17h
SCN8
SCN7
SCN6
SCN5
SCN4
SCN3
SCN2
SCN1
SLP
VS mode
DFM1
DFM0
TRANS
OEDef
(6830h)
TY1
TY0
ID1
ID0
AM
LG2
LG1
LG0
WMode DMode1 DMode0
Optimize Access
Speed 3
(6CEBh)
Generic Interface
Contrl
XL7
XL6
XL5
XL4
XL3
XL2
XL1
XL0
HBP7
HBP6
HBP5
HBP4
HBP3
HBP2
HBP1
HBP0
VFP7
VFP6
VFP5
VFP4
VFP3
VFP2
VFP1
VFP0
VBP7
VBP6
VBP5
VBP4
VBP3
VBP2
VBP1
VBP0
(00D0h)
R16h
(0001h)
Entry mode
Horizontal Porch
(EF1Ch)
Vertical Porch
(0103h)
Solomon Systech
Apr 2007 P 24/82
INVDOT INVDEN INNVHS INVVS
Rev 1.3
SSD1289
(continued)
Reg#
R1Eh
R22h
R23h
Register
R/W D/C IB15 IB14 IB13 IB12 IB11 IB10
R28h
R28h
R29h
R2Fh
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
R41h
R49h
R4Ah
R4Eh
VCM0
WMG3
WMG2
WMG1
WMG0
WMR3
WMR2
WMR1
WMR0
WMG5
WMG4
RAM write data

mask (2)
0
0
Frame Frequency
1
1
(8000h)
Data[17:0] mapping depends on the interface setting
WMB5
WMB4
WMB3
WMB2
WMB1
WMB0
OSC3
OSC2
OSC1
OSC0
VCOM OTP
(000Ah)
Optimize Access
Speed 1
(0006h)
VCOM OTP
(80C0h)
Optimize Access
Speed 2
(12BEh)
control (1)
1
1
1
1
1
1
1
1
1
1
PKP12
PKP11
PKP10
PKP02
PKP01
PKP00
PKP32
PKP31
PKP30
PKP22
PKP21
PKP20
PKP52
PKP51
PKP50
PKP42
PKP41
PKP40
PRP12
PRP11
PRP10
PRP02
PRP01
PRP00
PKN12
PKN11
PKN10
PKN02
PKN01
PKN00
PKN32
PKN31
PKN30
PKN22
PKN21
PKN20
PKN52
PKN51
PKN50
PKN42
PKN41
PKN40
PRN12
PRN11
PRN10
PRN02
PRN01
PRN00
VRP14
VRP13
VRP12
VRP11
VRP10
VRP03
VRP02
VRP01
VRP00
control (10)
0
0
0
0
0
0
0
0
0
0
VRN14
VRN13
VRN12
VRN11
VRN10
VRN03
VRN02
VRN01
VRN00
Vertical scroll
control (1)
VL10
control (2)
control (3)
control (4)
control (5)
control (6)
control (7)
control (8)
control (9)
Vertical scroll
control (2)
Horizontal RAM
address position
Vertical RAM
address start
position
First window start
Second window end
Set GDDRAM Y
address counter
VL18
VL17
VL16
VL15
VL14
VL13
VL12
VL11
VL28
VL27
VL26
VL25
VL24
VL23
VL22
VL21
VL20
HEA6
HEA5
HEA4
HEA3
HEA2
HEA1
HEA0
HSA7
HSA6
HSA5
HSA4
HSA3
HSA2
HSA1
HSA0
VSA8
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
VEA8
VEA7
VEA6
VEA5
VEA4
VEA3
VEA2
VEA1
VEA0
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
SS28
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
SE28
SE27
SE26
SE25
SE24
SE23
SE22
SE21
SE20
XAD7
XAD6
XAD5
XAD4
XAD3
XAD2
XAD1
XAD0
YAD8
YAD7
YAD6
YAD5
YAD4
YAD3
YAD2
YAD1
YAD0
(013Fh)
Set GDDRAM X
address counter
HEA7
(013Fh)
Second window
start
(0000h)
First window end
Vertical RAM
address end
position
0
0
(0000h)
Note:
IB0
VCM1
WMR4
(0000h)
R4Fh
IB1
VCM2
(0000h)
R4Bh
IB2
VCM3
WMR5
(013Fh)
R48h
IB3
VCM4
(0000h)
R46h
IB4
VCM5
(EF00h)
R45h
IB5
RAM write data

mask (1)
(0000h)
R44h
IB6
nOTP
RAM data read
RAM data write
(0000h)
R42h
IB7
(0000h)
R25h
IB8
1
1
1
(0000h)
R24h
IB9
0
0
1
Power control (5)
In R01h, bits REV, CAD, BGR, TB, RL, CM will override the corresponding hardware pins settings.
Setting R28h as 0x0006 is required before setting R25h and R29h registers.
SSD1289
Rev 1.3
P 25/82
Apr 2007
Solomon Systech
Table 8-2 Gamma Registers POR value

Command
R30h-R3Bh
PKP0
PKP1
PKP2
PKP3
PKP4
PKP5
PRP0
PRP1
VRP0
VRP1
PKN0
PKN1
PKN2
PKN3
PKN4
PKN5
PRN0
PRN1
VRN0
VRN1
GAMAS[2:0]
000, 100
000
000
111
111
110
100
000
000
0100
00100
011
001
000
000
111
111
000
000
0110
00000
GAMAS[2:0]
001, 101
000
000
101
100
101
010
000
010
1101
10110
101
010
010
001
101
110
010
000
1010
00111
GAMAS[2:0]
010, 110
000
000
111
111
110
100
000
000
0100
00100
011
001
000
000
111
111
000
000
0110
00000
GAMAS[2:0]
011, 111
000
000
111
111
110
100
000
000
0000
11110
011
001
000
000
111
111
000
000
1111
00000
Table 8-3: Registers POR value at GAMAS[2:0] = 000,100

Reg#
Register
R03h
R0Dh
R0Eh
R1Eh
Power control (1)

Power control (3)
Power control (4)
Power control (5)
Hex
IB15 IB14 IB13 IB12 IB11 IB10 IB9
code
6664
0009
3200
0029
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
IB8
IB7
IB6
IB5
IB4
IB3
IB2
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
IB8
IB7
IB6
IB5
IB4
IB3
IB2
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
0
IB1 IB0
0
0
0
0
0
1
0
1

Reg#
Register
R03h
R0Dh
R0Eh
R1Eh
Power control (1)

Power control (3)
Power control (4)
Power control (5)
Hex
code
6A64
000A
2C00
0034
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
IB1 IB0
0
1
0
0
0
0
0
0

Reg#
Register
R03h
R0Dh
R0Eh
R1Eh
Power control (1)

Power control (3)
Power control (4)
Power control (5)
Hex
code
6264
0009
3200
002F
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
IB1 IB0
0
0
0
1
0
1
0
1

Reg#
Register
R03h
R0Dh
R0Eh
R1Eh
Power control (1)

Power control (3)
Power control (4)
Power control (5)
Solomon Systech
Hex
code
6464
000A
3000
0031
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
Apr 2007 P 26/82
Rev 1.3
IB1 IB0
0
1
0
0
0
0
0
1
SSD1289
COMMAND DESCRIPTION
Index (IR)
R/W
W
DC
0
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
ID7
IB6
ID6
IB5
ID5
IB4
ID4
IB3
ID3
IB2
ID2
IB1
ID1
IB0
ID0
The index instruction specifies the RAM control indexes (R00h to RFFh). It sets the register number in the range of
00000000 to 11111111 in binary form. But do not access to Index register and instruction bits which do not have its
own index register.
Device Code Read (R00h)

R/W
R
DC
1
IB15
1
IB14
0
IB13
0
IB12
0
IB11
1
IB10
0
IB9
0
IB8
1
IB7
1
IB6
0
IB5
0
IB4
0
IB3
1
IB2
0
IB1
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
1
If this register is read forcibly, 8989h is read.
Oscillator (R00h) (POR = 0000h)

R/W
DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB0
OSCEN
0
OSCEN: The oscillator will be turned on when OSCEN = 1, off when OSCEN = 0.
Driver Output Control (R01h) (POR = [0XXXX0X1]3Fh)

R/W
DC
W
1
POR
IB15
0
0
IB14
RL
X
IB13
REV
X
IB12
CAD
X
IB11
BGR
X
IB10
SM
0
IB9
TB
X
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
1
0
0
1
1
1
1
1
1
Note: The POR value of REV, CAD, BGR, TB and RL are determined by the corresponding hardware pin state. The
software bit setting will override hardware setting if this command is sent.
REV: Displays all character and graphics display sections with reversal when REV = 1. Since the grayscale level can
be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is
indicated below.
REV
0
1
RGB data
00000H
:
3FFFFH
00000H
:
3FFFFH
Source Output level

Vcom = L
V63
:
V0
V0
:
V63
Vcom = H
V0
:
V63
V63
:
V0
CAD: Set up based on retention capacitor configuration of the TFT panel.

CAD
0
1
Retention capacitor configuration

Cs on Common
Cs on Gate
BGR: Selects the order from RGB to BGR in writing 18-bit pixel data in the GDDRAM.
When BGR = 0 <R><G> color is assigned from S0.
When BGR = 1 <G><R> color is assigned from S0.
SSD1289
Rev 1.3
P 27/82
Apr 2007
Solomon Systech
SM: Change scanning order of gate driver.

SM
0
1
Gate scan squence (GD=0)

G0, G1, G2, G3G219 (left and right gate interlaced)
G0, G2, G318, G1, G3, G319
See Scan mode setting on next page.

TB: Selects the output shift direction of the gate driver.
When TB = 1, G0 shifts to G319.
When TB = 0, G319 shifts to G0.
RL: Selects the output shift direction of the source driver.
When RL = 1, S0 shifts to S719 and <R><G> color is assigned from S0.
When RL = 0, S719 shifts to S0 and <R><G> color is assigned from S719.
Set RL bit and BGR bit when changing the dot order of R, G and B. RL setting will be ignored when display with RAM
(Dmode[1:0] = 00).
MUX[8:0]: Specify number of lines for the LCD driver. MUX[8:0] settings cannot exceed 319.
Remark: When using the partial display, the output for non-display area will be minimum voltage.
Solomon Systech
Apr 2007 P 28/82
Rev 1.3
SSD1289
GD=1, G1 is the 1st gate output channel, gate output sequence is G1, G0, G3, G2, , G319, G318.
SM = 0
SM = 1
G1
G3
G5
G0
G2
G4
G1
G3
G317
G319
TB = 1
RL = 1
G0
G2
G317
G319
G316
G318
G316
G318
S0
S0
S719
G0
G2
G4
G1
G3
G5
S719
G1
G3
G317
G319
G0
G2
TB = 0
RL = 1
G316
G318
G316
G318
G317
G319
S0
S0
S719
G0
G2
G4
G1
G3
G5
S719
G1
G3
G317
G319
TB = 1
RL = 0
G0
G2
G316
G318
G316
G318
G317
G319
S0
S0
S719
G0
G2
G4
G1
G3
G5
S719
G1
G3
G317
G319
G0
G2
TB = 0
RL = 0
S0
SSD1289
Rev 1.3
G316
G318
G316
G318
G317
G319
P 29/82
S719
Apr 2007
S0
S719
Solomon Systech
GD=0, G0 is the 1st gate output channel, gate output sequence is G0, G1, G2, G3, , G318, G319.
SM = 0
SM = 1
G0
G2
G4
G1
G3
G5
G0
G2
G316
G318
TB = 1
RL = 1
G1
G3
G316
G318
G317
G319
S0
G317
G319
S0
S719
S719
G0
G2
G0
G2
G4
G1
G3
G5
G316
G318
G1
G3
TB = 0
RL = 1
G316
G318
G317
G319
S0
G317
G319
S719
S0
S719
G0
G2
G0
G2
G4
G1
G3
G5
G316
G318
TB = 1
RL = 0
G1
G3
G316
G318
G317
G319
S0
G317
G319
S0
S719
S719
G0
G2
G4
G1
G3
G5
G0
G2
G316
G318
G1
G3
TB = 0
RL = 0
G316
G318
G317
G319
S0
Solomon Systech
S719
G317
G319
S0
S719
Apr 2007 P 30/82
Rev 1.3
SSD1289
LCD-Driving-Waveform Control (R02h) (POR = 0000h)

R/W
DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12 IB11 IB10

FLD ENWS B/C
0
0
0
IB9
IB8
IB7
EOR WSMD NW7
0
0
0
IB6
NW6
0
IB5
NW5
0
IB4
NW4
0
IB3
NW3
0
IB2
NW2
0
IB1
NW1
0
IB0
NW0
0
FLD: Set display in interlace drive mode to protect from flicker. It splits one frame into 3 fields and drive.
When FLD = 1, it is 3 field driving, which also limit VBP = 1 and cannot be used for Cs on gate panel type.
That is CAD = 1 & FLD =1 cannot be coexist.
When FLD = 0, it is normal driving.
The following figure shows the gate selection when the 3-field invension is enabled and the output waveform of the 3field interlaced driving.
Table 9-1: 3-field interlace driving
TB = 1
Gate
G0
G1
G2
G3
G4
FLD = 0
X
X
X
X
X
X
X
X
X
X
X
G317
G318
G319
FLD = 1
X
TB = 0
Gate
G319
G318
G317
G316
G315
G2
G1
G0
FLD = 0
X
X
X
X
X
X
X
x
X
X
X
FLD = 1
X
X
Figure 9-1: gate output timing in 3-field interlacing driving

1 frame
Field 1
Blank period
Field 2
Field 3
Field 1
AC Polarity
G0
G1
G2
G3
G4
G5
G3n +1
G3n +2
G3n +3
SSD1289
Rev 1.3
P 31/82
Apr 2007
Solomon Systech
B/C: Select the liquid crystal drive waveform VCOM.

When B/C = 0, frame inversion of the LCD driving signal is enabled.
When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[7:0]+1.
EOR: When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for
alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven
and the N-lines.
NW[7:0]: Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). N-line is equal to
NW[7:0]+1.
Figure 9-2: Line Inversion AC Driver
N Frame
Back porch
1
N+1 Frame
Front porch
322
335
336
Back porch
1
Front porch
3
322
335
336
Frame Inversion
320 line drive
N Frame
Back porch
1
N+1 Frame
Front porch
322
335
336
Back porch
1
Front porch
3
322
335
336
Line Inversion
320 line drive
Solomon Systech
Apr 2007 P 32/82
Rev 1.3
SSD1289
ENWS: When ENWS = 1, it enables WSYNC output pin. Mode1 or Mode2 is selected by WSMD. When ENWS =
0(POR), it disables WSYNC feature, the WSYNC output pin will be high-impedance.
WSYNC
/CS
D/C
MPU
/WR
SSD1289
D[17:0]
16
WSMD = 0 is mode1, the waveform of WSYNC output will be:
tn
tu
WSYNC
100%
Memory
Access
0%
Fast write MCU

Slow write MCU
SSD1289 displaying memory
tn is the time when there is No Update of LCD screen from on-chip ram content.
tu is the time when the LCD screen is updating based on on-chip ram content.
e.g. fosc = 510KHz, for 320mux, tn = 282us (6 lines), tu =15.06ms (320 lines)
WSMD = 1 is mode2, the waveform of WSYNC output will be:
WSYNC
0
m-1
mux line read
For fast write MCU: MCU should start to write new frame of ram data just after rising edge of long WSYNC pulse and
should be finished well before the rising edge of the next long WSYNC pulse.
e.g. 5MHz 8 bit parallel write cycle for 18 bit color depth, or 3MHz 8 bit parallel write cycle for 16 bit color depth.
For slow write MCU (Half the write speed of fast write): MCU should start to write new frame ram data after the rising
edge of the first short WSYNC pulse and must be finished within 2 frames time.
e.g. 2.5MHz 8 bit parallel write cycle for 18 bit color depth.
* Usually, mode2 is for slower MCU, while mode1 is for fast MCU.
SSD1289
Rev 1.3
P 33/82
Apr 2007
Solomon Systech
Power control 1 (R03h) (POR = 6664h)

R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11

DCT3 DCT2 DCT1 DCT0 BT2
0
1
1
0
0
IB10
BT1
1
IB9
BT0
1
IB8
0
0
IB7
DC3
0
IB6
DC2
1
IB5
DC1
1
IB4
DC0
0
IB3
AP2
0
IB2
AP1
1
IB1
AP0
0
IB0
0
0
*note: this POR value is for GAMAS[2:0] = 000, for POR values of all GAMAS[2:0] setting please refer to Table 5.
DCT[3:0]: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
DCT3 DCT2 DCT1 DCT0
Step-up cycle
0
0
0
0
Fline 24
0
0
0
1
Fline 16
0
0
1
0
Fline 12
0
0
1
1
Fline 8
0
1
0
0
Fline 6
0
1
0
1
Fline 5
0
1
1
0
Fline 4
0
1
1
1
Fline 3
1
0
0
0
Fline 2
1
0
0
1
Fline 1
1
0
1
0
fosc / 4
1
0
1
1
fosc / 6
1
1
0
0
fosc / 8
1
1
0
1
fosc / 10
1
1
1
0
fosc / 12
1
1
1
1
fosc / 16
* Fline = Line frequency
fosc = Internal oscillator frequency (~510KHz)
BT[2:0]: Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply
voltage to be used.
BT2
0
0
0
0
1
1
1
1
BT1
0
0
1
1
0
0
1
1
Solomon Systech
BT0
0
1
0
1
0
1
0
1
VGH output
VCIX2 +4 x VCI
VCIX2 +4 x VCI
VCIX2 +4 x VCI
VCI x 5
VCI x 5
VCI x 5
VCI x 4
VCI x 4
VGL output
-(VCIX2 x 3) + VCI
-(VGH) + VCix2
-(VGH)
-(VGH)
-(VGH) + VCI
-(VGH) + VCix2
-(VGH)
-(VGH) + VCI
VGH booster ratio

+6
+6
+6
+5
+5
+5
+4
+4
VGL booster ratio

-5
-4
-6
-5
-4
-3
-4
-3
Apr 2007 P 34/82
Rev 1.3
SSD1289
DC[3:0]: Set the step-up cycle of the step-up circuit for 262k-color mode (CM = VSS). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
DC3 DC2 DC1 DC0

Step-up cycle
0
0
0
0
Fline 24
0
0
0
1
Fline 16
0
0
1
0
Fline 12
0
0
1
1
Fline 8
0
1
0
0
Fline 6
0
1
0
1
Fline 5
0
1
1
0
Fline 4
0
1
1
1
Fline 3
1
0
0
0
Fline 2
1
0
0
1
Fline 1
1
0
1
0
fosc / 4
1
0
1
1
fosc / 6
1
1
0
0
fosc / 8
1
1
0
1
fosc / 10
1
1
1
0
fosc / 12
1
1
1
1
fosc / 16
* Fline = Line frequency
fosc = Internal oscillator frequency (~510KHz)
AP[2:0]: Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When
the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current
taking into account the power consumption. During times when there is no display, such as when the system is in a sleep
mode.
AP2
0
0
0
0
1
1
1
1
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Op-amp power
Least
Small
Small to medium
Medium
Medium to large
Large
Large to Maximum
Maximum
Compare register (R05h-R06h) (POR = 0000h)

Reg# R/W DC
W
1
R05h
POR
W
1
R06h
POR
IB15 IB14 IB13 IB12 IB11 IB10

CPR5 CPR4 CPR3 CPR2 CPR1 CPR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IB9
0
0
0
0
IB8
0
0
0
0
IB7
IB6
IB5
IB4
IB3
IB2
CPG5 CPG4 CPG3 CPG2 CPG1 CPG0
0
0
0
0
0
0
CPB5 CPB4 CPB3 CPB2 CPB1 CPB0
0
0
0
0
0
0
IB1
0
0
0
0
IB0
0
0
0
0
CPR[5:0], CPG[5:0], CPB[5:0]: Set the value for the compare register, of which the data read out from the GDDRAM
or data written to the GDDRAM by the microcomputer are compared. This function is not available in the external
display interface mode. In the external display mode, make sure LG[2:0] = 000. CPR[5:0] compares the pins RR[5:0],
CPG[5:0] compares the pins GG[5:0], and CPB[5:0] compares the pins BB[5:0]. Refer to Section 14 Interface Mapping
for writing methods in RGB data.
SSD1289
Rev 1.3
P 35/82
Apr 2007
Solomon Systech
Display Control (R07h) (POR = 0000h)

R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
PT1
0
IB11
PT0
0
IB10
VLE2
0
IB9
IB8
VLE1 SPT
0
0
IB7
0
0
IB6
0
0
IB5
IB4
GON DTE
0
0
IB3
CM
0
IB2
0
0
IB1
D1
0
IB0
D0
0
PT[1:0]: Normalize the source outputs when non-displayed area of the partial display is driven.
VLE[2:1]: When VLE1 = 1 or VLE2 = 1, a vertical scroll is performed in the 1st screen by taking data VL17-0 in R41h
register. When VLE1 = 1 and VLE2 = 1, a vertical scroll is performed in the 1st and 2nd screen by VL1[8:0] and VL2[8:0]
respectively.
SPT: When SPT = 1, the 2-division LCD drive is performed.
CM: 8-color mode setting.
When CM = 1, 8-color mode is selected.
When CM = 0, 8-color mode is disable.
GON: Gate off level becomes VGH when GON = 0.
DTE: When GON = 1 and DTE = 0, all gate outputs become VGL. When GON = 1 and DTE = 1, selected gate
wire becomes VGH, and non-selected gate wires become VGL.
D[1:0]: Display is on when D1 = 1 and off when D1 = 0. When off, the display data remains in the GDDRAM, and
can be displayed instantly by setting D1 = 1. When D1= 0, the display is off with all of the source outputs set to the
GND level. Because of this, the driver can control the charging current for the LCD with AC driving. When D[1:0] =
01, the internal display is performed although the display is off. When D[1:0] = 00, the internal display operation
halts and the display is off. Control the display on/off while control GON and DTE.
GON
DTE
D1
D0
0
0
1
0
0
0
0
0
0
0
1
1
Internal
Display
Operation
Halt
Operation
Operation
Operation
Operation
Source output
Gate output
GND
GND
GND
Grayscale level
output
VGH
VGH
VGOFFL
VGOFFL
Selected gate line: VGH
Non-selected gate line:
VGOFFL
Grayscale level
output
Frame Cycle Control (R0Bh) (POR = 5308h)

R/W
DC
W
1
POR
IB15
NO1
0
IB14 IB13 IB12 IB11

NO0 SDT1 SDT0
0
1
0
1
0
IB10
EQ2
0
IB9
EQ1
1
IB8
EQ0
1
IB7
DIV1
0
IB6
IB5
IB4
IB3
IB2
IB1
IB0
DIV0 SDIV SRTN RTN3 RTN2 RTN1 RTN0
0
0
0
1
0
0
0
NO[1:0]: Sets amount of non-overlap of the gate output.

NO1
0
0
1
1
NO0
0
1
0
1
1 Line period
Amount of non-overlap
reserved
1 clock cycle (POR)
2 clock cycle
3 clock cycle
1 Line period
Gn
Gn+1
Solomon Systech
Non-overlap period
Apr 2007 P 36/82
Rev 1.3
SSD1289
SDT[1:0]: Set delay amount from the gate output signal falling edge of the source outputs.
SDT1
0
0
1
1
SDT0
0
1
0
1
Delay amount of the source output

0 clock cycle
1 clock cycle (POR)
2 clock cycle
3 clock cycle
EQ[2:0]: Sets the equalizing period.

EQ2
0
0
0
0
1
1
1
1
EQ1
0
0
1
1
0
0
1
1
EQ0
0
1
0
1
0
1
0
1
1 Line period
EQ period
No EQ
2 clock cycle
3 clock cycle
4 clock cycle
5 clock cycle
6 clock cycle
7 clock cycle
8 clock cycle
1 Line period
Gn
Sn
EQ
Delay amount of
the source output
Equalizing
period
DIV[1:0]: Set the division ratio of clocks for internal operation. Internal operations are driven by clocks which
frequency is divided according to the DIV1-0 setting.
DIV1
0
0
1
1
DIV0
0
1
0
1
Division Ratio
1
2
4
8
* fosc = internal oscillator frequency, ~510kHz

SDIV: When SDIV = 1, DIV1-0 value will be count. When SDIV = 0, DIV1-0 value will be auto determined.
SRTN: When SRTN =1, RTN3-0 value will be count. When SRTN = 0, RTN3-0 value will be auto determined.
RTN[3:0]: Set the no. of clocks in each line. The total number will be the decimal value of RTN3-0 plus 16. e.g. if
RTN3-0 = 1010h, the total number of clocks in each line = 10 +16 = 26 clocks.
SSD1289
Rev 1.3
P 37/82
Apr 2007
Solomon Systech
Frame frequency calculation

For DMode[1:0] = 00
Frame _ frequency =
where
Fosc
div (rtn + 16) (mux + vbp + vfp + 3)
Fosc = internal oscillator frequency

div = Division ratio determined by DIV[1:0]
rtn = RTN[3:0]
mux = MUX[8:0]
vbp = VBP[7:0]
vfp = VFT[7:0]
for default values of SSD1289

Fosc = ~510KHz, DIV[1:0] = 00, RTN[3:0] = 8, MUX[8:0] = 319, VBP[7:0] = 3, VFP[7:0] = 1,
Frame frequency =
510 K
510 K
=
= 65 Hz
1 (8 + 16) (319 + 3 + 1 + 3) 1 24 326
Power Control 2 (R0Ch) (POR = 0004h)

R/W DC
W
1
POR
IB15 IB14
0
0
0
0
IB13
0
0
IB12 IB11
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
IB1
IB0
VRC2 VRC1 VRC0
1
0
0
VRC[2:0]: Adjust VCIX2 output voltage. The adjusted level is indicated in the chart below VRC2-0 setting.
VRC2 VRC1 VRC0
VCIX2 voltage
0
0
0
5.1V
0
0
1
5.2V
0
1
0
5.3V
0
1
1
5.4V
1
0
0
5.5V
1
0
1
5.6V
1
1
0
5.7V
1
1
1
5.8V
Note: The above setting is valid when VCI has high enough voltage supply for boosting up the required voltage.
The above setting is assumed 100% booster efficiency. Please refer to DC Characteristics for detail.
Solomon Systech
Apr 2007 P 38/82
Rev 1.3
SSD1289
Power Control 3 (R0Dh) (POR = 0009h)

R/W DC
W
1
POR*
IB15 IB14
0
0
0
0
IB13
0
0
IB12 IB11
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
IB2
IB1
IB0
VRH3 VRH2 VRH1 VRH0
1
0
0
1
VRH[3:0]: Set amplitude magnification of VLCD63. These bits amplify the VLCD63 voltage 1.54 to 2.725 times the Vref
voltage set by VRH[3:0].
VRH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VRH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VRH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VRH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VLCD63 Voltage
Vref x 1.540
Vref x 1.620
Vref x 1.700
Vref x 1.780
Vref x 1.850
Vref x 1.930
Vref x 2.020
Vref x 2.090
Vref x 2.165
Vref x 2.245
Vref x 2.335
Vref x 2.400
Vref x 2.500
Vref x 2.570
Vref x 2.645
Vref x 2.725
*Vref is the internal reference voltage equals to 2.0V.

Power Control 4 (R0Eh) (POR = 3200h)
R/W DC
W
1
POR*

IB9
IB8
0
0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0
0
0
1
1
0
0
1
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
0
0
VcomG: When VcomG = 1, it is possible to set output voltage of VcomL to any level, and the instruction (VDV4-0)
becomes available. When VcomG = 0, VcomL output is fixed to Hi-z level, VCIM output for VcomL power supply
stops, and the instruction (VDV4-0) becomes unavailable. Set VcomG according to the sequence of power supply setting
flow as it relates with power supply operating sequence.
VDV[4:0]: Set the alternating amplitudes of Vcom at the Vcom alternating drive. These bits amplify 0.6 to 1.23 times
the VLCD63 voltage. When VcomG = 0, the settings become invalid. External voltage at VcomR is referenced when
VDH = 01111.
VCOML = 0.9475*VCOMH - VCOMA
VDV4
0
0
0
VDV3
0
0
0
VDV1
0
0
1
VDV0
0
1
0
1
1
VDV2
0
0
0
:
:
:
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
:
:
:
1
1
1
0
1
1
1
0
1
Vcom Amplitude
VLCD63 x 0.60
VLCD63 x 0.63
VLCD63 x 0.66
:
Step = 0.03
:
VLCD63 x 0.99
VLCD63 x 1.02
Reference from
external variable
resistor
VLCD63 x 1.05
VLCD63 x 1.08
:
Step = 0.03
:
VLCD63 x 1.20
VLCD63 x 1.23
Reserved
Reserved
Note: Vcom amplitude < 5.5V
SSD1289
Rev 1.3
P 39/82
Apr 2007
Solomon Systech
Gate Scan Position (R0Fh) (POR = 0000h)

R/W DC
W
1
POR

0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0
0
0
0
0
0
0
0
0
0
SCN[8:0]: Set the scanning starting position of the gate driver. The valid range is from 0 to 319.
1st line of
data
G0
G0
1st line of
data
G29
SCN8-0
= 000000000
SCN8-0
= 000011101
G319
G319
Sleep mode (R10h) (POR = 0001h)

R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
SLP
1
SLP: Sleep mode enable bit. In the sleep mode, the internal display operations are halted except the R-C oscillator to
reduce current consumption. No change in the GDDRAM data or instructions during the sleep mode is made, although it
is retained.
When SLP = 1, the driver enters into the sleep mode.
When SLP = 0, the driver leaves the sleep mode.
Entry Mode (R11h) (POR = 6830h)

R/W DC
IB15
IB14 IB13 IB12
IB11
IB10
IB9
IB8
W
1 VSMode DFM1 DFM0 TRANS OEDef WMode DMode1 DMode0
POR
0
1
1
0
1
0
0
0
IB7
TY1
0
IB6
TY0
0
IB5
ID1
1
IB4
ID0
1
IB3
AM
0
IB2 IB1 IB0

LG2 LG1 LG0
0
0
0
VSMode: When VSMode = 1 at DMode[1:0] = 00, the frame frequency will be dependent on VSYNC.
VSYNC
/CS
D/C
MPU
/WR
SSD1289
D[17:0]
16
In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to
the internal RAM at faster than the calculated minimum speed (internal display oerpation speed + buffer), it becomes
possible to rewrite the moving picture data without flickering the display and display a moving picture via system
interface.
The display operation is performed in synchronization with the internal clock signal generated from the internal
oscillator and the VSYNC signal. The display data is written in the internal RAM so that the SSD1289 rewrites the data
only within the moving picture area and minimize the number of data transfer required for moving picture display.
Therefore, the SSD1289 can write data via VSYNC interface in high speed with low power consumption.
Solomon Systech
Apr 2007 P 40/82
Rev 1.3
SSD1289
VSYNC
RAM data
write via
system I/F
The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more
than the values calculated from the following formulas, respectively.
Fosc [ Hz ] = Frame _ frequency * ( mux + vfp + vbp + 3 ) * ( rtn + 16 ) * ( div )
240 * mux
RAMWriteSpeed (min)[ Hz ] >
1
( vbp + mux m arg ins ) * ( rtn + 16 ) *
fosc
where
Fosc = internal oscillator frequency

div = Division ratio determined by DIV[1:0]
rtn = RTN[3:0]
mux = MUX[8:0]
vbp = VBP[7:0]
vfp = VFT[7:0]
Note: When RAM write operation is not started right after the falling edge of VSYNC, the time from the falling edge of
VSYNC until the start of RAM write operation must also be taken into account.
DFM[1:0]: Set the color display mode.
DFM1
1
1
DFM0
1
0
Color mode
65k color (POR)
262k color
TRANS: When TRANS = 1, transparent display is allowed during DMode[1:0] = 1x.

OEDef:
When OEDef = 1, OE defines the display window.
When OEDef = 0, the display window is defined by R4Eh and R4Fh.
WMode: Select the source of data to write in the RAM.
WMode
0
1
Write RAM from

Normal data bus (POR)
Generic interface
DMode[1:0]: SSD1289 allows data display from RAM data or from generic input data. When DMode[1:0] = 00, it
displays the ram content. When DMode[1:0] = 01, it displays from generic input data.
DMode1
0
0
1
1
SSD1289
DMode0
0
1
0
1
Display
Ram (POR)
Generic input
RAM and Generic data
RAM and Generic data
Rev 1.3
P 41/82
Remark
Frame frequency depends on Fosc (POR)
Frame frequency depends on VSYNC, default DMode setting in RGB interface
In this case, generic data is shown in the display window
In this case, RAM data is shown in the display window
Apr 2007
Solomon Systech
Picture In Picture Function
PS[3:0] = 0010 / 0001
Initialize SSD1289 and display

data from generic input
240 x 320
RGB data
Set SSD1289 RAM write address

and GDDRAM X and Y address
counter
120 x 64
Set DMode = 11 and OEDef =
0
RAM data
SSD1289
Define the position of the window

to display RAM data
Set TRANS = 1 to enable
transparent function
Picture in Picture
TY[1:0]: In 262k color mode, 16 bit parallel interface, there are three types of methods in writing data into the ram,
Type A, B and C are described as below.
TY1
0
0
1
Interface Color mode Cycle

st
262k Type A 1
nd
2
rd
3
st
16 bit 262k Type B 1
nd
2
st
262k Type C 1
nd
2
Remark :
Solomon Systech
D17
R5
B5
G5
R5
x
R5
B5
D16
R4
G4
G4
R4
x
R4
G4
TY0
0
1
0
D15
R3
B3
G3
R3
x
R3
B3
D14
R2
B2
G2
R2
x
R2
B2
Writing mode
Type A
Type B
Type C
D13
R1
B1
G1
R1
x
R1
B1
Hardware pins
D12 D11 D10 D9 D8 D7
R0 x
x
G5 G4
B0 x
x
R5 R4
G0 x
x
B5 G4
R0 x
x
G5 G4
x
x
x
B5 G4
R0 x
x
G5 G4
B0 x
x
x
x
D6
G3
R3
B3
G3
B3
G3
x
D5
G2
R2
B2
G2
B2
G2
x
D4
G1
R1
B1
G1
B1
G1
x
D3 D2 D1 D0
G0 x
x
R0 x
x
B0 x
x
G0 x
x
B0 x
x
G0 x
x
x
x
x
Don't care bits

Not connected pins
Apr 2007 P 42/82
Rev 1.3
SSD1289
ID[1:0]: The address counter is automatically incremented by 1, after data are written to the GDDRAM when ID[1:0] =
1. The address counter is automatically decremented by 1, after data are written to the GDDRAM when ID[1:0] = 0.
The setting of incrementing or decrementing of the address counter can be made independently in each upper and lower
bit of the address. The direction of the address when data are written to the GDDRAM is set with AM bits.
AM: Set the direction in which the address counter is updated automatically after data are written to the GDDRAM.
When AM = 0, the address counter is updated in the horizontal direction. When AM = 1, the address counter is
updated in the vertical direction. When window addresses are selected, data are written to the GDDRAM area specified
by the window addresses in the manner specified with ID1-0 and AM bits.
ID[1:0]="00
Horizontal: decrement
Vertical: decrement
ID[1:0]="01
Horizontal: increment
Vertical: decrement
ID[1:0]="10
Horizontal: decrement
Vertical: increment
ID[1:0]="11
Horizontal: increment
Vertical: increment
00,00h
00,00h
00,00h
00,00h
AM="0
Horizontal
13F,EFh
13F,EFh
13F,EFh
00,00h
00,00h
00,00h
13F,EFh
00,00h
AM="1
Vertical
13F,EFh
13F,EFh
13F,EFh
13F,EFh
LG[2:0]: Write data to the GDDRAM after comparing the write data written to the GDDRAM by the microcomputer
with the values in the compare registers (CPR[5:0], CPG[5:0], CPB[5:0]) and performing a logical and arithmetic
operation on them.
Generic Interface Control (R15h) (POR = 00d0h)

R/W DC
W
1
POR

0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
1
1
IB6
1
1
IB5
0
0
IB4
1
1
IB3
IB2
IB1
IB0
INVDOT INVDEN INVHS INVVS
INVDOT: sets the signal polarity of DOTCLK pin. When INVDOT = 1, set DOTCLK is negative edge trigger.
INVDEN: sets the signal polarity of DEN pin. When INVDEN = 1, set DEN is active low.
INVHS: sets the signal polarity of HSYNC pin. When INVHS = 1, set inverse polarity of HSYNC.
INVVS: sets the signal polarity of VSYNC pin.When INVVS = 1, set inverse polarity of VSYNC.
SSD1289
Rev 1.3
P 43/82
Apr 2007
Solomon Systech
Horizontal Porch (R16h) (POR = EF1Ch)

R/W
W
DC
1

XL7 XL6 XL5 XL4 XL3
IB10
XL2
IB9
XL1
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
XL0 HBP7 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
XL[7:0]: Set the number of valid pixel per line. Number of valid pixel per line is equal to XL[7:0] + 1
XL7
0
0
0
XL6
XL5
XL4
XL3
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
XL2
XL1
XL0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
0
1
0
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
No. of pixel per

line
1
2
3
:
Step = 1
:
239
240 (POR)
Reserved
Reserved
HBP[7:0]: Set the delay period from falling edge of HSYNC signal to first valid data. The pixel data exceed the range
set by XL[7:0] and before the first valid data will be treated as dummy data.
HBP7
HBP6
HBP5
HBP4
HBP3
0
0
0
0
0
0
0
0
0
0
HBP2
HBP1
HBP0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
0
1
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
:
:
:
1
1
1
1
1
1
1
1
No. of clock
cycle of
DOTCLK
2
3
:
Step = 1
:
28
29
30 (POR)
31
32
:
Step = 1
:
256
257
Cycle time of HYSYNC

Set by HBP[7:0]
Set by XL[7:0]
HYSNC
Default 240 pixels per line
Pixel
Data
Dummy
D0
D1
D2
D237 D238 D239
Dummy
DOTCLK
Default 30 clock cycles

of DOTCLK
Solomon Systech
Apr 2007 P 44/82
Rev 1.3
SSD1289
Vertical Porch (R17h) (POR = 0103h)

R/W DC
W
1
POR

0
VFP6 VFP5 VFP4 VFP3 VFP2
0
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VFP1 VFP0 VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
0
1
0
0
0
0
0
0
1
1
VFP[6:0]: Set the delay period from the last valid line to the falling edge of VSYNC of the next frame. The line data
within this delay period will be treated as dummy line.
VFP6 VFP5 VFP4 VFP3 VFP2 VFP1 VFP0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
No. of clock cycle of

HSYNC
1
2 (POR)
:
Step = 1
:
127
128
VBP[7:0]: Set the delay period from falling edge of VSYNC to first valid line. The line data within this delay period
will be treated as dummy line.
VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
1
:
:
:
1
1
1
1
1
1
1
1
No. of clock cycle of

HSYNC
1
2
3
4 (POR)
:
Step = 1
:
255
256
Cycle time of VSYNC

Set by VFP[6:0]
Set by VBP[7:0]
VSYNC
Set by MUX[8:0]
HSYNC
Dummy Lines
SSD1289
Rev 1.3
P 45/82
st
1 Line
Apr 2007
Last Line
Dummy Lines
Solomon Systech
Power Control 5 (R1Eh) (POR = 0029h)

R/W DC
W
1
POR*

0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
nOTP
0
IB6
0
0
IB5
IB4
IB3
IB2
IB1
IB0
VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
1
0
1
0
0
1
nOTP: nOTP equals to 0 after power on reset and VcomH voltage equals to programmed OTP value. When nOTP set
to 1, setting of VCM[5:0] becomes valid and voltage of VcomH can be adjusted.
VCM[5:0]: Set the VcomH voltage if nOTP = 1. These bits amplify the VcomH voltage 0.35 to 0.99 times the
VLCD63 voltage. Default value is 101001 when power on reset.
VCM5
0
0
VCM4
0
0
VCM3
0
0
VCM2
0
0
VCM1
0
0
VCM0
0
1
1
1
1
1
0
1
:
:
:
1
1
1
1
1
1
VcomH
VLCD63 x 0.35
VLCD63 x 0.36
:
Step = 0.01
:
VLCD63 x 0.98
VLCD63 x 0.99
Write Data to GRAM (R22h)

R/W
W
DC
1
D[17:0]
WD[17:0] mapping depends on the interface setting
WD[17:0]: Transforms all the GDDRAM data into 18-bit, and writes the data. Format for transforming data into 18-bit
depends on the interface used. SSD1289 selects the grayscale level according to the GDDRAM data. After writing data
to GDDRAM, address is automatically updated according to AM bit and ID bit. Access to GDDRAM during stand-by
mode is not available.
Read Data from GRAM (R22h)

R/W
R
DC
1
D[17:0]
RD[17:0] mapping depends on the interface setting
RD[17:0]: Read 18-bit data from the GDDRAM. When the data is read to the microcomputer, the first-word read
immediately after the GDDRAM address setting is latched from the GDDRAM to the internal read-data latch. The data
on the data bus (DB170) becomes invalid and the second-word read is normal. When bit processing, such as a logical
operation, is performed, only one read can be processed since the latched data in the first word is used.
RAM write data mask (R23h R24h) (POR = 0000h)

Reg#
R23h
R24h
R/W
DC
W
1
POR
W O 1
POR
IB15
IB14
IB13
IB12
IB11
IB10
WMR5 WMR4 WMR3 WMR2 WMR1 WMR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IB9
0
0
0
0
IB8
0
0
0
0
IB7
IB6
IB5
IB4
IB3
IB2
WMG5 WMG4 WMG3 WMG2 WMG1 WMG0
WMB5 WMB4 WMB3 WMB2 WMB1 WMB0
IB1
0
0
0
0
IB0
0
0
0
0
WMR[5:0], WMG[5:0], WMB[5:0]: In writing to the GDDRAM, these bits write-mask the data to be written to the
GDDRAM by a bit unit. For example, if WMR5 = 1, the WMR5 write-mask is enabled and data RR5 will be masked
and not write into the GDDRAM. WMR[5:0] mask pins RR[5:0], WMG[5:0] mask pins GG[5:0], and WMB[5:0] mask
pins BB[5:0]. For writing GDDRAM methods, refer to Section 14 Interface Mapping.
Solomon Systech
Apr 2007 P 46/82
Rev 1.3
SSD1289
Frame Frequency Control (R25h) (POR = 8000h)

R/W DC IB15 IB14 IB13 IB12 IB11
W
1 OSC3 OSC2 OSC1 OSC0 0
POR*
1
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
0
0
IB2
1
0
IB1
1
0
OSC[3:0]: Set the frame frequency by OSC[3:0]

OSC[3:0]
Internal Oscillator
Frequency (Hz)
Corresponding
Frame Freq (Hz)
(other registers are at
POR value)
0000
0010
0101
1000
1010
1100
1110
390K
430K
470K
510K
548K
587K
626K
50
55
60
65
70
75
80
Vcom OTP (R28h R29h)

Reg# R/W
R28h W
R29h W
DC
1
1
IB15
0
1
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
1
IB6
0
1
IB5
0
0
IB4
0
0
IB3
0
0
IB0
0
0
When OTP is access, these registers must be set accordantly.

OTP programming sequence
Step
Operation
Power up the module at VCI = 2.7V, VDDEXT = VDDIO = 1.8V.
1
Turn on the display as normal to 65k/262k color mode (displaying a test
pattern if any).
Set nOTP to 1 (R1Eh) and optimizes VcomH by adjusting VCM[5:0]
2
(R1Eh).
3
Power down the whole module.
Connect a supply to the module at VCI = 2.7V, VDDEXT = VDDIO =
4
1.8V
Write below commands for OTP initialization and wait for 200ms for
activate the OTP :
Index
Value
R00h
0x0001
5
R28h
0x0006
R29h
0x80C0
Connect a 14.5V supply to VGH through a current limiting resistor, see
figure below.
Write the optimized value found in Step 2 to VCM[5:0] (R1Eh) and set
6
nOTP to 1.
7
Fire the OTP by write HEX code 000Ah to register R28h.
8
Wait 500ms.
OTP complete. Power down the whole module and remove 14.5V
9
supply.
Note: nOTP must set to 0 to activate the OTP effect.
Precaution:
1. All capacitors on OTP machine should be discharged completely before placing the LCD module.
2. The OTP programming voltage should not be applied when placing and removing the LCD module.
3. The OTP programming voltage should not be applied before VDDIO/VDDEXT/VCI.
4. After OTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before
removing the LCD module.
SSD1289
Rev 1.3
P 47/82
Apr 2007
Solomon Systech
Figure 9-3 OTP circuitry
SSD1289
VGH
+C
-
Note:
GND
14.5V
R = 1K ~ 2k ohm
C = 1uF
(built-in on the module)
GND
Gamma Control (R30h to R3Bh)

Reg# R/W DC
IB15
IB14
IB13
IB12
IB11
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
VRP
14
VRN
14
VRP
13
VRN
13
IB10
PKP
12
PKP
32
PKP
52
PRP
12
PKN
12
PKN
32
PKN
52
PRN
12
VRP
12
VRN
12
IB9
PKP
11
PKP
31
PKP
51
PRP
11
PKN
11
PKN
31
PKN
51
PRN
11
VRP
11
VRN
11
IB8
PKP
10
PKP
30
PKP
50
PRP
10
PKN
10
PKN
30
PKN
50
PRN
10
VRP
10
VRN
10
IB7
IB6
IB5
IB4
IB3
VRP
03
VRN
03
IB2
PKP
02
PKP
22
PKP
42
PRP
02
PKN
02
PKN
22
PKN
42
PRN
02
VRP
02
VRN
02
IB1
PKP
01
PKP
21
PKP
41
PRP
01
PKN
01
PKN
21
PKN
41
PRN
01
VRP
01
VRN
01
IB0
PKP
00
PKP
20
PKP
40
PRP
00
PKN
00
PKN
20
PKN
40
PRN
00
VRP
00
VRN
00
Note: please refer to table 5 for POR values.

PKP[52:00]: Gamma micro adjustment register for the positive polarity output
PRP[12:00]: Gradient adjustment register for the positive polarity output
VRP[14:00]: Adjustment register for amplification adjustment of the positive polarity output
PKN[52:00]: Gamma micro adjustment register for the negative polarity output
PRN[12:00]: Gradient adjustment register for the negative polarity output
VRN[14:00]: Adjustment register for the amplification adjustment of the negative polarity output.
(For details, see the Section 11 Gamma Adjustment Function).
Solomon Systech
Apr 2007 P 48/82
Rev 1.3
SSD1289
Vertical Scroll Control (R41h-R42h) (POR =0000h)

Reg# R/W DC
W
1
R41h
POR
W
1
R42h
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VL18 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10
0
0
0
0
0
0
0
0
0
VL28 VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20
0
0
0
0
0
0
0
0
0
VL1[8:0]: Specify scroll length at the scroll display for vertical smooth scrolling. Any raster-row from the first to 320th
can be scrolled for the number of the raster-row. After 320th raster-row is displayed, the display restarts from the first
raster-row. The display-start raster-row (VL1[8:0]) is valid when VLE1 = 1 or VLE2 = 1. The raster-row display is
fixed when VLE[2:1] = 00.
VL2[8:0]: Specify scroll length at the scroll display for vertical smooth scrolling at 2nd screen. The display-start rasterrow (VL2[8:0]) is valid when VLE1 = 1 and VLE2 = 1.
Horizontal RAM address position (R44h) (POR = EF00h)

R/W DC
W
1
POR

IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
HSA[7:0]/HEA[7:0]: Specify the start/end positions of the window address in the horizontal direction by an address unit.
Data are written to the GDDRAM within the area determined by the addresses specified by HEA[7:0] and HSA[7:0].
These addresses must be set before the RAM write. In setting these bits, make sure that 00h HSA[7:0] HEA[7:0]
EFh.
Vertical RAM address position (R45h-R46h)

Reg# R/W DC
W
1
R45h
POR
W
1
R46h
POR
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
0
0
0
0
0
0
0
0
0
VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
1
0
0
1
1
1
1
1
1
VSA[8:0]/VEA[8:0]: Specify the start/end positions of the window address in the vertical direction by an address unit.
Data are written to the GRAM within the area determined by the addresses specified by VEA[8:0] and VSA[8:0]. These
addresses must be set before the RAM write. In setting these bits, make sure that 00h VSA[8:0] VEA[8:0]
13Fh.
1st Screen driving position (R48h-R49h)
Reg# R/W DC
W
1
R48h
POR
W
1
R49h
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
0
0
0
0
0
0
0
0
0
SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
1
0
0
1
1
1
1
1
1
SS1[8:0]: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the set gate
driver, i.e. the first driving Gate is G0 if SS1[8:0] = 00H
SE1[8:0]: Specify the driving end position for the first screen in a line unit. The LCD driving is performed to the set gate
driver. For instance, when SS1[8:0] = 07H and SE1[8:0] = 10H are set, the LCD driving is performed from G7 to
G16, and non-selection driving is performed for G1 to G6, G17, and others. Ensure that SS1[8:0] SE1[8:0] 13FH.
SSD1289
Rev 1.3
P 49/82
Apr 2007
Solomon Systech
2nd Screen driving position (R4Ah-R4Bh)

Reg# R/W DC
W
1
R4Ah
POR
W
1
R4Bh
POR
IB15
0
0
0
0
IB14
0
0
0
0
IB13
0
0
0
0
IB12
0
0
0
0
IB11
0
0
0
0
IB10
0
0
0
0
IB9
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
0
0
0
0
0
0
0
0
0
SE28 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
1
0
0
1
1
1
1
1
1
SS2[8:0]: Specify the driving start position for the second screen in a line unit. The LCD driving starts from the set gate
driver. The second screen is driven when SPT = 1.
SE2[8:0]: Specify the driving end position for the second screen in a line unit. The LCD driving is performed to the set
gate driver. For instance, when SPT = 1, SS2[8:0] = 20H, and SE2[8:0] = 2FH are set, the LCD driving is
performed from G32 to G47. Ensure that SS1[8:0] SE1[8:0] ; SS2[8:0] SE2[8:0] 13FH.
RAM address set (R4Eh-R4Fh)
Reg# R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9
W
1
0
0
0
0
0
0
0
R4Eh
POR
0
0
0
0
0
0
0
W
1
0
0
0
0
0
0
0
R4Fh
POR
0
0
0
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0
0
0
0
0
0
0
0
0
0
YAD8 YAD7 YAD6 YAD5 YAD4 YAD 3 YAD 2 YAD 1 YAD 0
0
0
0
0
0
0
0
0
0
XAD[7:0]: Make initial settings for the GDDRAM X address in the address counter (AC).
YAD[8:0]: Make initial settings for the GDDRAM Y address in the address counter (AC).
After GDDRAM data are written, the address counter is automatically updated according to the settings with AM, I/D
bits and setting for a new GDDRAM address is not required in the address counter. Therefore, data are written
consecutively without setting an address. The address counter is not automatically updated when data are read out from
the GDDRAM. GDDRAM address setting cannot be made during the standby mode. The address setting should be made
within the area designated with window addresses.
Optimize data access speed (R28 + R2F + R12)
Reg# R/W
R28h W
R2Fh W
R12h W
DC
1
1
1
IB15
0
0
0
IB14
0
0
1
IB13
0
0
1
IB12
0
1
0
IB11
0
0
1
IB10
0
0
1
IB9
0
1
0
IB8
0
0
0
IB7
0
1
1
IB6
0
0
1
IB5
0
1
1
IB4
0
1
0
IB3
0
1
1
IB2
1
1
0
IB1
1
1
1
IB0
0
0
1
For video application, data access speed optimization may necessary in order to generate smooth display during the high
speed RAM update.
The data access speed optimization function is only valid by using three set (R28, R2F, R12) of commands together with
correct sequence.
Solomon Systech
Apr 2007 P 50/82
Rev 1.3
SSD1289
Window Address Function

The window address function enables writing display data sequentially in a window address area made in the internal
GDDRAM. The window address area is made by setting the horizontal address register (start: HSA7-0, end: HEA 7-0
bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and ID[1:0] bits set the transition
direction of RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables
the SSD1289 to write data including image data sequentially without taking the data wrap position into account. The
window address area must be made within the GDDRAM address map area.
Condition:
00h HSA[7:0] HEA[7:0] EFh
00h VSA[8:0] VEA[8:0] 13Fh
AM and ID[1:0] refer to R11h
GDDRAM address map
0000h
0000h
00EFh
0000h
Window address area
120x40 at middle
0000h
013Fh
00EFh
013Fh
Window address setting area:

HSA[7:0] = 3Bh; HEA[7:0] = B3h
VSA[8:0] = 8Bh; VEA[8:0] = B3h
AM = 0 and ID[1;]] = 11
SSD1289
Rev 1.3
P 51/82
Apr 2007
Solomon Systech
Partial Display Mode

The SSD1289 enables to selectively drive two screens at arbitrary positions with the screen-driving position registers
(R48h to R4Bh). Only the lines required to display two screens at arbitrary positions are selectively driven to reduce the
power consumption.
The first screen driving position registers (R48 and R49) specifies the start line (SS18-10) and the end line (SE18-10) for
displaying the first screen. The second screen driving position register (R4A) specifies the start line (SS28-20) and the
end line (SE28-20) for displaying the second screen. The second screen control is effective when the SPT bit is set to 1.
The total number of lines driven for displaying the first and second screens must be less than the number of lines to drive
the LCD.
Condition:
SS1[8:0] SE1[8:0] 13FH
SS1[8:0] SE1[8:0]
SS2[8:0] SE2[8:0] 13FH
G0
G9
SSD1289
1st screen
Non display area
G150
G159
SOLOMON SYSTECH
2nd screen
Non display area
The number of driven display lines: MUX[8:0] = 13F (319+1 lines)

1st screen setting: SS[18:10] = 00h, SE[18:10] = 09h
2nd screen seeting: SS[28:10] = 96h, SE[28:10] = 9Fh
Solomon Systech
Apr 2007 P 52/82
Rev 1.3
SSD1289
10 GAMMA ADJUSTMENT FUNCTION

The SSD1289 incorporates gamma adjustment function for the 262,144-color display. Gamma adjustment is
implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle
adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid
crystal panels specification.
RGB Interface
Display Data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
PKP02 PKP01 PKP00

PKP12 PKP11 PKP10
PKP22 PKP21 PKP20
Positive
polarity
register
V0
PKP32 PKP31 PKP30

PKP42 PKP41 PKP40
8-levels
Grayscale
amplifier
PRP12 PRP11 PRP10
6-bits
6-bits
64 grayscale
Control <R>
64 grayscale
Control <G>
64 grayscale
Control 
LCD Driver
LCD Driver
LCD Driver
64 levels
PKP52 PKP51 PKP50

PRP02 PRP01 PRP00
6-bits
VRP03 VRP02 VRP01 VRP00

VRP14 VRP13 VRP12 VRP11 VRP10
V63
PKN02 PKN01 PKN00
PKN12 PKN11 PKN10
PKN22 PKN21 PKN20
Negative
polarity
register
PKN32 PKN31 PKN30
PKN42 PKN41 PKN40

PKN52 PKN51 PKN50
PRN02 PRN01 PRN00
LCD
PRN12 PRN11 PRN10

VRN03 VRN02 VRN01 VRN00
VRN14 VRN13 VRN12 VRN11 VRN10
SSD1289
Rev 1.3
P 53/82
Apr 2007
Solomon Systech
10.1 Structure of Grayscale Amplifier

Below figure indicates the structure of the grayscale amplifier. It determines 8 levels (VIN0-VIN7) by the gradient
adjuster and the micro adjustment register. Also, dividing these levels with ladder resistors generates V0 to V63.
Gradient
adjustment register
VLCD63
PRP0
3
PRP1
PKP0
Amplitude
adjustment register
Micro adjustment register
PKP1
PKP2
PKP3
PKP4
3
PKP5
VRP0
VRP1
VINP0
V0
VINP1
8 to 1
selector
V1
:
V7
VINP2
8 to 1
selector
VINP3
VINP4
8 to 1
selector
Grayscale Amplifier
8 to 1
selector
Ladder resistor
V8
V19
V20
:
V42
V43
:
V54
VINP5
8 to 1
selector
V55
:
V61
8 to 1
selector
VINP6
VINP7
*
GND
Solomon Systech
V62
V63
Individual ladder resistors are used for positive and

negative polarity.
Apr 2007 P 54/82
Rev 1.3
SSD1289
Ladder resistor for negative polarity
Ladder resistor for positive polarity

VLCD63
VRP0[3:0]
0 to 30R
VRP0
5R
4R
0 to 28R
VRHP
1R
5R
RP1
RP2
RP3
RP4
RP5
RP6
RP7
1R
16R
RP23
1R
RP24
RP25
RP26
RP27
RP28
RP29
RP30
1R
0 to 28R
VRLP
4R
5R
0 to 31R
VRP1 8R
PKP0[2:0]
KVP1
KVP2
KVP3
KVP4
KVP5 8 to 1
KVP6 selector
KVP7
KVP8
PRP0[2:0]
KVP9
RP8
KVP10
RP9
KVP11
RP10 KVP12
RP11 KVP13 8 to 1
RP12 KVP14 selector
RP13 KVP15
RP14 KVP16
RP15
RP31
RP32
RP33
RP34
RP35
RP36
RP37
RP38
VRN0[3:0]
VRN0
KVP0
RP0
RP16
RP17
RP18
RP19
RP20
RP21
RP22
5R
VINP0
VINP1
PKP1[2:0]
VINP2
PKP2[2:0]
KVP17
KVP18
KVP19
KVP20
KVP21 8 to 1
KVP22 selector
KVP23
KVP24
VINP3
PKP3[2:0]
KVP25
KVP26
KVP27
KVP28
KVP29 8 to 1
KVP30 selector
KVP31
KVP32
VINP4
PKP4[2:0]
KVP33
KVP34
KVP35
KVP36
KVP37 8 to 1
KVP38 selector
KVP39
KVP40
PRP1[2:0]
KVP41
RP38 KVP42
RP40 KVP43
RP41 KVP44
RP42 KVP45 8 to 1
RP43 KVP46 selector
RP44 KVP47
RP45 KVP48
VINP5
PKP5[2:0]
RP46
VINP6
VINP7
VRP1[4:0]
RP47
5R
4R
0 to 28R
VRHN
1R
5R
KVN0
RN0
RN1
RN2
RN3
RN4
RN5
RN6
RN7
PRN0[2:0]
KVN9
RN8 KVN10
RN9 KVN11
RN10 KVN12
RN11 KVN13 8 to 1
RN12 KVN14 selector
RN13 KVN15
RN14 KVN16
RN15
1R
RN16
RN17
RN18
RN19
RN20
RN21
RN22
16R
RN23
1R
RN24
RN25
RN26
RN27
RN28
RN29
RN30
5R
1R
0 to 28R
VRLN
4R
KVN1
KVN2
KVN3
KVN4
KVN5 8 to 1
KVN6 selector
KVN7
KVN8
RN31
RN32
RN33
RN34
RN35
RN36
RN37
RN38
PKN0[2:0]
VINN1
PKN1[2:0]
VINN2
PKN2[2:0]
KVN17
KVN18
KVN19
KVN20
KVN21 8 to 1
KVN22 selector
KVN23
KVN24
VINN3
PKN3[2:0]
KVN25
KVN26
KVN27
KVN28
KVN29 8 to 1
KVN30 selector
KVN31
KVN32
VINN4
PKN4[2:0]
KVN33
KVN34
KVN35
KVN36
KVN37 8 to 1
KVN38 selector
KVN39
KVN40
PRN1[2:0]
KVN41
RN38 KVN42
RN40 KVN43
RN41 KVN44
RN42 KVN45 8 to 1
RN43 KVN46 selector
RN44 KVN47
RN45 KVN48
5R
0 to 31R
VRN1 8R
VINN0
VINN5
PKN5[2:0]
VINN6
VINN7
VRN1[4:0]
RN47
GND
SSD1289
Rev 1.3
P 55/82
Apr 2007
Solomon Systech
10.2 Gamma Adjustment Register

This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This
register can independent set up to positive/negative polarities and there are three types of register groups to adjust
gradient, amplitude, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. (Using
the same setting for Reference-value and R.G.B.) Following graphics indicates the operation of each adjusting register.
Grayscale Number
10.2.1
Micro adjustment
Grayscale Voltage
Amplitude adjustment
Grayscale Voltage
Grayscale Voltage
Gradient adjustment
Grayscale Number
Grayscale Number
Gradient adjusting register
The gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the
grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistors in
the middle of the ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator. Also, there is an
independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive.
10.2.2
Amplitude adjusting register
The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it
controls the variable resistors in the boundary of the ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale
voltage generator. Also, there is an independent resistor on the positive/negative polarities as well as the gradientadjusting resistor.
10.2.3
Micro adjusting register
The micro-adjusting register is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it
controls each reference voltage level by the 8 to 1 selector towards the 8-level reference voltage generated from the
ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting
resistors.
Solomon Systech
Apr 2007 P 56/82
Rev 1.3
SSD1289
10.3
Ladder Resistor / 8 to 1 selector
This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable
resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. The gamma registers control the
variable resistors and 8 to 1 selector resistors.
Variable Resistor
There are 3 types of the variable resistors that are for the gradient and amplitude adjustment. The resistance is set by the
resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0 / VRP(N)1) as below.
PRP(N)[0:1]
000
001
010
011
100
101
110
111
Resistance
0R
4R
8R
12R
16R
20R
24R
28R
VRP(N)0
0000
0001
0010
Resistance
0R
2R
4R
VRP(N)1
00000
00001
00010
:
Step = 1R
:
:
Step = 2R
:
1110
1111
Resistance
0R
1R
2R
28R
30R
11110
11111
30R
31R
8 to 1 selecter
In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which are generated by the ladder resistors.
There are six types of reference voltage (VIN1 to VIN6) and totally 48 divided voltages can be selected in one ladder
resistor. Following figure explains the relationship between the micro-adjusting register and the selecting voltage.
Registor
PKP[2:0]
000
001
010
011
100
101
110
111
VINP1
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
Grayscale voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
SSD1289
Postive polarity
Selected voltage
VINP2 VINP3 VINP4
KVP9 KVP17 KVP25
KVP10 KVP18 KVP26
KVP11 KVP19 KVP27
KVP12 KVP20 KVP28
KVP13 KVP21 KVP29
KVP14 KVP22 KVP30
KVP15 KVP23 KVP31
KVP16 KVP24 KVP32
VINP5
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
VINP6
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
Formula
Grayscale voltage
VINP(N)0
V22
VINP(N)1
V23
V8+(V1-V8)*(30/48)
V24
V8+(V1-V8)*(23/48)
V25
V8+(V1-V8)*(16/48)
V26
V8+(V1-V8)*(12/48)
V27
V8+(V1-V8)*(8/48)
V28
V8+(V1-V8)*(4/48)
V29
VINP(N)2
V30
V20+(V8-V20)*(22/24)
V31
V20+(V8-V20)*(20/24)
V32
V20+(V8-V20)*(18/24)
V33
V20+(V8-V20)*(16/24)
V34
V20+(V8-V20)*(14/24)
V35
V20+(V8-V20)*(12/24)
V36
V20+(V8-V20)*(10/24)
V37
V20+(V8-V20)*(8/24)
V38
V20+(V8-V20)*(6/24)
V39
V20+(V8-V20)*(4/24)
V40
V20+(V8-V20)*(2/24)
V41
VINP(N)3
V42
V43+(V20-V43)*(22/23)
V43
Rev 1.3
P 57/82
Apr 2007
Registor
PKN[2:0]
000
001
010
011
100
101
110
111
Negative polarity
Selected voltage
VINN1 VINN2 VINN3 VINN4
KVN1 KVN9 KVN17 KVN25
Formula
Grayscale voltage
V43+(V20-V43)*(21/23)
V44
V43+(V20-V43)*(20/23)
V45
V43+(V20-V43)*(19/23)
V46
V43+(V20-V43)*(18/23)
V47
V43+(V20-V43)*(17/23)
V48
V43+(V20-V43)*(16/23)
V49
V43+(V20-V43)*(15/23)
V50
V43+(V20-V43)*(14/23)
V51
V43+(V20-V43)*(13/23)
V52
V43+(V20-V43)*(12/23)
V53
V43+(V20-V43)*(11/23)
V54
V43+(V20-V43)*(10/23)
V55
V43+(V20-V43)*(9/23)
V56
V43+(V20-V43)*(8/23)
V57
V43+(V20-V43)*(7/23)
V58
V43+(V20-V43)*(6/23)
V59
V43+(V20-V43)*(5/23)
V60
V43+(V20-V43)*(4/23)
V61
V43+(V20-V43)*(3/23)
V62
V43+(V20-V43)*(2/23)
V63
V43+(V20-V43)*(1/23)
VINP(N)4
VINN5
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
VINN6
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
Formula
V55+(V43-V55)*(22/24)
V55+(V43-V55)*(20/24)
V55+(V43-V55)*(18/24)
V55+(V43-V55)*(16/24)
V55+(V43-V55)*(14/24)
V55+(V43-V55)*(12/24)
V55+(V43-V55)*(10/24)
V55+(V43-V55)*(8/24)
V55+(V43-V55)*(6/24)
V55+(V43-V55)*(4/24)
V55+(V43-V55)*(2/24)
VINP(N)5
V62+(V55-V62)*(44/48)
V62+(V55-V62)*(40/48)
V62+(V55-V62)*(36/48)
V62+(V55-V62)*(32/48)
V62+(V55-V62)*(25/48)
V62+(V55-V62)*(18/48)
VINP(N)6
VINP(N)7
Solomon Systech
Reference voltage of positive polarity:

Reference
Formula
Micr0-adjusting rgister
-KVP0
VLCD63 - V x VRP0 / SUMRP
PKP0[2:0] = 000
KVP1
VLCD63 - V x (VRP0 + 5R) / SUMRP
PKP0[2:0] = 001
KVP2
PKP0[2:0] = 010
KVP3
PKP0[2:0] = 011
KVP4
PKP0[2:0] = 100
KVP5
PKP0[2:0] = 101
KVP6
PKP0[2:0] = 110
KVP7
PKP0[2:0] = 111
KVP8
PKP1[2:0] = 000
KVP9
VLCD63 - V x (VRP0 + 33R + VRHP) / SUMRP
PKP1[2:0] = 001
KVP10
PKP1[2:0] = 010
KVP11
PKP1[2:0] = 011
KVP12
PKP1[2:0] = 100
KVP13
PKP1[2:0] = 101
KVP14
PKP1[2:0] = 110
KVP15
PKP1[2:0] = 111
KVP16
PKP2[2:0] = 000
KVP17
PKP2[2:0] = 001
KVP18
PKP2[2:0] = 010
KVP19
PKP2[2:0] = 011
KVP20
PKP2[2:0] = 100
KVP21
PKP2[2:0] = 101
KVP22
PKP2[2:0] = 110
KVP23
PKP2[2:0] = 111
KVP24
PKP3[2:0] = 000
KVP25
PKP3[2:0] = 001
KVP26
PKP3[2:0] = 010
KVP27
PKP3[2:0] = 011
KVP28
PKP3[2:0] = 100
KVP29
PKP3[2:0] = 101
KVP30
PKP3[2:0] = 110
KVP31
PKP3[2:0] = 111
KVP32
PKP4[2:0] = 000
KVP33
PKP4[2:0] = 001
KVP34
PKP4[2:0] = 010
KVP35
PKP4[2:0] = 011
KVP36
PKP4[2:0] = 100
KVP37
PKP4[2:0] = 101
KVP38
PKP4[2:0] = 110
KVP39
PKP4[2:0] = 111
KVP40
PKP5[2:0] = 000
KVP41
VLCD63 - V x (VRP0 + 87R + VRHP + VRLP) / SUMRP
PKP5[2:0] = 001
KVP42
PKP5[2:0] = 010
KVP43
PKP5[2:0] = 011
KVP44
PKP5[2:0] = 100
KVP45
PKP5[2:0] = 101
KVP46
PKP5[2:0] = 110
KVP47
VLCD63-V x (VRP0 + 111R + VRHP + VRLP) / SUMRP
PKP5[2:0] = 111
KVP48
-KVP49
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1
V: Voltage difference between VLCD63 and of GND.
Solomon Systech
Apr 2007 P 58/82
Reference voltage
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
Rev 1.3
SSD1289
Reference voltage of negative polarity:

Reference
Formula
Micr0-adjusting rgister
-KVN0
VLCD63 - V x VRN0 / SUMRN
PKN0[2:0] = 000
KVN1
VLCD63 - V x (VRN0 + 5R) / SUMRN
PKN0[2:0] = 001
KVN2
PKN0[2:0] = 010
KVN3
PKN0[2:0] = 011
KVN4
PKN0[2:0] = 100
KVN5
PKN0[2:0] = 101
KVN6
PKN0[2:0] = 110
KVN7
PKN0[2:0] = 111
KVN8
PKN1[2:0] = 000
KVN9
VLCD63 - V x (VRN0 + 33R + VRHN) / SUMRN
PKN1[2:0] = 001
KVN10
PKN1[2:0] = 010
KVN11
PKN1[2:0] = 011
KVN12
PKN1[2:0] = 100
KVN13
PKN1[2:0] = 101
KVN14
PKN1[2:0] = 110
KVN15
PKN1[2:0] = 111
KVN16
PKN2[2:0] = 000
KVN17
PKN2[2:0] = 001
KVN18
PKN2[2:0] = 010
KVN19
PKN2[2:0] = 011
KVN20
PKN2[2:0] = 100
KVN21
PKN2[2:0] = 101
KVN22
PKN2[2:0] = 110
KVN23
PKN2[2:0] = 111
KVN24
PKN3[2:0] = 000
KVN25
PKN3[2:0] = 001
KVN26
PKN3[2:0] = 010
KVN27
PKN3[2:0] = 011
KVN28
PKN3[2:0] = 100
KVN29
PKN3[2:0] = 101
KVN30
PKN3[2:0] = 110
KVN31
PKN3[2:0] = 111
KVN32
PKN4[2:0] = 000
KVN33
PKN4[2:0] = 001
KVN34
PKN4[2:0] = 010
KVN35
PKN4[2:0] = 011
KVN36
PKN4[2:0] = 100
KVN37
PKN4[2:0] = 101
KVN38
PKN4[2:0] = 110
KVN39
PKN4[2:0] = 111
KVN40
PKN5[2:0] = 000
KVN41
VLCD63 - V x (VRN0 + 87R + VRHN + VRLN) / SUMRN
PKN5[2:0] = 001
KVN42
PKN5[2:0] = 010
KVN43
PKN5[2:0] = 011
KVN44
PKN5[2:0] = 100
KVN45
PKN5[2:0] = 101
KVN46
PKN5[2:0] = 110
KVN47
VLCD63-V x (VRN0 + 111R + VRHN + VRLN) / SUMRN
PKN5[2:0] = 111
KVN48
-KVN49
SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1
V: Voltage difference between VLCD63 and of GND.
SSD1289
Rev 1.3
P 59/82
Apr 2007
Reference voltage
VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
Solomon Systech
11 MAXIMUM RATINGS
Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDDIO
VDDEXT
VCI
I
TA
Tstg
Parameter
Supply Voltage
Input Voltage
Current Drain Per Pin Excluding VDDIO and
VSS
Operating Temperature
Storage Temperature
Value
-0.3 to +4.0
-0.3 to +4.0
VSS - 0.3 to 5.0
Unit
V
V
V
25
mA
-20 to +70
-65 to +150
o
o
C
C
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, strong electric fields, when exposed to a MOS
device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using
insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material.
All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must
not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. It is advised that proper precautions to be taken
to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VCI and Vout be
constrained to the range VSS < VDDIO VCI < VOUT. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either
VSS or VDDIO). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during
normal operation. This device is not radiation protected.
12 DC CHARACTERISTICS
DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 1.65 to 3.6V, TA = -20 to 70C)
Symbol
Parameter
VDDIO
Power supply pin of IO pins
VDDEXT
Auxiliary power supply pin for

VDD
Test Condition
Recommend Operating Voltage
Possible Operating Voltage
VCI
Booster Reference Supply

Voltage Range

VGH
VCIX2
VGH
VGL
VcomH
VcomL
VLCD63
VLCD63
VOH1
VOL1
VIH1
VIL1
IOH
IOL
Gate driver High Output

Voltage Booster efficiency
VCIX2 primary booster

efficiency
Gate driver High Output
Voltage
Gate driver Low Output
Voltage
Vcom High Output Voltage
Vcom Low Output Voltage
Max. Source Voltage
Source voltage variation
Logic High Output Voltage
Logic Low Output Voltage
Logic High Input voltage
Logic Low Input voltage
Logic High Output Current
Source
Logic Low Output Current
Drain
Solomon Systech
Min
Typ
Max
Unit
1.4
3.6
1.4
3.6
2.5 or
VDDIO
whichever
is higher
3.6
88
90
82
84
83
85
15
-15
-7
-VCIM+0.5
-2
0.9* VDDIO
0
0.8*VDDIO
0
5
5
2
VDDIO
0.1*VDDIO
VDDIO
0.2*VDDIO
V
V
V
%
V
V
V
V
Vout = VDDIO-0.4V
50
Vout = 0.4V
-50
No panel loading; 4x or 5x
booster; ITO for CYP, CYN,
VCIX2, VCI and VCHS = 10
Ohm
No panel loading; 6x booster;
ITO for CYP, CYN, VCIX2, VCI
and VCHS = 10 Ohm
No panel loading, ITO for CYP,
CYN, VCIX2, VCI and VCHS =
10 Ohm
Iout=-100A
Iout=100A
Apr 2007 P 60/82
Rev 1.3
SSD1289
IOZ
IIL/IIH
CIN
fDOTCLK
RSON
RGON
RCON
Idp(262k)
Logic Output Tri-state Current

Drain Source
Logic Input Current
Logic Pins Input Capacitance
DOTCLK frequency
Source drivers output
resistance
Gate drivers output resistance
Vcom output resistance
Display current for 262k
Idp(8 color)
Display current for 8 color

mode
Islp
Sleep mode current
-1
-1
1
1
7.5
8.22
A
pF
MHz
500
200
Ivdd
150
300
uA
Ivci
2.5
mA
Ivdd
120
300
Ivci
mA
Ivdd
30
100
Ivci
40
200
Display is ON
Vddio=Vddext = 1.8V,
Vci = 2.8V. 5x/-5x
booster ratio. Full color
current consumption,
without panel loading
Current consumption for
8 color partial display,
without panel loading
Oscillator off, no
source/gate output, Ram
read write halt. Send
command R10-0001
(sleep mode), R00-0000
(stop osc)
Remark: Ivdd = Ivddio + Ivddext
SSD1289
Rev 1.3
P 61/82
Apr 2007
Solomon Systech
13 AC CHARACTERISTICS
Table 13-1 Parallel 6800 Timing Characteristics (TA = -20 to 70C, VDDIO = 1.4V to 3.6V, VDDEXT = 1.4V 1.95V,
REGVDD=L)
Symbol
tcycle
tcycle
tAS
tAH
tDSW
tDHW
tACC
tOH
PWCSL
PWCSH
PWCSL
PWCSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Clock Cycle Time (read cycle)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Output Hold time
Pulse width /CS low (write cycle)
Pulse width /CS high (write cycle)
Pulse width /CS low (read cycle)
Pulse width /CS high (read cycle)
Rise time
Fall time
Min
Typ
Max
100
1000
0
0
5
5
250
100
50
50
500
500
-
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tAH
R/W
tcycle
PWCSL
CS
PWCSH
tR
tF
E
tDHW
tDSW
D0~D17(WRITE)
Valid Data
tACC
D0~D17(READ)
Valid Data
tOH
Figure 13-1 Parallel 6800-series Interface Timing Characteristics
Solomon Systech
Apr 2007 P 62/82
tOH
Rev 1.3
SSD1289
Table 13-2 Parallel 8080 Timing Characteristics
(TA = -20 to 70C, VDDIO = 1.65V to 3.6V, VDDEXT = 1.65V to 1.95V, REGVDD = L)
Symbol
tcycle
tcycle
tAS
tAH
tDSW
tDHW
tACC
tOH
WH
PWL
PWH
PWL
PWH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Clock Cycle Time (read cycle)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Output Hold time
Width high
Pulse Width low (write cycle)
Pulse Width high (write cycle)
Pulse Width low (read cycle)
Pulse Width high (read cycle)
Rise time
Fall time
Min
Typ
Max
100
1000
0
0
5
5
250
100
20
50
50
500
500
-
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
(Case 1)
D/C
tAH
tAS
WH
CS
tcycle
PWL
WR
tR
tF
RD
PWH
tDHW
tDSW
D0~D15(WRITE)
Valid Data
Write Cycle
(Case 2)
D/C
tAH
tAS
WR
WH
tcycle
PWL
CS
tDSW
D0~D15(WRITE)
SSD1289
tR
tF
RD
Rev 1.3
PWH
tDHW
Valid Data
P 63/82
Apr 2007
Solomon Systech
Read Cycle
(Case 1)
D/C
tAH
tAS
CS
tR
tF
tcycle
WR
PWH
PWL
RD
tACC
D0~D7(READ)
Valid Data
Read Cycle
(Case 2)
D/C
tAH
tAS
RD
tR
tF
tcycle
WR
PWH
PWL
CS
tACC
D0~D7(READ)
Valid Data
tOH
Figure 13-2 Parallel 8080-series Interface Timing Characteristics
Solomon Systech
Apr 2007 P 64/82
Rev 1.3
SSD1289
Table 13-3 - Serial Timing Characteristics

(TA = -20 to 70C, VDDIO = 1.65V to 3.6V, VDDEXT = 1.65V to 1.95V, REGVDD = L)
Symbol
tcycle
fCLK
tAS
tAH
tCSS
tCSH
tDSW
tOHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Serial Clock Cycle Time
SPI Clock tolerance = +/- 2 ppm
Register select Setup Time
Register select Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise time
Fall time
Min
Typ
Max
77
Unit
ns
13
MHz
4
5
2
10
5
10
38
38
-
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAS
tCSS
CS
tAH
tCSH
tcycle
tCLKL
SCK
tR
tDHW
tF
tDSW
SDI
tCLKH
Valid Data
CS
SCK
D7
SDI
D6
D5
D4
D3
D2
D1
D0
Figure 13-3 4 wire Serial Timing Characteristics
SSD1289
Rev 1.3
P 65/82
Apr 2007
Solomon Systech
Figure 13-4 - Pixel Clock Timing in RGB interface mode

tvsys
tvsyh
VSYNC
thsys
thsyh
HSYNC
thv
tDOTCLK
DOTCLK
tCKL
tds
tCKH
tdh
Pixel
Data
Characteristics
DOTCLK Frequency
DOTCLK Period
Vertical Sync Setup Time
Vertical Sync Hold Time
Horizontal Sync Setup Time
Horizontal Sync Hold Time
Phase difference of Sync Signal
Falling Edge
DOTCLK Low Period
DOTCLK High Period
Data Setup Time
Data hold Time
Solomon Systech
Symbol
fDOTCLK
tDOTCLK
tvsys
tvsyh
thsys
thsyh
Min
122
20
20
20
20
Typ
5.5
182
-
Max
8.22
-
Units
MHz
nSec
nSec
nSec
nSec
nSec
thv
240
tDOTCLK
tCKL
tCKH
tds
tdh
61
61
40
40
nSec
nSec
nSec
nSec
Apr 2007 P 66/82
Rev 1.3
SSD1289
Figure 0-5 - Pixel Clock Timing in RGB interface mode
Hcycle = 280
tHBP = 30
HDISP = 240
tHFP = 10
DOTCLK
HYSNC
DEN
Pixel
Data
Dummy
D0
D1
D2
Dummy
D328 D239 D240
a) Horizontal Data Transaction Timing

Vcycle = 326 Lines
tVBP = 4
VYSNC
tVFP = 2
VDISP = 320 Lines
HSYNC
Line 0
Line 319
DEN
b) Vertical Data Transaction Timing
Characteristics
DOTCLK Frequency
DOTCLK Period
Horizontal Frequency (Line)
Vertical Frequency (Refresh)
Horizontal Back Porch
Horizontal Front Porch
Horizontal Data Start Point
Horizontal Blanking Period
Horizontal Display Area
Horizontal Cycle
Vertical Back Porch
Vertical Front Porch
Vertical Data Start Point
Vertical Blanking Period
Vertical Display Area
Vertical Cycle
SSD1289
Rev 1.3
P 67/82
Symbol
fDOTCLK
tDOTCLK
fH
fV
tHBP
tHFP
tHBP
tHBP + tHFP
HDISP
Hcycle
tVBP
tVFP
tVBP
tVBP + tVFP
VDISP
Vcycle
Apr 2007
Min
122
-
Typ
5.5
182
19.6
60
30
10
30
40
240
280
4
2
4
6
320
326
Max
8.22
29.3
90
-
Unit
MHz
nSec
kHz
Hz
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
Line
Line
Line
Line
Line
Line
Solomon Systech
14 GDDRAM ADDRESS
TB=1
G0
G1
G2
G3
G4
.
.
.
G316
G317
G318
G319
RL=1
S0
S1
S2
S3
S4
S5
S6
S7
S8
RL=0 S719 S718 S717 S716 S715 S714 S713 S712 S711
BGR=0 R
G
B
R
G
B
R
G
B
BGR=1 B
G
R
B
G
R
B
G
R
TB=0
0000H,0000H
0000H, 0001H
0000H, 0010H
G319
0001H,0000H
0001H, 0001H
0001H, 0010H
G318
0010H,0000H
0010H, 0001H
0010H, 0010H
G317
0011H,0000H
0011H, 0001H
0011H, 0010H
G316
0100H,0000H
0100H, 0001H
0100H, 0010H
G315
.
.
.
.
.
.
.
.
.
.
.
.
013CH, 0000H
013CH, 0001H
013CH, 0010H
G3
013DH, 0000H
013DH, 0001H
013DH, 0010H
G2
G1
013EH, 0000H
013EH, 0001H
013EH, 0010H
G0
013FH, 0000H
013FH, 0001H
013FH, 0010H
Horizontal address
Remark :
S714 S715 S716 S717 S718 S719

S5
S4
S3
S2
S1
S0
R
G
B
R
G
B
B
G
R
B
G
R
.
.
.
0000H, 00EEH
0001H, 00EEH
0010H, 00EEH
0011H, 00EEH
0100H, 00EEH
0000H, 00EFH
0001H, 00EFH
0010H, 00EFH
0011H, 00EFH
0100H, 00EFH
.
.
.
013CH, 00EEH
013DH, 00EEH
013EH, 00EEH
013FH, 00EEH
.
.
.
013CH, 00EFH
013DH, 00EFH
013EH, 00EFH
013FH, 00EFH
238
239
Vertical
address
0
1
2
3
4
.
.
.
316
317
318
319
The address is in 00xxH,0yyyH format, where yyy is the vertical address and xx is the horizontal address
Solomon Systech
Apr 2007 P 68/82
Rev 1.3
SSD1289
15
INTERFACE MAPPING
15.1 Interface Setting

Table 15-1: Interface setting and data bus setting
PS3 PS2 PS1 PS0 Interface Mode
1
1
1
1 3-wire SPI
1
1
1
0 4-wire SPI
1
0
1
1 16-bit 6800 parallel interface
1
0
1
1
0
0
1
0
0
0
1
1
1 18-bits 6800 parallel interface
0
1
1
0 9-bits 6800 parallel interface
0
1
0
0
1
0
0
0
1
1 Reserved
0
0
1
0 Reserved
0
0
0
1 18-bit RGB interface + 4-wire SPI
15.1.1
Data bus
D[17:10], D[8:1]
D[8:1]
D[17:10], D[8:1]
D[8:1]
D[17:0]
D[8:0]
D[17:0]
D[8:0]
Reserved
Reserved
D[17:0],
6800-series System Bus Interface
E
/CS
D/C
MPU
R/W
SSD1289
D[17:0]
18/16/9/8
Table 15-2 The Function of 6800-series parallel interface

PS3 PS2 PS1 PS0
1
Interface Mode
Data bus
1
0
D[17:10],
D[8:1]
D[8:1]
D[17:0]
0
D[8:0]
R/W
D/C
/CS
Read 8-bit command
Operation
Read 8-bit parameters or status*
Write 8-bit command
Write 16-bit display data
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
* A dummy read is required before the first actual display data read
SSD1289
Rev 1.3
P 69/82
Apr 2007
Solomon Systech
15.1.2
8080-series System Bus Interface

/RD
/CS
D/C
MPU
SSD1289
/WR
D[17:0]
18/16/9/8
Table 15-3 Interface Mode Selection

PS3 PS2 PS1 PS0
1
Interface Mode
D[8:1]
1
D[17:10],
D[8:1]
0
Data bus
D[17:0]
0
D[8:0]
/WR
/RD
D/C
/CS
Read 8-bit command
Operation
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
Read 8-bit command
Write 8-bit command
* A dummy read is required before the first actual display data read
15.1.3
Generic Bus Interface
DEN
DOTCLK
HSYNC
MPU
VSYNC
SSD1289
D[17:12] / RR[5:0]
D[11:6] / GG[5:0]
D[5:0] / BB[0:5]
18-/16-/6-bit
Solomon Systech
Apr 2007 P 70/82
Rev 1.3
SSD1289
15.2 Mapping for Writing an Instruction
Interface
18 bits
16 bits
9 bits
8 bits
Cycle D17 D16 D15 D14 D13 D12 D11

1st
2nd
1st
2nd
Remark :
Hardware pins
D10 D9
D8
D7
D6
D5
D4
D3
IB8
x
IB8
IB7
IB6 IB5 IB4 IB3 IB2
IB7
IB6 IB5 IB4 IB3 IB2
D2
IB1
IB1
IB9
IB1
IB9
IB1
D1
IB0
IB0
IB8
IB0
IB8
IB0
D0
x
x
x
Don't care bits

Not connected pins
15.3 Mapping for Writing Pixel Data
Interface
18 bits
16 bits
9 bits
8 bits
Color mode Cycle D17

262k
R5
st
1
R5
nd
2
B5
rd
3
G5
st
262k
1
R5
nd
2
x
st
1
R5
nd
2
B5
65k
R4
st
1
262k
nd
2
st
1
nd
262k
2
rd
3
st
1
65k
nd
2
D16
R4
R4
B4
G4
R4
x
R4
B4
R3
Remark :
Don't care bits

Not connected pins
D15
R3
R3
B3
G3
R3
x
R3
B3
R2
D14
R2
R2
B2
G2
R2
x
R2
B2
R1
D13
R1
R1
B1
G1
R1
x
R1
B1
R0
Hardware pins
D12 D11 D10 D9 D8 D7
R0 G5 G4 G3 G2 G1
R0 x
x
G5 G4
B0 x
x
R5 R4
G0 x
x
B5 B4
R0 x
x
G5 G4
x
x
x
B5 B4
R0 x
x
G5 G4
B0 x
x
x
x
G5 G4 G3
G2 G1
R5 R4
G2 G1
R5 R4
G5 G4
B5 B4
R4 R3
G2 G1
D6
G0
G3
R3
B3
G3
B3
G3
x
G0
R3
G0
R3
G3
B3
R2
G0
D5 D4 D3
B5 B4 B3
G2 G1 G0
R2 R1 R0
B2 B1 B0
G2 G1 G0
B2 B1 B0
G2 G1 G0
x
x
x
B4 B3 B2
R2 R1 R0
B5 B4 B3
R2 R1 R0
G2 G1 G0
B2 B1 B0
R1 R0 G5
B4 B3 B2
D2 D1
B2 B1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B1 B0
G5 G4
B2 B1
x
x
x
x
x
x
G4 G3
B1 B0
D0
B0
G3
B0
15.4 Mapping for Writing Pixel Data in generic mode

Hardware pins
Interface
Color mode
18-bit RGB
262k
D17
D16 D15
D14
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
If displaying 65K color in generic mode, interface mode selection should be set to 18-bit RGB
Interface. The RR0 and BB0 are suggested to connect to RR5 and BB5 representively.
SSD1289
D0
RR5 RR4 RR3 RR2 RR1 RR0 GG5 GG4 GG3 GG2 GG1 GG0 BB0 BB1 BB2 BB3 BB4 BB5
Rev 1.3
P 71/82
Apr 2007
Solomon Systech
DISPLAY SETTING SEQUENCE

15.5 Display ON Sequence
Power supply setting
Set R07h at 0021h

GON = 1
DTE = 0
D[1:0] = 01
Set R00h at 0001h
Set R07h at 0023h

GON = 1
DTE = 0
D[1:0] = 11
Set R10h at 0000h

Exit sleep mode
Wait 30ms
Set R07h at 0033h

GON = 1
DTE = 1
D[1:0] = 11
Entry Mode setting (R11h)
LCD driver AC setting (R02h)
RAM data write (R22h)
Display ON
and start to write RAM
Solomon Systech
Apr 2007 P 72/82
Rev 1.3
SSD1289
15.6 Display OFF Sequence
Display ON
Set R07h at 0000h

Halt the operation
Set R00h at 0000h

Turn off oscillator
Set R10h at 0001h

Enter sleep mode
Wait unit VGH < 5V
Remove power from VDDEXT and VCI, then remove VDDIO
Display OFF
VGH
VCIX2
/RES
VCI / VDDEXT
VDDIO
Note:
1. VDDIO should be the last to fall, or VCI/VDDEXT/VDDIO could be power off at the same time
2. If OTP is active in the application, the OTP programming voltage should be turned off and capacitors at VGH and VCIX2 discharged before
VCI/VDDEXT/VDDIO are turned off.
SSD1289
Rev 1.3
P 73/82
Apr 2007
Solomon Systech
15.7 Sleep Mode Display Sequence
Display ON
Set R10h at 0001h
Ivci = 66uA
Sleeping
Release from Sleep

Set R10h at 0000h
Display ON
Solomon Systech
Apr 2007 P 74/82
Rev 1.3
SSD1289
16 POWER SUPPLY BLOCK DIAGRAM
VCOM
VCIM
VGH
VGL
VCOMH VCOML VGOFFH
VGOFFHL
VLCD63
S0 to S719
VCIX2/G/J
VDDEXT
VCI
Regulator Circuit &
VCOM Generator Circuit
VCIP
Source
driver
VSS/VSSRC/
AVSS/VCHS
CXP
Booster
Circuit
CXN
CYP
&
CYN
VLCD63
Regulator
Circuit
Supply Voltage
Regulator
Circuit
CP
CN
Gamma /
Grayscale
Voltage
Generator
Switches
Network
Data
Latches
C1P
C2P
G0 to G319
GTESTL, GTESTR
C1N
GDDRAM
Gate Driver
C2N
C3P
OSC /
Timing
Generator
C3N
REGVDD
VRAM/
VREGR
Address
Counter
System Interface / RGB interface / Control Logic
SSD1289
Rev 1.3
P 75/82
Apr 2007
EXTCLK
GD
BGR
CM
RL
TB
VSYNC
HSYNC
DOTCLK
DEN
D[0-17]
D/C
R/W
CS
PS0-3
RES
WSYNC
VCORE/
VREGC
REV
SHUT
VDDIO
Solomon Systech
17 SSD1289 OUTPUT VOLTAGE RELATIONSHIP
VGH (9~15V)
VLCD63 (max 5.5V)

VCOMH (max 5V)
VCI (2.5~3.6V)
VCOM amplitude
(max 5.5V)
VSS
VCOML
VGOFFH
VGL (-7~-15V)
Solomon Systech
Apr 2007 P 76/82
Rev 1.3
SSD1289
18 APPLICATION CIRCUIT
Figure 18-1 - Booster Capacitors
C1P
C1N
C2P
C2N
C3P
C3N
CXP
CXN
CYP
CYN
CP
CN
+16V
+16V
+16V
+16V
+16V
+16V
-
All capacitors
0.1 ~ 0.22uF
Figure 18-2 Filtering and charge sharing capacitors
VCIX2
VCIX2G
6.3V
VCIX2J
VCIM 6.3V
CDUM0 6.3V
CDUM1 6.3V
16V
VGH
16V
VGL
VCI
VCIP
VSS
+
+
+
+
-
VCIX2 should be separated with VCIX2G/VCIX2J at ITO

layout to provide noise free path.
VCI should be separated with VCIP at ITO layout to provide
noise free path.
VSS should be separated with VCHS, AVSS and VSSRC at
ITO layout to provide noise free path.
6.3V
6.3V
VGOFFH 16V
VCORE 6.3V
VRAM 6.3V
6.3V
VCOMH
6.3V
VCOML
6.3V
VLCD63
Capacitor for VCIX2 / VCIX2G / VCIX2J = 3.3uF ~ 4.7uF.

Capacitor for VCI = 4.7uF
All other capacitors 1.0uF ~ 2.2uF.
2.2uF is preferred for better display and power consumption.
Capacitors on VGOFFH, VGOFFHL are for Cs on gate
application. Leave them open for Cs on COM application.
Capacitors on CDUM0 and CDUM1 are for power saving.
+
+
+
+
Panel FPC
VCI
16V
VGOFFHL +
Panel
VCOM
VCIX2
VCIX2J
VCIX2G
FPC
VCIP
3.3uF
4.7uF
VCI
1uF
VSS
AVSS
VSSRC
VCHS
VSS
SSD1289
Rev 1.3
P 77/82
Apr 2007
Solomon Systech
Figure 18-3 Power supply pin connection
3.6V System Vdd > 1.95V,

1.65V System Vdd > 1.4V
1.95V System Vdd > 1.65V
VDDEXT
System
Vdd
VDDEXT
VDDIO
System
Vdd
REGVDD
VDDIO
VCORE,
VREGC
VCORE,
VREGC
VRAM,
VREGR
Vci
VCI
VCIP
VSS
Solomon Systech
VRAM,
VREGR
Vci
VCI
VCIP
REGVDD
VSS
Apr 2007 P 78/82
Rev 1.3
SSD1289
SSD1289
Rev 1.3
P 79/82
Apr 2007
HSYNC
VSYNC
DOTCLK
DEN
Hardware
Setting Pins
Dump driver
interface
RES
CS
E
D/C
R/W
D0-D17
External component
pins
G0-G319
SHUT
CM
BGR
REV
CAD
TB
RL
GD
MCU serial interface

and control
Refer to figure 3-5
Power/Ground
VCI / VSS
AVSS / DVSS
VDDIO
VDDEXT
Figure 18-4 Panel Connection Example
240RGB x 320 TFT Panel

(Cs on Common)
320
720
S0-S719
VCOM
SSD1289
Solomon Systech
Figure 18-5 - ITO and FPC connection example
Operating conditions:
z
1.65V < System VDD < 1.95V
z
CS on common structure
FPC
Suggested max
panel ITO
resistance (ohm)
TFT Panel
VCOM
20
VGH
20
C2P
20
C2N
20
C1P
20
C1N
10
CP
10
CN
20
C3P
20
C3N
VCI
20
5
These pins could be

connected to 1 or 0
on FPC
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
(Optional)
Test pad: TESTA,
TESTB, TESTC
Separate VSSRC from VSS

to provide noise free
path
100
100
100
100
100
100
100
VGL
VCHS
SPID
CAD
REV
GAMAS0
GAMAS1
GAMAS2
BGR
TB
RL
REGVDD
PS2
PS1
PS0
PS3
SHUT
CM
/RES
VSYNC
HSYNC
DOTCLK
DEN
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
/RD
/WR
DC
SDO
SDI
SCK
/CS
WSYNC
TESTA
TESTB
TESTC
EXTCLK
20
VREGC
VCORE
20
VREGR
VRAM
20
VDDEXT
10
VSSRC
20
CDUM0
20
CDUM1
10
VSS
10
AVSS
20
VDDIO
VCI
VCIP
VGGOFFHL
Separate VCIP from VCI

to provide noise free
path
Remarks: pin name admentment from previous datasheet version

VCORE is identical to VDD
VREGC is identical to LVVDD
VRAM is identical to VDDRAM
VREGR is identical to LVVDDR
10
VLCD63
10
VCOML
10
VCOMH
10
VCIM
VCI
VCIX2J
VCIX2G
VCIX2
CYP
CYN
VCHS
10
CXN
10
CXP
VGOFFH
VCOM
VCOMR
Solomon Systech
Apr 2007 P 80/82
Rev 1.3
SSD1289
19 PACKAGE INFORMATION
19.1 DIE TRAY DIMENSIONS
SSD1289
Rev 1.3
P 81/82
Apr 2007
Solomon Systech
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical
parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support
or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
http://www.solomon-systech.com
Solomon Systech
Apr 2007 P 82/82
Rev 1.3
SSD1289

Datasheet Controlador de Display LCD TFT SSD1289

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Datasheet Controlador de Display LCD TFT SSD1289

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SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

Copyright 2007 Solomon Systech Limited

GENERAL DESCRIPTION ......................................................................................... 5

Gold Bump Die

System Interface / RGB Interface

DIE PAD FLOOR PLAN

Output Pad Pitch (Gate and source):

23.984 x 1.600 mm2

Table 5-1 - SSD1289 Bump Pad Coordinate (Bump Center)

Apr 2007 P 10/82

Apr 2007 P 12/82

Apr 2007 P 14/82

Apr 2007 P 16/82

Table 6-1: Power Supply Pins

System ground pin of the IC.

Negative voltage of VCI.

A positive power output pin for gate driver.

This pin is the maximum source driver voltage.

A negative power output pin for gate driver.

- Connect a capacitor to VCOM if Cs on gate application.

- Connect a capacitor to CXN

- Connect a capacitor to C2N

- Connect a capacitor to C3N

- Connect a capacitor to VSS

- Connect a capacitor to VSS

Input pin to enable internal vdd regulation.

Regulator output for VCORE use.

Vdd for RAM use. Connect a capacitor for stabilization

Regulator output for RAM use.

Voltage input pin for internal logic, connect to system VDD.

Voltage input pin for logic I/O, connect to system VDD.

Table 6-2 - Interface Logic Pins

80-system : WR (write strobe signal)

Ram Write Synchronization output

System reset pin.

Chip select pin of serial interface.

Clock pin of serial interface.

Data input pin in serial mode.

Data output pin in serial mode.

Apr 2007 P 18/82

Table 6-3: Mode Selection Pins

Gamma selection pin. This pin should be connected to VDDIO / VSS

Gamma selection pin. This pin should be connected to VDDIO / VSS

Table 6-4: Driver Output Pins

A power supply for the TFT-display common electrode.

Table 6-5: Miscellaneous Pins

These pins must be left open and cannot be connected together

Apr 2007 P 20/82

BLOCK FUNCTION DESCRIPTION

MPU Parallel 6800-series Interface

write column address

Figure 7-1 Read Display Data

b) MPU Parallel 8080-series Interface

MPU 4-lines Serial Peripheral Interface

d) MPU 3-lines Serial Peripheral Interface

6800 series Parallel

8080 series Parallel

MCU Serial Interface

Table 7-1 - Data bus selection modes

Address Counter (AC)

Graphic Display Data RAM (GDDRAM)