Study of Advanced Topic, Abstract-1.

Date: 26/08/2013

PAPER TITLE: FinFET A Self-Aligned Double-Gate MOSFET Scalable to 20 nm. AUTHORS: Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano,Charles Kuo, Erik Anderson, Tsu-Jae King, Jerey Bokor and Chenming Hu. JOURNAL: IEEE Transactions on Electron Devices. VOL:47. Year: December, 2000. ABSTRACT: This paper enumerates the device fabrication and characterization of the double gate MOSFET commonly known as FinFET. The introduction section indicates the problems encountered in the working of conventional MOSFETs sized below 50nm and SOI-MOSFETs(Silicon On Insulator-MOSFET).The conventional MOSFETs suer from short channel eect when sized below 50nm and The SOI-MOSFETs have high parasitic resistance. The proposed solution for the aforementioned problems is the FinFET device which is based on the DELTA(fully DEpleted Lean channel TrAnsistor) structure. The second section of the paper gives a detailed fabrication process of the device and in-situ measurements carried out. The base material is a thick Si lm(50nm) on which a buried oxide layer (400nm) had been used. On this layer a very thin( 10nm) Si layer(n) had been grown. This is the rst Gate electrode. By using CVD (Chemical Vapour Deposition) technique, a layer of Si3 N i4 and SiO2 had been deposited on the Si-n so as to protect it from the fabrication processes. The Si-n had been patterned using Electron Beam (EB) lithography. After this step the Source/Drain regions had been formed by depositing a Phosphorus doped amorphous Si on the thin Si-n, with a small gap in between them(by EB lithography) to separate the source and drain regions. After this, by CVD, SiO2 spacers had been deposited around the source and drain regions. The spacers around the Si-n had been removed by over etching. After this step, a very thin layer of gate-oxide SiO2 had been grown on the exposed side walls of the Si-n by dry oxidation, during which the amorphous phosphorus doped Si source/drain region become crystalline. Perpendicular to source/drain and Si-n layer along the gap where the, a Boron doped Si0.4 Ge0.6 layer had been deposited and patterned to form the Gate terminal. The thickness of the various layers had been measured using Ellipsometry and their structures had been visualised by SEM(Scanning Electron Microscopy). The fabrication process is similar to that of MOSFET but it is quasi-planar, as the source/drain and second gate regions are elevated from the Si-n structure. The last 2 sections discuss the various characteristics obtained by probing and testing the devices fabricated for n widths from 20-40nm and gate length from 17nm-50nm. The characteristics include drain current Id w.r.to gate to source voltage Vgs and drain to source voltage Vds . These are similar to conventional MOSFETs. The reduced subthreshold leakage current can be clearly observed from Id v/s Vgs plot, which indicates reduced short channel eect. Threshold voltage Vt , an important parameter, can be controlled by varying the Gate length has been studied. The variation in the transconductance Gm has been plotted for dierent n-widths. The self-alignment of the Gate has been veried by measuring eective drain bias and gate bias voltages, due to which the parasitic resistance is reduced. A 5-n FinFET has been fabricated which has higher current driving capability than the single-n FinFET. The results as given in the paper indicate that FinFET can be a successor to MOSFET.