EL5473 Introduction to VLSI Design

Instructor: N. Sertac Artan Course Syllabus

Course Description
This course covers CMOS processing technology, MOS transistor theory, static/dynamic circuit and logic design techniques, circuit performance estimation, standard cells and gate arrays, clocking strategies, input/output structures, datapath, memory and control logic design. Advanced VLSI CAD tools are used for schematic capture, layout, timing analysis and simulations for functionality and performance.

Contact Info:
Oce: 10.069 (2MTC) Tel: (718) 260-3496 E-mail: artan at poly edu Homepage: http://eeweb.poly.edu/artan Oce Hours: Wednesdays, 1:00 pm 3:00 pm. Contact Preference: Please, try to utilize oce hours for most if not all of your questions. Use email only for quick questions (e.g., Do we need a calculator for tomorrows exam?). If you are not available at my oce hours, please, send me an email for an appointment at least two days before your desired appointment date.

Teaching Assistants:
Ken Chiang and Zhendong Eric Xu Oce: 10.067 (2MTC), E-mail: cchian05, zx327 at students poly edu Oce Hours: TBA

Prerequisites
* CS2204: Digital Logic and State Machine Design, or equivalent. * EE3114: Fundamentals of Electronics I or equivalent.

Time and Venue

Class meets: Wednesdays 6:00 8:30 pm @ RH 215 Exam/Presentation Schedule: Midterm: October 30th , Wednesday. Project Presentations: TBA. Final: TBA

Grading Grading Components Quizzes (Wed. 6 pm) Exam 1 (Midterm) Exam 2 (Final) Homeworks Projects % 10% 20% 20% 20% 30%

Quizzes
There will be a short (10-20 min), 1-2 question (fact check, problem, design, or programming) quiz most Wednesdays at 6 pm covering the previous class material. The quizzes will be closed-book, but calculators will be permitted: There will be no make-up exam for the quizzes.

Homeworks and Projects

4 students/group There will be about 5 homeworks (some of the homeworks will be assigned per student, some per group). Late submission: -25 points/day. 2

 Project topics will be announced around mid-semester. Grading components: Report, presentation, design. Register your group at my.poly by next Friday (9/13).

Exams
4 5 questions. 90 120 mins. Open (paper) book. Calculators will be permitted (no cell phones, or other electronics)

Class Website
All class material will be posted to my.poly.

References
Textbook
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition) by Neil Weste and David Harris (4th Edition) http://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321547748

Other References
CMOS Circuit Design, Layout, and Simulation, 3rd Edition by Jacob Baker http://www.amazon.com/Circuit-Simulation-Edition-Microelectronic-Systems/dp/0470881321

Digital VLSI Chip Design with Cadence and Synopsys CAD Tools by Erik Brunvand http://www.amazon.com/Digital-Design-Cadence-Synopsys-Tools/dp/0321547993

Digital Integrated Circuits (2nd Edition) by Jan Rabaey http://www.amazon.com/Digital-Integrated-Circuits-2nd-Edition/dp/0130909963

Software
Toolchain: We will be using Cadence tools.