Tutorial 3 Solutions

1. (Reference: Pages 1-11, 1-28, 1-29 of 8085 datasheet) Mnemonic code: MOV A, B ADD C MOV D, A Sequence of operations: Read register B: Contents of register B are placed on the data bus Write accumulator: Contents on the data bus are written on the accumulator Read register C: Contents of register C are placed on the data bus Write temporary register: Contents of data bus are written on the temporary register Addition of accumulator and temporary register using ALU and result is stored in accumulator Read accumulator: The stored result in accumulator A is read and placed on the data bus Write register D: The result on the data bus is written to register D

2. The two requirements of the PWM signal are: 1) Frequency of 125kHz: To obtain a clock frequency of 125kHz, it is necessary to reduce bus clock frequency by a factor of 16. Frequency reduction takes place in two stages: first in the prescaler, where the bus clock is stepped down to source clocks (A or B). This is done by writing the PWMPRCLK register (refer page 738). Further, the source clock frequency is stepped down to PWM output channel frequency. This is done by writing the PWMPERx register (refer page 753). 2) Duty cycle of 25%: Duty cycle = [(PWMPERx PWMDTYx)/PWMPERx]*100%. Therefore, for 25% duty cycle, we need, PWMPERx PWMDTYx = 0.25PWMPERx Therefore, PWMDTYx = 0.75PWMPERx To achieve 25% duty cycle, we will need PWMPERx = 4 and PWMDTYx = 3. Thus, clock A is scaled by 4 times to channel 0 (say). Therefore, a prescaling factor of 4 is needed. This can be adjusted setting PWMPRCLK = 0000 0010

Thus, the instruction set becomes, PWME = 0000 0001 % set channel 0 enabled PWMCLK = 0000 0000 % clock A is source of PWM channel 0 PWMPOL = 0000 0000 % polarity 0: pwm pulse start with level low and then goes hi PWMPRCLK = 0000 0010 % Combination of this and PWMPR0 would set pwm freq % here reduction by factor of 4 is achieved PWMCAE = 0000 0000 % left aligned output mode for channel 0 (actually all) PWMPER0 = 0000 0100 % Value 4 to have period reduction by another factor 4 and at % the same time achieve the duty cycle as mentioned above PWMDTY0 = 0000 0011 % To achieve 50% duty cycle Notes: 1) The actual denotation may change depending on the compiler software you choose. The values to be written to the registers, however, remain the same. 2) In actual implementation, all registers will have standard values of 0000 0000. These are, however, specified here only since the values are required in the respective formulae. 3) Note that not all registers specified in the datasheet are used. This is because, some registers, like those concerning clocks SA and SB are not required.

3. (Reference: Pages 1-28, 1-29 of 8085 datasheet) The program proceeds in a loop executing the following steps Value of register pair DE is decremented by 1 Contents of register D are moved to the accumulator (higher order byte of pair DE) The value stored in the accumulator is incremented (D+1) Value stored in the accumulator A is OR-ed with register E bitwise and result is stored in A In short, the program executes A= (D+1) OR E, in an infinite loop every time decreasing value of the pair DE by 1. (NOTE : This program does not do anything useful/meaningful for any applications but is meant just to understand how things would work)

4. Microinstruction required to be executed and the various stages are as follows 1) (MA) (PC) 2) (IR) M[MA]; (PC) (PC) + 1

3) (MA) (PC) 4) (T) M[MA]; 5) (MA) (PC) 6) (W) M[MA]; 7) (AL) (W) 8) (B) (T) + (AL); 9) (MA) (B) 10) (AL) M[MA]

(PC) (PC) + 1 (PC) (PC) + 1

1,2 are instruction fetch operation to fetch instruction from memory in register IR. 3,4 read the second byte (immediately after the instruction) from memory and store it in register T. 5,6 read the third byte from memory and store it in register W. contents of W are moved to AL (Note: we could have directly had the contents of memory moved to AL as well. State definitions would change accordingly). 8 moves the addition of T and AL (carried out by ALU) to register B. Finally B is set as memory address MA and contents of Memory at this address are transferred to register AL in 10. Note: THIS IS NOT THE UNIQUE SOLUTION. YOU CAN HAVE YOUR OWN SEQUENCE AND THE NEW STATES DEFINED SO AS TO FINALLY ACHIEVE THE OPERATION WITH ARCHITECTURE GIVEN (EXCEPT FOR THE CHANGE IN STATES)

5. (Reference: Pages 1-28, 1-29 of 8085 datasheet) Mnemonic code: MOV D, M MOV B, M MOV C, M MOV A, D ANA B ANA C MOV E, A MOV A, D XRA B XRA C ORA E Assembly code: 01010110 01000110 01001110

//Move value of variable A in memory to register D //Move value of variable B in memory to register B //Move value of variable C in memory to register C //Move variable A to accumulator //AND accumulator with B to get A.B in accumulator //AND accumulator with B to get A.B.C in accumulator //Store A.B.C in accumulator to register E //Move variable A to accumulator //XOR accumulator with B to get A B in accumulator //XOR accumulator with C to get A B C in accumulator //OR accumulator with E = A.B.C to get Y in accumulator

01111010 10100000 10100001 01011111 01111010 10101000 10101001 10110011 NOTE: YOU MAY SIMPLIFY EXPRESSION (OR MAKE IT MORE COMPLEX) AND IMPLEMENT IT IN A DIFFERENT WAY AS WELL.